463aa6d49d
arch/alpha/alpha_linux_process.cc:
Added using directive for AlphaISA namespace
arch/alpha/alpha_memory.hh:
arch/alpha/isa/branch.isa:
cpu/pc_event.hh:
Added typedefs for Addr
arch/alpha/alpha_tru64_process.cc:
arch/alpha/arguments.cc:
Added using directive for AlphaISA
arch/alpha/ev5.hh:
Added an include of arch/alpha/isa_traits.hh, and a using directive for the AlphaISA namespace.
arch/alpha/faults.hh:
Added a typedef for the Addr type, and changed the formatting of the faults slightly.
arch/alpha/isa/main.isa:
Untemplatized StaticInst, added a using for namespace AlphaISA to show up in decoder.cc and the exec.ccs, relocated makeNop to decoder.hh
arch/alpha/isa/mem.isa:
Untemplatized StaticInst and StaticInstPtr
arch/alpha/isa/pal.isa:
cpu/base_dyn_inst.cc:
Untemplatized StaticInstPtr
arch/alpha/isa_traits.hh:
Changed variables to be externs instead of static since they are part of a namespace and not a class.
arch/alpha/stacktrace.cc:
Untemplatized StaticInstPtr, and added a using directive for AlphaISA.
arch/alpha/stacktrace.hh:
Added some typedefs for Addr and MachInst, and untemplatized StaticInstPtr
arch/alpha/vtophys.cc:
Added a using directive for AlphaISA
arch/alpha/vtophys.hh:
Added the AlphaISA namespace specifier where needed
arch/isa_parser.py:
Changed the placement of the definition of the decodeInst function to be outside the namespaceInst namespace.
base/loader/object_file.hh:
cpu/o3/bpred_unit.hh:
Added a typedef for Addr
base/loader/symtab.hh:
Added a typedef for Addr, and added a TheISA to Addr in another typedef
base/remote_gdb.cc:
Added a using namespace TheISA, and untemplatized StaticInstPtr
base/remote_gdb.hh:
Added typedefs for Addr and MachInst
cpu/base.cc:
Added TheISA specifier to some variables exported from the isa.
cpu/base.hh:
Added a typedef for Addr, and TheISA to some variables from the ISA
cpu/base_dyn_inst.hh:
Untemplatized StaticInstPtr, and added TheISA specifier to some variables from the ISA.
cpu/exec_context.hh:
Added some typedefs for types from the isa, and added TheISA specifier to some variables from the isa
cpu/exetrace.hh:
Added typedefs for some types from the ISA, and untemplatized StaticInstPtr
cpu/memtest/memtest.cc:
cpu/o3/btb.cc:
dev/baddev.cc:
dev/ide_ctrl.cc:
dev/ide_disk.cc:
dev/isa_fake.cc:
dev/ns_gige.cc:
dev/pciconfigall.cc:
dev/platform.cc:
dev/sinic.cc:
dev/uart8250.cc:
kern/freebsd/freebsd_system.cc:
kern/linux/linux_system.cc:
kern/system_events.cc:
kern/tru64/dump_mbuf.cc:
kern/tru64/tru64_events.cc:
sim/process.cc:
sim/pseudo_inst.cc:
sim/system.cc:
Added using namespace TheISA
cpu/memtest/memtest.hh:
cpu/trace/opt_cpu.hh:
cpu/trace/reader/itx_reader.hh:
dev/ide_disk.hh:
dev/pcidev.hh:
dev/platform.hh:
dev/tsunami.hh:
sim/system.hh:
sim/vptr.hh:
Added typedef for Addr
cpu/o3/2bit_local_pred.hh:
Changed the include to use arch/isa_traits.hh instead of arch/alpha/isa_traits.hh. Added typedef for Addr
cpu/o3/alpha_cpu.hh:
Added typedefs for Addr and IntReg
cpu/o3/alpha_cpu_impl.hh:
Added this-> to setNextPC to fix a problem since it didn't depend on template parameters any more. Removed "typename" where it was no longer needed.
cpu/o3/alpha_dyn_inst.hh:
Cleaned up some typedefs, and untemplatized StaticInst
cpu/o3/alpha_dyn_inst_impl.hh:
untemplatized StaticInstPtr
cpu/o3/alpha_impl.hh:
Fixed up a typedef of MachInst
cpu/o3/bpred_unit_impl.hh:
Added a using TheISA::MachInst to a function
cpu/o3/btb.hh:
Changed an include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr
cpu/o3/commit.hh:
Removed a typedef of Impl::ISA as ISA, since TheISA takes care of this now.
cpu/o3/cpu.cc:
Cleaned up namespace issues
cpu/o3/cpu.hh:
Cleaned up namespace usage
cpu/o3/decode.hh:
Removed typedef of ISA, and changed it to TheISA
cpu/o3/fetch.hh:
Fized up typedefs, and changed ISA to TheISA
cpu/o3/free_list.hh:
Changed include of arch/alpha/isa_traits.hh to arch/isa_traits.hh
cpu/o3/iew.hh:
Removed typedef of ISA
cpu/o3/iew_impl.hh:
Added TheISA namespace specifier to MachInst
cpu/o3/ras.hh:
Changed include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr.
cpu/o3/regfile.hh:
Changed ISA to TheISA, and added some typedefs for Addr, IntReg, FloatReg, and MiscRegFile
cpu/o3/rename.hh:
Changed ISA to TheISA, and added a typedef for RegIndex
cpu/o3/rename_map.hh:
Added an include for arch/isa_traits.hh, and a typedef for RegIndex
cpu/o3/rob.hh:
Added a typedef for RegIndex
cpu/o3/store_set.hh:
cpu/o3/tournament_pred.hh:
Changed an include of arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef of Addr
cpu/ozone/cpu.hh:
Changed ISA into TheISA, and untemplatized StaticInst
cpu/pc_event.cc:
Added namespace specifier TheISA to Addr types
cpu/profile.hh:
kern/kernel_stats.hh:
Added typedef for Addr, and untemplatized StaticInstPtr
cpu/simple/cpu.cc:
Changed using directive from LittleEndianGuest to AlphaISA, which will contain both namespaces. Added TheISA where needed, and untemplatized StaticInst
cpu/simple/cpu.hh:
Added a typedef for MachInst, and untemplatized StaticInst
cpu/static_inst.cc:
Untemplatized StaticInst
cpu/static_inst.hh:
Untemplatized StaticInst by using the TheISA namespace
dev/alpha_console.cc:
Added using namespace AlphaISA
dev/simple_disk.hh:
Added typedef for Addr and fixed up some formatting
dev/sinicreg.hh:
Added TheISA namespace specifier where needed
dev/tsunami.cc:
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
Added using namespace TheISA. It might be better for it to be AlphaISA
dev/tsunami_cchip.cc:
Added typedef for TheISA. It might be better for it to be AlphaISA
kern/linux/aligned.hh:
sim/pseudo_inst.hh:
Added TheISA namespace specifier to Addr
kern/linux/linux_threadinfo.hh:
Added typedef for Addr, and TheISA namespace specifier to StackPointerReg
kern/tru64/mbuf.hh:
Added TheISA to Addr type in structs
sim/process.hh:
Added typedefs of Addr, RegFile, and MachInst
sim/syscall_emul.cc:
Added using namespace TheISA, and a cast of VMPageSize to the int type
sim/syscall_emul.hh:
Added typecast for Addr, and TheISA namespace specifier for where needed
--HG--
extra : convert_revision : 91d4f6ca33a73b21c1f1771d74bfdea3b80eff45
121 lines
5.1 KiB
C++
121 lines
5.1 KiB
C++
/*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __ARCH_ALPHA_EV5_HH__
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#define __ARCH_ALPHA_EV5_HH__
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#include "config/alpha_tlaser.hh"
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#include "arch/alpha/isa_traits.hh"
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namespace EV5 {
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//It seems like a safe assumption EV5 only applies to alpha
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using namespace AlphaISA;
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#if ALPHA_TLASER
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const uint64_t AsnMask = ULL(0x7f);
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#else
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const uint64_t AsnMask = ULL(0xff);
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#endif
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const int VAddrImplBits = 43;
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const Addr VAddrImplMask = (ULL(1) << VAddrImplBits) - 1;
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const Addr VAddrUnImplMask = ~VAddrImplMask;
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inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
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inline Addr VAddrVPN(Addr a) { return a >> AlphaISA::PageShift; }
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inline Addr VAddrOffset(Addr a) { return a & AlphaISA::PageOffset; }
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inline Addr VAddrSpaceEV5(Addr a) { return a >> 41 & 0x3; }
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inline Addr VAddrSpaceEV6(Addr a) { return a >> 41 & 0x7f; }
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#if ALPHA_TLASER
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inline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFF00000); }
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const int PAddrImplBits = 40;
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#else
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inline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFFF00000); }
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const int PAddrImplBits = 44; // for Tsunami
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#endif
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const Addr PAddrImplMask = (ULL(1) << PAddrImplBits) - 1;
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const Addr PAddrUncachedBit39 = ULL(0x8000000000);
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const Addr PAddrUncachedBit40 = ULL(0x10000000000);
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const Addr PAddrUncachedBit43 = ULL(0x80000000000);
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const Addr PAddrUncachedMask = ULL(0x807ffffffff); // Clear PA<42:35>
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inline Addr Phys2K0Seg(Addr addr)
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{
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#if !ALPHA_TLASER
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if (addr & PAddrUncachedBit43) {
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addr &= PAddrUncachedMask;
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addr |= PAddrUncachedBit40;
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}
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#endif
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return addr | AlphaISA::K0SegBase;
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}
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inline int DTB_ASN_ASN(uint64_t reg) { return reg >> 57 & AsnMask; }
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inline Addr DTB_PTE_PPN(uint64_t reg)
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{ return reg >> 32 & (ULL(1) << PAddrImplBits - AlphaISA::PageShift) - 1; }
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inline int DTB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; }
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inline int DTB_PTE_XWE(uint64_t reg) { return reg >> 12 & 0xf; }
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inline int DTB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; }
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inline int DTB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; }
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inline int DTB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; }
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inline int DTB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; }
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inline int ITB_ASN_ASN(uint64_t reg) { return reg >> 4 & AsnMask; }
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inline Addr ITB_PTE_PPN(uint64_t reg)
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{ return reg >> 32 & (ULL(1) << PAddrImplBits - AlphaISA::PageShift) - 1; }
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inline int ITB_PTE_XRE(uint64_t reg) { return reg >> 8 & 0xf; }
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inline bool ITB_PTE_FONR(uint64_t reg) { return reg >> 1 & 0x1; }
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inline bool ITB_PTE_FONW(uint64_t reg) { return reg >> 2 & 0x1; }
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inline int ITB_PTE_GH(uint64_t reg) { return reg >> 5 & 0x3; }
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inline bool ITB_PTE_ASMA(uint64_t reg) { return reg >> 4 & 0x1; }
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inline uint64_t MCSR_SP(uint64_t reg) { return reg >> 1 & 0x3; }
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inline bool ICSR_SDE(uint64_t reg) { return reg >> 30 & 0x1; }
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inline int ICSR_SPE(uint64_t reg) { return reg >> 28 & 0x3; }
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inline bool ICSR_FPE(uint64_t reg) { return reg >> 26 & 0x1; }
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inline uint64_t ALT_MODE_AM(uint64_t reg) { return reg >> 3 & 0x3; }
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inline uint64_t DTB_CM_CM(uint64_t reg) { return reg >> 3 & 0x3; }
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inline uint64_t ICM_CM(uint64_t reg) { return reg >> 3 & 0x3; }
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const uint64_t MM_STAT_BAD_VA_MASK = ULL(0x0020);
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const uint64_t MM_STAT_DTB_MISS_MASK = ULL(0x0010);
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const uint64_t MM_STAT_FONW_MASK = ULL(0x0008);
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const uint64_t MM_STAT_FONR_MASK = ULL(0x0004);
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const uint64_t MM_STAT_ACV_MASK = ULL(0x0002);
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const uint64_t MM_STAT_WR_MASK = ULL(0x0001);
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inline int Opcode(AlphaISA::MachInst inst) { return inst >> 26 & 0x3f; }
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inline int Ra(AlphaISA::MachInst inst) { return inst >> 21 & 0x1f; }
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const Addr PalBase = 0x4000;
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const Addr PalMax = 0x10000;
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/* namespace EV5 */ }
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#endif // __ARCH_ALPHA_EV5_HH__
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