10e6450120
Update stats for recent changes. Mostly minor changes in register access stats due to addition of new cc register type and slightly different (and more accurate) classification of int vs. fp register accesses.
1252 lines
149 KiB
Text
1252 lines
149 KiB
Text
|
|
---------- Begin Simulation Statistics ----------
|
|
sim_seconds 5.192278 # Number of seconds simulated
|
|
sim_ticks 5192277855000 # Number of ticks simulated
|
|
final_tick 5192277855000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
host_inst_rate 964497 # Simulator instruction rate (inst/s)
|
|
host_op_rate 1859169 # Simulator op (including micro ops) rate (op/s)
|
|
host_tick_rate 39021883302 # Simulator tick rate (ticks/s)
|
|
host_mem_usage 587612 # Number of bytes of host memory used
|
|
host_seconds 133.06 # Real time elapsed on the host
|
|
sim_insts 128336541 # Number of instructions simulated
|
|
sim_ops 247382226 # Number of ops (including micro ops) simulated
|
|
system.physmem.bytes_read::pc.south_bridge.ide 2866368 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu.inst 825920 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu.data 9005696 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::total 12698368 # Number of bytes read from this memory
|
|
system.physmem.bytes_inst_read::cpu.inst 825920 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_inst_read::total 825920 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_written::writebacks 8111936 # Number of bytes written to this memory
|
|
system.physmem.bytes_written::total 8111936 # Number of bytes written to this memory
|
|
system.physmem.num_reads::pc.south_bridge.ide 44787 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu.inst 12905 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu.data 140714 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::total 198412 # Number of read requests responded to by this memory
|
|
system.physmem.num_writes::writebacks 126749 # Number of write requests responded to by this memory
|
|
system.physmem.num_writes::total 126749 # Number of write requests responded to by this memory
|
|
system.physmem.bw_read::pc.south_bridge.ide 552044 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu.inst 159067 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu.data 1734440 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::total 2445626 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::cpu.inst 159067 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::total 159067 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::writebacks 1562308 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::total 1562308 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_total::writebacks 1562308 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::pc.south_bridge.ide 552044 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu.inst 159067 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu.data 1734440 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::total 4007933 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.readReqs 198412 # Total number of read requests accepted by DRAM controller
|
|
system.physmem.writeReqs 126749 # Total number of write requests accepted by DRAM controller
|
|
system.physmem.readBursts 198412 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts
|
|
system.physmem.writeBursts 126749 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts
|
|
system.physmem.bytesRead 12698368 # Total number of bytes read from memory
|
|
system.physmem.bytesWritten 8111936 # Total number of bytes written to memory
|
|
system.physmem.bytesConsumedRd 12698368 # bytesRead derated as per pkt->getSize()
|
|
system.physmem.bytesConsumedWr 8111936 # bytesWritten derated as per pkt->getSize()
|
|
system.physmem.servicedByWrQ 73 # Number of DRAM read bursts serviced by write Q
|
|
system.physmem.neitherReadNorWrite 1635 # Reqs where no action is needed
|
|
system.physmem.perBankRdReqs::0 12784 # Track reads on a per bank basis
|
|
system.physmem.perBankRdReqs::1 12459 # Track reads on a per bank basis
|
|
system.physmem.perBankRdReqs::2 12489 # Track reads on a per bank basis
|
|
system.physmem.perBankRdReqs::3 12363 # Track reads on a per bank basis
|
|
system.physmem.perBankRdReqs::4 12693 # Track reads on a per bank basis
|
|
system.physmem.perBankRdReqs::5 12438 # Track reads on a per bank basis
|
|
system.physmem.perBankRdReqs::6 12070 # Track reads on a per bank basis
|
|
system.physmem.perBankRdReqs::7 11839 # Track reads on a per bank basis
|
|
system.physmem.perBankRdReqs::8 11744 # Track reads on a per bank basis
|
|
system.physmem.perBankRdReqs::9 12077 # Track reads on a per bank basis
|
|
system.physmem.perBankRdReqs::10 12394 # Track reads on a per bank basis
|
|
system.physmem.perBankRdReqs::11 12547 # Track reads on a per bank basis
|
|
system.physmem.perBankRdReqs::12 12952 # Track reads on a per bank basis
|
|
system.physmem.perBankRdReqs::13 12861 # Track reads on a per bank basis
|
|
system.physmem.perBankRdReqs::14 12454 # Track reads on a per bank basis
|
|
system.physmem.perBankRdReqs::15 12175 # Track reads on a per bank basis
|
|
system.physmem.perBankWrReqs::0 8332 # Track writes on a per bank basis
|
|
system.physmem.perBankWrReqs::1 8067 # Track writes on a per bank basis
|
|
system.physmem.perBankWrReqs::2 8010 # Track writes on a per bank basis
|
|
system.physmem.perBankWrReqs::3 7928 # Track writes on a per bank basis
|
|
system.physmem.perBankWrReqs::4 8252 # Track writes on a per bank basis
|
|
system.physmem.perBankWrReqs::5 8013 # Track writes on a per bank basis
|
|
system.physmem.perBankWrReqs::6 7644 # Track writes on a per bank basis
|
|
system.physmem.perBankWrReqs::7 7381 # Track writes on a per bank basis
|
|
system.physmem.perBankWrReqs::8 7165 # Track writes on a per bank basis
|
|
system.physmem.perBankWrReqs::9 7640 # Track writes on a per bank basis
|
|
system.physmem.perBankWrReqs::10 7945 # Track writes on a per bank basis
|
|
system.physmem.perBankWrReqs::11 8073 # Track writes on a per bank basis
|
|
system.physmem.perBankWrReqs::12 8394 # Track writes on a per bank basis
|
|
system.physmem.perBankWrReqs::13 8318 # Track writes on a per bank basis
|
|
system.physmem.perBankWrReqs::14 7938 # Track writes on a per bank basis
|
|
system.physmem.perBankWrReqs::15 7649 # Track writes on a per bank basis
|
|
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
|
|
system.physmem.numWrRetry 2 # Number of times wr buffer was full causing retry
|
|
system.physmem.totGap 5192277790500 # Total gap between requests
|
|
system.physmem.readPktSize::0 0 # Categorize read packet sizes
|
|
system.physmem.readPktSize::1 0 # Categorize read packet sizes
|
|
system.physmem.readPktSize::2 0 # Categorize read packet sizes
|
|
system.physmem.readPktSize::3 0 # Categorize read packet sizes
|
|
system.physmem.readPktSize::4 0 # Categorize read packet sizes
|
|
system.physmem.readPktSize::5 0 # Categorize read packet sizes
|
|
system.physmem.readPktSize::6 198412 # Categorize read packet sizes
|
|
system.physmem.writePktSize::0 0 # Categorize write packet sizes
|
|
system.physmem.writePktSize::1 0 # Categorize write packet sizes
|
|
system.physmem.writePktSize::2 0 # Categorize write packet sizes
|
|
system.physmem.writePktSize::3 0 # Categorize write packet sizes
|
|
system.physmem.writePktSize::4 0 # Categorize write packet sizes
|
|
system.physmem.writePktSize::5 0 # Categorize write packet sizes
|
|
system.physmem.writePktSize::6 126749 # Categorize write packet sizes
|
|
system.physmem.rdQLenPdf::0 155262 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::1 13260 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::2 7507 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::3 2990 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::4 2888 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::5 2505 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::6 1478 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::7 1332 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::8 1262 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::9 1180 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::10 1090 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::11 1081 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::12 1017 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::13 1087 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::14 1166 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::15 1120 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::16 895 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::17 630 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::18 354 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::19 213 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::20 22 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::0 4326 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::1 4668 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::2 5455 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::3 5499 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::4 5505 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::5 5508 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::6 5509 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::7 5509 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::8 5509 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::9 5511 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::10 5511 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::11 5511 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::12 5511 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::13 5511 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::14 5511 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::15 5511 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::16 5511 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::17 5511 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::18 5511 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::19 5510 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::20 5510 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::21 5510 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::22 5510 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::23 1185 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::24 843 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::25 56 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::26 12 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::27 6 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::28 3 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::29 2 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::30 2 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::31 2 # What write queue length does an incoming req see
|
|
system.physmem.bytesPerActivate::samples 45297 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::mean 459.065810 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::gmean 168.635945 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::stdev 1572.397321 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::64-67 18574 41.00% 41.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::128-131 7178 15.85% 56.85% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::192-195 4205 9.28% 66.13% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::256-259 2900 6.40% 72.54% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::320-323 1973 4.36% 76.89% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::384-387 1677 3.70% 80.59% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::448-451 1250 2.76% 83.35% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::512-515 1043 2.30% 85.66% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::576-579 738 1.63% 87.29% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::640-643 608 1.34% 88.63% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::704-707 523 1.15% 89.78% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::768-771 460 1.02% 90.80% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::832-835 307 0.68% 91.48% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::896-899 311 0.69% 92.16% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::960-963 233 0.51% 92.68% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1024-1027 396 0.87% 93.55% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1088-1091 152 0.34% 93.89% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1152-1155 138 0.30% 94.19% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1216-1219 115 0.25% 94.45% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1280-1283 132 0.29% 94.74% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1344-1347 133 0.29% 95.03% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1408-1411 129 0.28% 95.32% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1472-1475 607 1.34% 96.66% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1536-1539 165 0.36% 97.02% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1600-1603 95 0.21% 97.23% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1664-1667 80 0.18% 97.41% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1728-1731 50 0.11% 97.52% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1792-1795 52 0.11% 97.63% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1856-1859 21 0.05% 97.68% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1920-1923 24 0.05% 97.73% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1984-1987 26 0.06% 97.79% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2048-2051 33 0.07% 97.86% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2112-2115 17 0.04% 97.90% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2176-2179 17 0.04% 97.94% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2240-2243 10 0.02% 97.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2304-2307 9 0.02% 97.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2368-2371 10 0.02% 98.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2432-2435 10 0.02% 98.02% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2496-2499 5 0.01% 98.03% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2560-2563 8 0.02% 98.05% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2624-2627 10 0.02% 98.07% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2688-2691 2 0.00% 98.08% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2752-2755 7 0.02% 98.09% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2816-2819 7 0.02% 98.11% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2880-2883 2 0.00% 98.11% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::2944-2947 4 0.01% 98.12% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3008-3011 2 0.00% 98.13% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3072-3075 3 0.01% 98.13% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3136-3139 4 0.01% 98.14% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3200-3203 4 0.01% 98.15% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3264-3267 6 0.01% 98.16% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3328-3331 1 0.00% 98.17% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3392-3395 3 0.01% 98.17% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3456-3459 11 0.02% 98.20% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3520-3523 1 0.00% 98.20% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3584-3587 3 0.01% 98.21% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3648-3651 3 0.01% 98.21% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3712-3715 3 0.01% 98.22% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3776-3779 12 0.03% 98.24% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3904-3907 2 0.00% 98.25% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::3968-3971 1 0.00% 98.25% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4032-4035 3 0.01% 98.26% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4096-4099 18 0.04% 98.30% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4160-4163 7 0.02% 98.31% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4224-4227 1 0.00% 98.32% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4288-4291 2 0.00% 98.32% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4352-4355 3 0.01% 98.33% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4416-4419 2 0.00% 98.33% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4480-4483 2 0.00% 98.34% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4544-4547 2 0.00% 98.34% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4608-4611 1 0.00% 98.34% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4672-4675 2 0.00% 98.35% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4800-4803 2 0.00% 98.35% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4864-4867 1 0.00% 98.35% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4928-4931 1 0.00% 98.36% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::4992-4995 2 0.00% 98.36% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5056-5059 2 0.00% 98.36% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5120-5123 2 0.00% 98.37% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5184-5187 1 0.00% 98.37% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5248-5251 1 0.00% 98.37% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5312-5315 2 0.00% 98.38% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5376-5379 2 0.00% 98.38% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5440-5443 1 0.00% 98.38% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5504-5507 2 0.00% 98.39% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5632-5635 2 0.00% 98.39% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5696-5699 1 0.00% 98.40% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5824-5827 1 0.00% 98.40% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::5952-5955 1 0.00% 98.40% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6016-6019 1 0.00% 98.40% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6080-6083 3 0.01% 98.41% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6144-6147 1 0.00% 98.41% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6272-6275 1 0.00% 98.41% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6400-6403 3 0.01% 98.42% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6528-6531 1 0.00% 98.42% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6592-6595 1 0.00% 98.42% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6720-6723 6 0.01% 98.44% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6848-6851 10 0.02% 98.46% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::6912-6915 4 0.01% 98.47% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7040-7043 3 0.01% 98.47% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7168-7171 3 0.01% 98.48% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7296-7299 1 0.00% 98.48% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7424-7427 1 0.00% 98.49% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7552-7555 3 0.01% 98.49% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7616-7619 1 0.00% 98.49% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7680-7683 1 0.00% 98.50% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7808-7811 1 0.00% 98.50% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::7936-7939 1 0.00% 98.50% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8064-8067 4 0.01% 98.51% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8192-8195 340 0.75% 99.26% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8320-8323 2 0.00% 99.26% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8384-8387 1 0.00% 99.27% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::8640-8643 1 0.00% 99.27% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9024-9027 1 0.00% 99.27% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9152-9155 1 0.00% 99.27% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9216-9219 5 0.01% 99.28% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9280-9283 1 0.00% 99.29% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9344-9347 1 0.00% 99.29% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9536-9539 1 0.00% 99.29% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9664-9667 1 0.00% 99.29% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9792-9795 1 0.00% 99.30% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::9856-9859 1 0.00% 99.30% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::10304-10307 1 0.00% 99.30% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::12544-12547 1 0.00% 99.30% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13248-13251 1 0.00% 99.30% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13568-13571 1 0.00% 99.31% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::13888-13891 1 0.00% 99.31% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14080-14083 1 0.00% 99.31% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14208-14211 1 0.00% 99.31% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14272-14275 2 0.00% 99.32% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14464-14467 1 0.00% 99.32% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14592-14595 1 0.00% 99.32% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14720-14723 1 0.00% 99.32% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14784-14787 1 0.00% 99.33% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::14912-14915 7 0.02% 99.34% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15040-15043 1 0.00% 99.34% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15104-15107 2 0.00% 99.35% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15232-15235 1 0.00% 99.35% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::15360-15363 4 0.01% 99.36% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16384-16387 244 0.54% 99.90% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16448-16451 12 0.03% 99.92% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16512-16515 10 0.02% 99.95% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16576-16579 4 0.01% 99.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16640-16643 4 0.01% 99.96% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16704-16707 4 0.01% 99.97% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16768-16771 1 0.00% 99.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16832-16835 1 0.00% 99.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::16896-16899 2 0.00% 99.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::17024-17027 1 0.00% 99.98% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::17152-17155 1 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::17280-17283 2 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::17344-17347 1 0.00% 99.99% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::17536-17539 2 0.00% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::17664-17667 1 0.00% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::total 45297 # Bytes accessed per row activation
|
|
system.physmem.totQLat 3410755000 # Total cycles spent in queuing delays
|
|
system.physmem.totMemAccLat 7054990000 # Sum of mem lat for all requests
|
|
system.physmem.totBusLat 991695000 # Total cycles spent in databus access
|
|
system.physmem.totBankLat 2652540000 # Total cycles spent in bank access
|
|
system.physmem.avgQLat 17196.59 # Average queueing delay per request
|
|
system.physmem.avgBankLat 13373.77 # Average bank access latency per request
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per request
|
|
system.physmem.avgMemAccLat 35570.36 # Average memory access latency
|
|
system.physmem.avgRdBW 2.45 # Average achieved read bandwidth in MB/s
|
|
system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MB/s
|
|
system.physmem.avgConsumedRdBW 2.45 # Average consumed read bandwidth in MB/s
|
|
system.physmem.avgConsumedWrBW 1.56 # Average consumed write bandwidth in MB/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
|
|
system.physmem.busUtil 0.03 # Data bus utilization in percentage
|
|
system.physmem.avgRdQLen 0.00 # Average read queue length over time
|
|
system.physmem.avgWrQLen 12.08 # Average write queue length over time
|
|
system.physmem.readRowHits 181292 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 98480 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 91.41 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 77.70 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 15968328.89 # Average gap between requests
|
|
system.membus.throughput 4372413 # Throughput (bytes/s)
|
|
system.membus.trans_dist::ReadReq 623536 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 623536 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 13773 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 13773 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 126749 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 2152 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 1652 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 159747 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 159747 # Transaction distribution
|
|
system.membus.trans_dist::MessageReq 1654 # Transaction distribution
|
|
system.membus.trans_dist::MessageResp 1654 # Transaction distribution
|
|
system.membus.pkt_count_system.apicbridge.master::system.cpu.interrupts.int_slave 3308 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.apicbridge.master::total 3308 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 480328 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 710110 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 391769 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 1582207 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 139016 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 139016 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 1724531 # Packet count per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.apicbridge.master::system.cpu.interrupts.int_slave 6616 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.apicbridge.master::total 6616 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 246444 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.cpu.interrupts.pio 1420217 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 14957248 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 16623909 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 5853056 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size_system.iocache.mem_side::total 5853056 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.tot_pkt_size::total 22483581 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.data_through_bus 22483581 # Total data (bytes)
|
|
system.membus.snoop_data_through_bus 219200 # Total snoop data (bytes)
|
|
system.membus.reqLayer0.occupancy 256796500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer1.occupancy 359311000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer2.occupancy 3308000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer3.occupancy 1350436000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer0.occupancy 1654000 # Layer occupancy (ticks)
|
|
system.membus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 2614907754 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 0.1 # Layer utilization (%)
|
|
system.membus.respLayer4.occupancy 428881000 # Layer occupancy (ticks)
|
|
system.membus.respLayer4.utilization 0.0 # Layer utilization (%)
|
|
system.iocache.tags.replacements 47507 # number of replacements
|
|
system.iocache.tags.tagsinuse 0.110729 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 47523 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 5049641350000 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.occ_blocks::pc.south_bridge.ide 0.110729 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_percent::pc.south_bridge.ide 0.006921 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::total 0.006921 # Average percentage of cache occupancy
|
|
system.iocache.ReadReq_misses::pc.south_bridge.ide 842 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 842 # number of ReadReq misses
|
|
system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
|
|
system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
|
|
system.iocache.demand_misses::pc.south_bridge.ide 47562 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 47562 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::pc.south_bridge.ide 47562 # number of overall misses
|
|
system.iocache.overall_misses::total 47562 # number of overall misses
|
|
system.iocache.ReadReq_miss_latency::pc.south_bridge.ide 148613936 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::total 148613936 # number of ReadReq miss cycles
|
|
system.iocache.WriteReq_miss_latency::pc.south_bridge.ide 10808111078 # number of WriteReq miss cycles
|
|
system.iocache.WriteReq_miss_latency::total 10808111078 # number of WriteReq miss cycles
|
|
system.iocache.demand_miss_latency::pc.south_bridge.ide 10956725014 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::total 10956725014 # number of demand (read+write) miss cycles
|
|
system.iocache.overall_miss_latency::pc.south_bridge.ide 10956725014 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::total 10956725014 # number of overall miss cycles
|
|
system.iocache.ReadReq_accesses::pc.south_bridge.ide 842 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 842 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
|
|
system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
|
|
system.iocache.demand_accesses::pc.south_bridge.ide 47562 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 47562 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::pc.south_bridge.ide 47562 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 47562 # number of overall (read+write) accesses
|
|
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_miss_rate::total 1 # miss rate for WriteReq accesses
|
|
system.iocache.demand_miss_rate::pc.south_bridge.ide 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::pc.south_bridge.ide 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_miss_latency::pc.south_bridge.ide 176501.111639 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::total 176501.111639 # average ReadReq miss latency
|
|
system.iocache.WriteReq_avg_miss_latency::pc.south_bridge.ide 231337.993964 # average WriteReq miss latency
|
|
system.iocache.WriteReq_avg_miss_latency::total 231337.993964 # average WriteReq miss latency
|
|
system.iocache.demand_avg_miss_latency::pc.south_bridge.ide 230367.205206 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total 230367.205206 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::pc.south_bridge.ide 230367.205206 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total 230367.205206 # average overall miss latency
|
|
system.iocache.blocked_cycles::no_mshrs 172843 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 15866 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs 10.893924 # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 0 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.writebacks::writebacks 46667 # number of writebacks
|
|
system.iocache.writebacks::total 46667 # number of writebacks
|
|
system.iocache.ReadReq_mshr_misses::pc.south_bridge.ide 842 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::total 842 # number of ReadReq MSHR misses
|
|
system.iocache.WriteReq_mshr_misses::pc.south_bridge.ide 46720 # number of WriteReq MSHR misses
|
|
system.iocache.WriteReq_mshr_misses::total 46720 # number of WriteReq MSHR misses
|
|
system.iocache.demand_mshr_misses::pc.south_bridge.ide 47562 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::total 47562 # number of demand (read+write) MSHR misses
|
|
system.iocache.overall_mshr_misses::pc.south_bridge.ide 47562 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::total 47562 # number of overall MSHR misses
|
|
system.iocache.ReadReq_mshr_miss_latency::pc.south_bridge.ide 104797436 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::total 104797436 # number of ReadReq MSHR miss cycles
|
|
system.iocache.WriteReq_mshr_miss_latency::pc.south_bridge.ide 8377057578 # number of WriteReq MSHR miss cycles
|
|
system.iocache.WriteReq_mshr_miss_latency::total 8377057578 # number of WriteReq MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::pc.south_bridge.ide 8481855014 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::total 8481855014 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::pc.south_bridge.ide 8481855014 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::total 8481855014 # number of overall MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
|
|
system.iocache.WriteReq_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for WriteReq accesses
|
|
system.iocache.WriteReq_mshr_miss_rate::total 1 # mshr miss rate for WriteReq accesses
|
|
system.iocache.demand_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
|
|
system.iocache.overall_mshr_miss_rate::pc.south_bridge.ide 1 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 124462.513064 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::total 124462.513064 # average ReadReq mshr miss latency
|
|
system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 179303.458433 # average WriteReq mshr miss latency
|
|
system.iocache.WriteReq_avg_mshr_miss_latency::total 179303.458433 # average WriteReq mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 178332.597746 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::total 178332.597746 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 178332.597746 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::total 178332.597746 # average overall mshr miss latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
|
|
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
|
|
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
|
|
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
|
|
system.pc.south_bridge.ide.disks1.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.pc.south_bridge.ide.disks1.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.pc.south_bridge.ide.disks1.dma_read_txs 0 # Number of DMA read transactions (not PRD).
|
|
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
|
|
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
|
|
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
|
|
system.iobus.throughput 631773 # Throughput (bytes/s)
|
|
system.iobus.trans_dist::ReadReq 230147 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 230147 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 57579 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 57579 # Transaction distribution
|
|
system.iobus.trans_dist::MessageReq 1654 # Transaction distribution
|
|
system.iobus.trans_dist::MessageResp 1654 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.cmos.pio 44 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.dma1.pio 6 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide.pio 11088 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.ide-pciconf 180 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.keyboard.pio 1364 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic1.pio 86 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pic2.pio 54 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.pit.pio 30 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.speaker.pio 436684 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.south_bridge.io_apic.pio 1210 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.i_dont_exist.pio 170 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.behind_pci.pio 2 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.com_1.pio 27236 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_2.pio 12 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_3.pio 12 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.fake_com_4.pio 12 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.fake_floppy.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.pc.pciconfig.pio 2128 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 480328 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 95124 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.pc.south_bridge.ide.dma::total 95124 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 3308 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.pc.south_bridge.io_apic.int_master::total 3308 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 578760 # Packet count per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.cmos.pio 22 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.dma1.pio 3 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide.pio 6686 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.ide-pciconf 221 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.keyboard.pio 682 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic1.pio 43 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pic2.pio 27 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.pit.pio 15 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.speaker.pio 218342 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.pc.south_bridge.io_apic.pio 2420 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.pc.i_dont_exist.pio 85 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.pc.behind_pci.pio 1 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.pc.com_1.pio 13618 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_2.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_3.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_com_4.pio 6 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.pc.fake_floppy.pio 5 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::system.pc.pciconfig.pio 4256 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.bridge.master::total 246444 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::system.iocache.cpu_side 3027280 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.pc.south_bridge.ide.dma::total 3027280 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::system.apicbridge.slave 6616 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size_system.pc.south_bridge.io_apic.int_master::total 6616 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.tot_pkt_size::total 3280340 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.data_through_bus 3280340 # Total data (bytes)
|
|
system.iobus.reqLayer0.occupancy 3946566 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 34000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 6000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer3.occupancy 8813000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer4.occupancy 122000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer5.occupancy 891000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer6.occupancy 77000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer7.occupancy 50000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer8.occupancy 26000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer8.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer9.occupancy 218343000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer10.occupancy 1014000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer11.occupancy 170000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer12.occupancy 2000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer13.occupancy 20374000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer14.occupancy 9000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer15.occupancy 9000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer16.occupancy 9000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer17.occupancy 10000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer18.occupancy 424359014 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer19.occupancy 1064000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 469469000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer1.occupancy 53490000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer2.occupancy 1654000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.numCycles 10384555710 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.committedInsts 128336541 # Number of instructions committed
|
|
system.cpu.committedOps 247382226 # Number of ops (including micro ops) committed
|
|
system.cpu.num_int_alu_accesses 231975048 # Number of integer alu accesses
|
|
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
|
|
system.cpu.num_func_calls 2299863 # number of times a function call or return occured
|
|
system.cpu.num_conditional_control_insts 23167946 # number of instructions that are conditional controls
|
|
system.cpu.num_int_insts 231975048 # number of integer instructions
|
|
system.cpu.num_fp_insts 0 # number of float instructions
|
|
system.cpu.num_int_register_reads 434515715 # number of times the integer registers were read
|
|
system.cpu.num_int_register_writes 197846848 # number of times the integer registers were written
|
|
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
|
|
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
|
|
system.cpu.num_cc_register_reads 132806307 # number of times the CC registers were read
|
|
system.cpu.num_cc_register_writes 95529498 # number of times the CC registers were written
|
|
system.cpu.num_mem_refs 22249600 # number of memory refs
|
|
system.cpu.num_load_insts 13881232 # Number of load instructions
|
|
system.cpu.num_store_insts 8368368 # Number of store instructions
|
|
system.cpu.num_idle_cycles 9777359201.998117 # Number of idle cycles
|
|
system.cpu.num_busy_cycles 607196508.001883 # Number of busy cycles
|
|
system.cpu.not_idle_fraction 0.058471 # Percentage of non-idle cycles
|
|
system.cpu.idle_fraction 0.941529 # Percentage of idle cycles
|
|
system.cpu.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
|
|
system.cpu.icache.tags.replacements 792807 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 510.358419 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 144581557 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 793319 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 182.248953 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 161241203250 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 510.358419 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.996794 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.996794 # Average percentage of cache occupancy
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 144581557 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 144581557 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 144581557 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 144581557 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 144581557 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 144581557 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 793326 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 793326 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 793326 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 793326 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 793326 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 793326 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 11210417756 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 11210417756 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 11210417756 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 11210417756 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 11210417756 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 11210417756 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 145374883 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 145374883 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 145374883 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 145374883 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 145374883 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 145374883 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.005457 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.005457 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.005457 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.005457 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.005457 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.005457 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 14130.909306 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 14130.909306 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 14130.909306 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 14130.909306 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 14130.909306 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 14130.909306 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 793326 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 793326 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 793326 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 793326 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 793326 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 793326 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 9617488244 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 9617488244 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 9617488244 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 9617488244 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 9617488244 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 9617488244 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.005457 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.005457 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.005457 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.005457 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.005457 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.005457 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 12122.996402 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 12122.996402 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 12122.996402 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 12122.996402 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 12122.996402 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 12122.996402 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.itb_walker_cache.tags.replacements 3898 # number of replacements
|
|
system.cpu.itb_walker_cache.tags.tagsinuse 3.066238 # Cycle average of tags in use
|
|
system.cpu.itb_walker_cache.tags.total_refs 7439 # Total number of references to valid blocks.
|
|
system.cpu.itb_walker_cache.tags.sampled_refs 3908 # Sample count of references to valid blocks.
|
|
system.cpu.itb_walker_cache.tags.avg_refs 1.903531 # Average number of references to valid blocks.
|
|
system.cpu.itb_walker_cache.tags.warmup_cycle 5166941674000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.itb_walker_cache.tags.occ_blocks::cpu.itb.walker 3.066238 # Average occupied blocks per requestor
|
|
system.cpu.itb_walker_cache.tags.occ_percent::cpu.itb.walker 0.191640 # Average percentage of cache occupancy
|
|
system.cpu.itb_walker_cache.tags.occ_percent::total 0.191640 # Average percentage of cache occupancy
|
|
system.cpu.itb_walker_cache.ReadReq_hits::cpu.itb.walker 7461 # number of ReadReq hits
|
|
system.cpu.itb_walker_cache.ReadReq_hits::total 7461 # number of ReadReq hits
|
|
system.cpu.itb_walker_cache.WriteReq_hits::cpu.itb.walker 2 # number of WriteReq hits
|
|
system.cpu.itb_walker_cache.WriteReq_hits::total 2 # number of WriteReq hits
|
|
system.cpu.itb_walker_cache.demand_hits::cpu.itb.walker 7463 # number of demand (read+write) hits
|
|
system.cpu.itb_walker_cache.demand_hits::total 7463 # number of demand (read+write) hits
|
|
system.cpu.itb_walker_cache.overall_hits::cpu.itb.walker 7463 # number of overall hits
|
|
system.cpu.itb_walker_cache.overall_hits::total 7463 # number of overall hits
|
|
system.cpu.itb_walker_cache.ReadReq_misses::cpu.itb.walker 4754 # number of ReadReq misses
|
|
system.cpu.itb_walker_cache.ReadReq_misses::total 4754 # number of ReadReq misses
|
|
system.cpu.itb_walker_cache.demand_misses::cpu.itb.walker 4754 # number of demand (read+write) misses
|
|
system.cpu.itb_walker_cache.demand_misses::total 4754 # number of demand (read+write) misses
|
|
system.cpu.itb_walker_cache.overall_misses::cpu.itb.walker 4754 # number of overall misses
|
|
system.cpu.itb_walker_cache.overall_misses::total 4754 # number of overall misses
|
|
system.cpu.itb_walker_cache.ReadReq_miss_latency::cpu.itb.walker 48555250 # number of ReadReq miss cycles
|
|
system.cpu.itb_walker_cache.ReadReq_miss_latency::total 48555250 # number of ReadReq miss cycles
|
|
system.cpu.itb_walker_cache.demand_miss_latency::cpu.itb.walker 48555250 # number of demand (read+write) miss cycles
|
|
system.cpu.itb_walker_cache.demand_miss_latency::total 48555250 # number of demand (read+write) miss cycles
|
|
system.cpu.itb_walker_cache.overall_miss_latency::cpu.itb.walker 48555250 # number of overall miss cycles
|
|
system.cpu.itb_walker_cache.overall_miss_latency::total 48555250 # number of overall miss cycles
|
|
system.cpu.itb_walker_cache.ReadReq_accesses::cpu.itb.walker 12215 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.itb_walker_cache.ReadReq_accesses::total 12215 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.itb_walker_cache.WriteReq_accesses::cpu.itb.walker 2 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.itb_walker_cache.WriteReq_accesses::total 2 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.itb_walker_cache.demand_accesses::cpu.itb.walker 12217 # number of demand (read+write) accesses
|
|
system.cpu.itb_walker_cache.demand_accesses::total 12217 # number of demand (read+write) accesses
|
|
system.cpu.itb_walker_cache.overall_accesses::cpu.itb.walker 12217 # number of overall (read+write) accesses
|
|
system.cpu.itb_walker_cache.overall_accesses::total 12217 # number of overall (read+write) accesses
|
|
system.cpu.itb_walker_cache.ReadReq_miss_rate::cpu.itb.walker 0.389194 # miss rate for ReadReq accesses
|
|
system.cpu.itb_walker_cache.ReadReq_miss_rate::total 0.389194 # miss rate for ReadReq accesses
|
|
system.cpu.itb_walker_cache.demand_miss_rate::cpu.itb.walker 0.389130 # miss rate for demand accesses
|
|
system.cpu.itb_walker_cache.demand_miss_rate::total 0.389130 # miss rate for demand accesses
|
|
system.cpu.itb_walker_cache.overall_miss_rate::cpu.itb.walker 0.389130 # miss rate for overall accesses
|
|
system.cpu.itb_walker_cache.overall_miss_rate::total 0.389130 # miss rate for overall accesses
|
|
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::cpu.itb.walker 10213.557005 # average ReadReq miss latency
|
|
system.cpu.itb_walker_cache.ReadReq_avg_miss_latency::total 10213.557005 # average ReadReq miss latency
|
|
system.cpu.itb_walker_cache.demand_avg_miss_latency::cpu.itb.walker 10213.557005 # average overall miss latency
|
|
system.cpu.itb_walker_cache.demand_avg_miss_latency::total 10213.557005 # average overall miss latency
|
|
system.cpu.itb_walker_cache.overall_avg_miss_latency::cpu.itb.walker 10213.557005 # average overall miss latency
|
|
system.cpu.itb_walker_cache.overall_avg_miss_latency::total 10213.557005 # average overall miss latency
|
|
system.cpu.itb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.itb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.itb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.itb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.itb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.itb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.itb_walker_cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.itb_walker_cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.itb_walker_cache.writebacks::writebacks 837 # number of writebacks
|
|
system.cpu.itb_walker_cache.writebacks::total 837 # number of writebacks
|
|
system.cpu.itb_walker_cache.ReadReq_mshr_misses::cpu.itb.walker 4754 # number of ReadReq MSHR misses
|
|
system.cpu.itb_walker_cache.ReadReq_mshr_misses::total 4754 # number of ReadReq MSHR misses
|
|
system.cpu.itb_walker_cache.demand_mshr_misses::cpu.itb.walker 4754 # number of demand (read+write) MSHR misses
|
|
system.cpu.itb_walker_cache.demand_mshr_misses::total 4754 # number of demand (read+write) MSHR misses
|
|
system.cpu.itb_walker_cache.overall_mshr_misses::cpu.itb.walker 4754 # number of overall MSHR misses
|
|
system.cpu.itb_walker_cache.overall_mshr_misses::total 4754 # number of overall MSHR misses
|
|
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::cpu.itb.walker 39044750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.itb_walker_cache.ReadReq_mshr_miss_latency::total 39044750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.itb_walker_cache.demand_mshr_miss_latency::cpu.itb.walker 39044750 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.itb_walker_cache.demand_mshr_miss_latency::total 39044750 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.itb_walker_cache.overall_mshr_miss_latency::cpu.itb.walker 39044750 # number of overall MSHR miss cycles
|
|
system.cpu.itb_walker_cache.overall_mshr_miss_latency::total 39044750 # number of overall MSHR miss cycles
|
|
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.389194 # mshr miss rate for ReadReq accesses
|
|
system.cpu.itb_walker_cache.ReadReq_mshr_miss_rate::total 0.389194 # mshr miss rate for ReadReq accesses
|
|
system.cpu.itb_walker_cache.demand_mshr_miss_rate::cpu.itb.walker 0.389130 # mshr miss rate for demand accesses
|
|
system.cpu.itb_walker_cache.demand_mshr_miss_rate::total 0.389130 # mshr miss rate for demand accesses
|
|
system.cpu.itb_walker_cache.overall_mshr_miss_rate::cpu.itb.walker 0.389130 # mshr miss rate for overall accesses
|
|
system.cpu.itb_walker_cache.overall_mshr_miss_rate::total 0.389130 # mshr miss rate for overall accesses
|
|
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 8213.031132 # average ReadReq mshr miss latency
|
|
system.cpu.itb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8213.031132 # average ReadReq mshr miss latency
|
|
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::cpu.itb.walker 8213.031132 # average overall mshr miss latency
|
|
system.cpu.itb_walker_cache.demand_avg_mshr_miss_latency::total 8213.031132 # average overall mshr miss latency
|
|
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::cpu.itb.walker 8213.031132 # average overall mshr miss latency
|
|
system.cpu.itb_walker_cache.overall_avg_mshr_miss_latency::total 8213.031132 # average overall mshr miss latency
|
|
system.cpu.itb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dtb_walker_cache.tags.replacements 7667 # number of replacements
|
|
system.cpu.dtb_walker_cache.tags.tagsinuse 5.048611 # Cycle average of tags in use
|
|
system.cpu.dtb_walker_cache.tags.total_refs 13083 # Total number of references to valid blocks.
|
|
system.cpu.dtb_walker_cache.tags.sampled_refs 7683 # Sample count of references to valid blocks.
|
|
system.cpu.dtb_walker_cache.tags.avg_refs 1.702850 # Average number of references to valid blocks.
|
|
system.cpu.dtb_walker_cache.tags.warmup_cycle 5163398099000 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dtb_walker_cache.tags.occ_blocks::cpu.dtb.walker 5.048611 # Average occupied blocks per requestor
|
|
system.cpu.dtb_walker_cache.tags.occ_percent::cpu.dtb.walker 0.315538 # Average percentage of cache occupancy
|
|
system.cpu.dtb_walker_cache.tags.occ_percent::total 0.315538 # Average percentage of cache occupancy
|
|
system.cpu.dtb_walker_cache.ReadReq_hits::cpu.dtb.walker 13083 # number of ReadReq hits
|
|
system.cpu.dtb_walker_cache.ReadReq_hits::total 13083 # number of ReadReq hits
|
|
system.cpu.dtb_walker_cache.demand_hits::cpu.dtb.walker 13083 # number of demand (read+write) hits
|
|
system.cpu.dtb_walker_cache.demand_hits::total 13083 # number of demand (read+write) hits
|
|
system.cpu.dtb_walker_cache.overall_hits::cpu.dtb.walker 13083 # number of overall hits
|
|
system.cpu.dtb_walker_cache.overall_hits::total 13083 # number of overall hits
|
|
system.cpu.dtb_walker_cache.ReadReq_misses::cpu.dtb.walker 8874 # number of ReadReq misses
|
|
system.cpu.dtb_walker_cache.ReadReq_misses::total 8874 # number of ReadReq misses
|
|
system.cpu.dtb_walker_cache.demand_misses::cpu.dtb.walker 8874 # number of demand (read+write) misses
|
|
system.cpu.dtb_walker_cache.demand_misses::total 8874 # number of demand (read+write) misses
|
|
system.cpu.dtb_walker_cache.overall_misses::cpu.dtb.walker 8874 # number of overall misses
|
|
system.cpu.dtb_walker_cache.overall_misses::total 8874 # number of overall misses
|
|
system.cpu.dtb_walker_cache.ReadReq_miss_latency::cpu.dtb.walker 95939000 # number of ReadReq miss cycles
|
|
system.cpu.dtb_walker_cache.ReadReq_miss_latency::total 95939000 # number of ReadReq miss cycles
|
|
system.cpu.dtb_walker_cache.demand_miss_latency::cpu.dtb.walker 95939000 # number of demand (read+write) miss cycles
|
|
system.cpu.dtb_walker_cache.demand_miss_latency::total 95939000 # number of demand (read+write) miss cycles
|
|
system.cpu.dtb_walker_cache.overall_miss_latency::cpu.dtb.walker 95939000 # number of overall miss cycles
|
|
system.cpu.dtb_walker_cache.overall_miss_latency::total 95939000 # number of overall miss cycles
|
|
system.cpu.dtb_walker_cache.ReadReq_accesses::cpu.dtb.walker 21957 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dtb_walker_cache.ReadReq_accesses::total 21957 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dtb_walker_cache.demand_accesses::cpu.dtb.walker 21957 # number of demand (read+write) accesses
|
|
system.cpu.dtb_walker_cache.demand_accesses::total 21957 # number of demand (read+write) accesses
|
|
system.cpu.dtb_walker_cache.overall_accesses::cpu.dtb.walker 21957 # number of overall (read+write) accesses
|
|
system.cpu.dtb_walker_cache.overall_accesses::total 21957 # number of overall (read+write) accesses
|
|
system.cpu.dtb_walker_cache.ReadReq_miss_rate::cpu.dtb.walker 0.404154 # miss rate for ReadReq accesses
|
|
system.cpu.dtb_walker_cache.ReadReq_miss_rate::total 0.404154 # miss rate for ReadReq accesses
|
|
system.cpu.dtb_walker_cache.demand_miss_rate::cpu.dtb.walker 0.404154 # miss rate for demand accesses
|
|
system.cpu.dtb_walker_cache.demand_miss_rate::total 0.404154 # miss rate for demand accesses
|
|
system.cpu.dtb_walker_cache.overall_miss_rate::cpu.dtb.walker 0.404154 # miss rate for overall accesses
|
|
system.cpu.dtb_walker_cache.overall_miss_rate::total 0.404154 # miss rate for overall accesses
|
|
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::cpu.dtb.walker 10811.246338 # average ReadReq miss latency
|
|
system.cpu.dtb_walker_cache.ReadReq_avg_miss_latency::total 10811.246338 # average ReadReq miss latency
|
|
system.cpu.dtb_walker_cache.demand_avg_miss_latency::cpu.dtb.walker 10811.246338 # average overall miss latency
|
|
system.cpu.dtb_walker_cache.demand_avg_miss_latency::total 10811.246338 # average overall miss latency
|
|
system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 10811.246338 # average overall miss latency
|
|
system.cpu.dtb_walker_cache.overall_avg_miss_latency::total 10811.246338 # average overall miss latency
|
|
system.cpu.dtb_walker_cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dtb_walker_cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dtb_walker_cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dtb_walker_cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dtb_walker_cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dtb_walker_cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dtb_walker_cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dtb_walker_cache.writebacks::writebacks 2999 # number of writebacks
|
|
system.cpu.dtb_walker_cache.writebacks::total 2999 # number of writebacks
|
|
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::cpu.dtb.walker 8874 # number of ReadReq MSHR misses
|
|
system.cpu.dtb_walker_cache.ReadReq_mshr_misses::total 8874 # number of ReadReq MSHR misses
|
|
system.cpu.dtb_walker_cache.demand_mshr_misses::cpu.dtb.walker 8874 # number of demand (read+write) MSHR misses
|
|
system.cpu.dtb_walker_cache.demand_mshr_misses::total 8874 # number of demand (read+write) MSHR misses
|
|
system.cpu.dtb_walker_cache.overall_mshr_misses::cpu.dtb.walker 8874 # number of overall MSHR misses
|
|
system.cpu.dtb_walker_cache.overall_mshr_misses::total 8874 # number of overall MSHR misses
|
|
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 78190500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_latency::total 78190500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::cpu.dtb.walker 78190500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dtb_walker_cache.demand_mshr_miss_latency::total 78190500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::cpu.dtb.walker 78190500 # number of overall MSHR miss cycles
|
|
system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 78190500 # number of overall MSHR miss cycles
|
|
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.404154 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dtb_walker_cache.ReadReq_mshr_miss_rate::total 0.404154 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::cpu.dtb.walker 0.404154 # mshr miss rate for demand accesses
|
|
system.cpu.dtb_walker_cache.demand_mshr_miss_rate::total 0.404154 # mshr miss rate for demand accesses
|
|
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::cpu.dtb.walker 0.404154 # mshr miss rate for overall accesses
|
|
system.cpu.dtb_walker_cache.overall_mshr_miss_rate::total 0.404154 # mshr miss rate for overall accesses
|
|
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 8811.189993 # average ReadReq mshr miss latency
|
|
system.cpu.dtb_walker_cache.ReadReq_avg_mshr_miss_latency::total 8811.189993 # average ReadReq mshr miss latency
|
|
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 8811.189993 # average overall mshr miss latency
|
|
system.cpu.dtb_walker_cache.demand_avg_mshr_miss_latency::total 8811.189993 # average overall mshr miss latency
|
|
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 8811.189993 # average overall mshr miss latency
|
|
system.cpu.dtb_walker_cache.overall_avg_mshr_miss_latency::total 8811.189993 # average overall mshr miss latency
|
|
system.cpu.dtb_walker_cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.dcache.tags.replacements 1622533 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 511.997176 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 20039030 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 1623045 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 12.346565 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 49459250 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 511.997176 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.999994 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 11994437 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 11994437 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 8042382 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 8042382 # number of WriteReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 20036819 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 20036819 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 20036819 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 20036819 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 1309601 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 1309601 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 315672 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 315672 # number of WriteReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 1625273 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 1625273 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 1625273 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 1625273 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 18886188795 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 18886188795 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 10748063695 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 10748063695 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 29634252490 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 29634252490 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 29634252490 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 29634252490 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 13304038 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 13304038 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 8358054 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 8358054 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 21662092 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 21662092 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 21662092 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 21662092 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098436 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.098436 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.037769 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.037769 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.075028 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.075028 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.075028 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.075028 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14421.330462 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 14421.330462 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 34048.200965 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 34048.200965 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 18233.399860 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 18233.399860 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 18233.399860 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 18233.399860 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 1539374 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 1539374 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 1309601 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 1309601 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 315672 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 315672 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 1625273 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 1625273 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 1625273 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 1625273 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 16253560205 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 16253560205 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10061381305 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 10061381305 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 26314941510 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 26314941510 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 26314941510 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 26314941510 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 94214672500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 94214672500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 2537247000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 2537247000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 96751919500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.overall_mshr_uncacheable_latency::total 96751919500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098436 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098436 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.037769 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.037769 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.075028 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.075028 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.075028 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.075028 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12411.078034 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12411.078034 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 31872.897517 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 31872.897517 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 16191.090057 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 16191.090057 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 16191.090057 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 16191.090057 # average overall mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
|
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.throughput 49299027 # Throughput (bytes/s)
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 2698843 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 2698315 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteReq 13773 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::WriteResp 13773 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 1543210 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeReq 2211 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::UpgradeResp 2211 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 360181 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 313477 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1586639 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 5979450 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 8835 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 18580 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 7593504 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 50772032 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204036453 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 261184 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb_walker_cache.mem_side::system.cpu.l2cache.cpu_side 621184 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.tot_pkt_size::total 255690853 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.data_through_bus 255669733 # Total data (bytes)
|
|
system.cpu.toL2Bus.snoop_data_through_bus 304512 # Total snoop data (bytes)
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 3835424500 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.snoopLayer0.occupancy 495000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 1193127756 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 3058413490 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer2.occupancy 7132250 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer3.occupancy 13311250 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.cpu.l2cache.tags.replacements 86950 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 64733.250589 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 3493106 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 151616 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 23.039165 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 50239.194329 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.dtb.walker 0.026648 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.itb.walker 0.141259 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 3379.223326 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 11114.665027 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.766589 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.dtb.walker 0.000000 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.itb.walker 0.000002 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.051563 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.169596 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.987751 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 6706 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3239 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 780407 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 1280531 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 2070883 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 1543210 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 1543210 # number of Writeback hits
|
|
system.cpu.l2cache.UpgradeReq_hits::cpu.data 301 # number of UpgradeReq hits
|
|
system.cpu.l2cache.UpgradeReq_hits::total 301 # number of UpgradeReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 200188 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 200188 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.dtb.walker 6706 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.itb.walker 3239 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 780407 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 1480719 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 2271071 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.dtb.walker 6706 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.itb.walker 3239 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 780407 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 1480719 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 2271071 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 1 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 5 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 12906 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 28336 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 41248 # number of ReadReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::cpu.data 1410 # number of UpgradeReq misses
|
|
system.cpu.l2cache.UpgradeReq_misses::total 1410 # number of UpgradeReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 113269 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 113269 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.dtb.walker 1 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.itb.walker 5 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 12906 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 141605 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 154517 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.dtb.walker 1 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.itb.walker 5 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 12906 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 141605 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 154517 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 89250 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 390250 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 1020078744 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2137913705 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 3158471949 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 16387856 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.UpgradeReq_miss_latency::total 16387856 # number of UpgradeReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 7707092698 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 7707092698 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 89250 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 390250 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 1020078744 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 9845006403 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 10865564647 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 89250 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 390250 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 1020078744 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 9845006403 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 10865564647 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 6707 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3244 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 793313 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 1308867 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 2112131 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 1543210 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 1543210 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 1711 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.UpgradeReq_accesses::total 1711 # number of UpgradeReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 313457 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 313457 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 6707 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.itb.walker 3244 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 793313 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 1622324 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 2425588 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 6707 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.itb.walker 3244 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 793313 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 1622324 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 2425588 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000149 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.001541 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.016268 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.021649 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.019529 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.824079 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.824079 # miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.361354 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.361354 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000149 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.001541 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.016268 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.087285 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.063703 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000149 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.001541 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.016268 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.087285 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.063703 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 89250 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 78050 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79039.109252 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75448.676772 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 76572.729563 # average ReadReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 11622.592908 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 11622.592908 # average UpgradeReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 68042.383159 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 68042.383159 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 89250 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 78050 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79039.109252 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 69524.426419 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 70319.541843 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 89250 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 78050 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79039.109252 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 69524.426419 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 70319.541843 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 80082 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 80082 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 1 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 5 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 12906 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 28336 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 41248 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1410 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.UpgradeReq_mshr_misses::total 1410 # number of UpgradeReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 113269 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 113269 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 1 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 5 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 12906 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 141605 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 154517 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 1 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 5 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 12906 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 141605 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 154517 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 76250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 326250 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 857244756 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1780461295 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2638108551 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 14985893 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 14985893 # number of UpgradeReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6290141302 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6290141302 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 76250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 326250 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 857244756 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8070602597 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 8928249853 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 76250 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 326250 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 857244756 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8070602597 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 8928249853 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 86655869000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 86655869000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 2370634500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 2370634500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 89026503500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 89026503500 # number of overall MSHR uncacheable cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000149 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001541 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016268 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.021649 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019529 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.824079 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.824079 # mshr miss rate for UpgradeReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.361354 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.361354 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000149 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.001541 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016268 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.087285 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.063703 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000149 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.001541 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016268 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087285 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.063703 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 65250 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66422.187820 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 62833.896633 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 63957.247648 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10628.292908 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10628.292908 # average UpgradeReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 55532.769796 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 55532.769796 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66422.187820 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 56993.768560 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57781.667085 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 76250 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 65250 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66422.187820 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 56993.768560 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57781.667085 # average overall mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|