a8b03e4d01
arch/alpha/isa/decoder.isa:
Make IPR accessing instructions serializing so they are not issued incorrectly in the O3 model.
arch/alpha/isa/pal.isa:
Allow IPR instructions to have flags.
base/traceflags.py:
Include new trace flags from the two new CPU models.
cpu/SConscript:
Create the templates for the split mem accessor methods. Also include the new files from the new models (the Ozone model will be checked in next).
cpu/base_dyn_inst.cc:
cpu/base_dyn_inst.hh:
Update to the BaseDynInst for the new models.
--HG--
extra : convert_revision : cc82db9c72ec3e29cea4c3fdff74a3843e287a35
93 lines
3.2 KiB
C++
93 lines
3.2 KiB
C++
/*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_O3_RAS_HH__
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#define __CPU_O3_RAS_HH__
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// For Addr type.
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#include "arch/isa_traits.hh"
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#include <vector>
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/** Return address stack class, implements a simple RAS. */
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class ReturnAddrStack
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{
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public:
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/** Creates a return address stack, but init() must be called prior to
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* use.
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*/
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ReturnAddrStack() {}
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/** Initializes RAS with a specified number of entries.
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* @param numEntries Number of entries in the RAS.
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*/
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void init(unsigned numEntries);
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/** Returns the top address on the RAS. */
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Addr top()
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{ return addrStack[tos]; }
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/** Returns the index of the top of the RAS. */
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unsigned topIdx()
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{ return tos; }
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/** Pushes an address onto the RAS. */
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void push(const Addr &return_addr);
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/** Pops the top address from the RAS. */
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void pop();
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/** Changes index to the top of the RAS, and replaces the top address with
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* a new target.
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* @param top_entry_idx The index of the RAS that will now be the top.
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* @param restored_target The new target address of the new top of the RAS.
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*/
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void restore(unsigned top_entry_idx, const Addr &restored_target);
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private:
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/** Increments the top of stack index. */
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inline void incrTos()
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{ if (++tos == numEntries) tos = 0; }
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/** Decrements the top of stack index. */
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inline void decrTos()
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{ tos = (tos == 0 ? numEntries - 1 : tos - 1); }
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/** The RAS itself. */
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std::vector<Addr> addrStack;
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/** The number of entries in the RAS. */
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unsigned numEntries;
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/** The number of used entries in the RAS. */
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unsigned usedEntries;
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/** The top of stack index. */
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unsigned tos;
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};
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#endif // __CPU_O3_RAS_HH__
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