gem5/tests/quick/00.hello/ref/mips/linux/simple-timing/simout
Steve Reinhardt 9e45ada171 stats: update stats for preceding coherence changes
Because the handling of the E state for multilevel caches
has changed, stats are affected for any non-ruby config
with caches, even uniprocessor simple CPU.
2010-09-09 14:40:19 -04:00

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Redirecting stdout to build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing/simout
Redirecting stderr to build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing/simerr
M5 Simulator System
Copyright (c) 2001-2008
The Regents of The University of Michigan
All Rights Reserved
M5 compiled Aug 26 2010 12:56:28
M5 revision 85cafc6ccb42 7662 default qtip tip sc-fail-fix
M5 started Aug 26 2010 12:56:30
M5 executing on zizzer
command line: build/MIPS_SE/m5.opt -d build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing -re tests/run.py build/MIPS_SE/tests/opt/quick/00.hello/mips/linux/simple-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello World!
Exiting @ tick 32088000 because target called exit()