620 lines
17 KiB
C++
620 lines
17 KiB
C++
/*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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*/
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#ifndef __CPU_OZONE_CPU_HH__
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#define __CPU_OZONE_CPU_HH__
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#include <set>
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#include "arch/regfile.hh"
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#include "base/statistics.hh"
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#include "base/timebuf.hh"
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#include "config/full_system.hh"
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#include "cpu/base.hh"
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#include "cpu/thread_context.hh"
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#include "cpu/inst_seq.hh"
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#include "cpu/ozone/rename_table.hh"
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#include "cpu/ozone/thread_state.hh"
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#include "cpu/pc_event.hh"
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#include "cpu/static_inst.hh"
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#include "mem/page_table.hh"
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#include "sim/eventq.hh"
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// forward declarations
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#if FULL_SYSTEM
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#include "arch/alpha/tlb.hh"
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namespace TheISA
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{
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class ITB;
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class DTB;
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}
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class PhysicalMemory;
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class MemoryController;
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class RemoteGDB;
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class GDBListener;
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namespace Kernel {
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class Statistics;
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};
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#else
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class Process;
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#endif // FULL_SYSTEM
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class Checkpoint;
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class EndQuiesceEvent;
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class MemObject;
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class Request;
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namespace Trace {
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class InstRecord;
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}
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template <class>
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class Checker;
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/**
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* Light weight out of order CPU model that approximates an out of
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* order CPU. It is separated into a front end and a back end, with
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* the template parameter Impl describing the classes used for each.
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* The goal is to be able to specify through the Impl the class to use
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* for the front end and back end, with different classes used to
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* model different levels of detail.
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*/
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template <class Impl>
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class OzoneCPU : public BaseCPU
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{
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private:
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typedef typename Impl::FrontEnd FrontEnd;
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typedef typename Impl::BackEnd BackEnd;
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typedef typename Impl::DynInst DynInst;
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typedef typename Impl::DynInstPtr DynInstPtr;
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typedef TheISA::FloatReg FloatReg;
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typedef TheISA::FloatRegBits FloatRegBits;
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typedef TheISA::MiscReg MiscReg;
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public:
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class OzoneTC : public ThreadContext {
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public:
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OzoneCPU<Impl> *cpu;
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OzoneThreadState<Impl> *thread;
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BaseCPU *getCpuPtr();
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void setCpuId(int id);
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int readCpuId() { return thread->readCpuId(); }
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#if FULL_SYSTEM
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System *getSystemPtr() { return cpu->system; }
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PhysicalMemory *getPhysMemPtr() { return cpu->physmem; }
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TheISA::ITB *getITBPtr() { return cpu->itb; }
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TheISA::DTB * getDTBPtr() { return cpu->dtb; }
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Kernel::Statistics *getKernelStats()
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{ return thread->getKernelStats(); }
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FunctionalPort *getPhysPort() { return thread->getPhysPort(); }
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VirtualPort *getVirtPort(ThreadContext *tc = NULL)
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{ return thread->getVirtPort(tc); }
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void delVirtPort(VirtualPort *vp);
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#else
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TranslatingPort *getMemPort() { return thread->getMemPort(); }
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Process *getProcessPtr() { return thread->getProcessPtr(); }
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#endif
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Status status() const { return thread->status(); }
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void setStatus(Status new_status);
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/// Set the status to Active. Optional delay indicates number of
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/// cycles to wait before beginning execution.
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void activate(int delay = 1);
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/// Set the status to Suspended.
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void suspend();
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/// Set the status to Unallocated.
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void deallocate(int delay = 0);
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/// Set the status to Halted.
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void halt();
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#if FULL_SYSTEM
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void dumpFuncProfile();
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#endif
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void takeOverFrom(ThreadContext *old_context);
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void regStats(const std::string &name);
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void serialize(std::ostream &os);
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void unserialize(Checkpoint *cp, const std::string §ion);
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#if FULL_SYSTEM
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EndQuiesceEvent *getQuiesceEvent();
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Tick readLastActivate();
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Tick readLastSuspend();
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void profileClear();
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void profileSample();
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#endif
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int getThreadNum();
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// Also somewhat obnoxious. Really only used for the TLB fault.
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TheISA::MachInst getInst();
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void copyArchRegs(ThreadContext *tc);
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void clearArchRegs();
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uint64_t readIntReg(int reg_idx);
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FloatReg readFloatReg(int reg_idx, int width);
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FloatReg readFloatReg(int reg_idx);
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FloatRegBits readFloatRegBits(int reg_idx, int width);
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FloatRegBits readFloatRegBits(int reg_idx);
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void setIntReg(int reg_idx, uint64_t val);
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void setFloatReg(int reg_idx, FloatReg val, int width);
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void setFloatReg(int reg_idx, FloatReg val);
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void setFloatRegBits(int reg_idx, FloatRegBits val, int width);
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void setFloatRegBits(int reg_idx, FloatRegBits val);
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uint64_t readPC() { return thread->PC; }
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void setPC(Addr val);
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uint64_t readNextPC() { return thread->nextPC; }
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void setNextPC(Addr val);
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uint64_t readNextNPC()
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{
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return 0;
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}
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void setNextNPC(uint64_t val)
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{ }
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public:
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// ISA stuff:
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MiscReg readMiscReg(int misc_reg);
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MiscReg readMiscRegWithEffect(int misc_reg);
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void setMiscReg(int misc_reg, const MiscReg &val);
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void setMiscRegWithEffect(int misc_reg, const MiscReg &val);
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unsigned readStCondFailures()
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{ return thread->storeCondFailures; }
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void setStCondFailures(unsigned sc_failures)
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{ thread->storeCondFailures = sc_failures; }
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#if FULL_SYSTEM
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bool inPalMode() { return cpu->inPalMode(); }
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#endif
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bool misspeculating() { return false; }
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#if !FULL_SYSTEM
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TheISA::IntReg getSyscallArg(int i)
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{ return thread->renameTable[TheISA::ArgumentReg0 + i]->readIntResult(); }
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// used to shift args for indirect syscall
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void setSyscallArg(int i, TheISA::IntReg val)
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{ thread->renameTable[TheISA::ArgumentReg0 + i]->setIntResult(i); }
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void setSyscallReturn(SyscallReturn return_value)
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{ cpu->setSyscallReturn(return_value, thread->readTid()); }
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Counter readFuncExeInst() { return thread->funcExeInst; }
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void setFuncExeInst(Counter new_val)
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{ thread->funcExeInst = new_val; }
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#endif
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void changeRegFileContext(TheISA::RegContextParam param,
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TheISA::RegContextVal val)
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{ panic("Not supported on Alpha!"); }
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};
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// Ozone specific thread context
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OzoneTC ozoneTC;
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// Thread context to be used
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ThreadContext *tc;
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// Checker thread context; will wrap the OzoneTC if a checker is
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// being used.
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ThreadContext *checkerTC;
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typedef OzoneThreadState<Impl> ImplState;
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private:
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// Committed thread state for the OzoneCPU.
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OzoneThreadState<Impl> thread;
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public:
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// main simulation loop (one cycle)
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void tick();
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std::set<InstSeqNum> snList;
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std::set<Addr> lockAddrList;
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private:
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struct TickEvent : public Event
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{
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OzoneCPU *cpu;
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int width;
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TickEvent(OzoneCPU *c, int w);
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void process();
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const char *description();
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};
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TickEvent tickEvent;
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/// Schedule tick event, regardless of its current state.
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void scheduleTickEvent(int delay)
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{
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if (tickEvent.squashed())
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tickEvent.reschedule(curTick + cycles(delay));
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else if (!tickEvent.scheduled())
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tickEvent.schedule(curTick + cycles(delay));
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}
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/// Unschedule tick event, regardless of its current state.
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void unscheduleTickEvent()
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{
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if (tickEvent.scheduled())
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tickEvent.squash();
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}
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public:
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enum Status {
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Running,
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Idle,
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SwitchedOut
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};
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Status _status;
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public:
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void post_interrupt(int int_num, int index);
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void zero_fill_64(Addr addr) {
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static int warned = 0;
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if (!warned) {
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warn ("WH64 is not implemented");
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warned = 1;
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}
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};
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typedef typename Impl::Params Params;
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OzoneCPU(Params *params);
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virtual ~OzoneCPU();
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void init();
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public:
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BaseCPU *getCpuPtr() { return this; }
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void setCpuId(int id) { cpuId = id; }
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int readCpuId() { return cpuId; }
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int cpuId;
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void switchOut();
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void signalSwitched();
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void takeOverFrom(BaseCPU *oldCPU);
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int switchCount;
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#if FULL_SYSTEM
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Addr dbg_vtophys(Addr addr);
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bool interval_stats;
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TheISA::ITB *itb;
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TheISA::DTB *dtb;
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System *system;
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PhysicalMemory *physmem;
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#endif
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virtual Port *getPort(const std::string &name, int idx);
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FrontEnd *frontEnd;
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BackEnd *backEnd;
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private:
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Status status() const { return _status; }
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void setStatus(Status new_status) { _status = new_status; }
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virtual void activateContext(int thread_num, int delay);
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virtual void suspendContext(int thread_num);
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virtual void deallocateContext(int thread_num, int delay);
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virtual void haltContext(int thread_num);
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// statistics
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virtual void regStats();
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virtual void resetStats();
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// number of simulated instructions
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public:
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Counter numInst;
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Counter startNumInst;
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virtual Counter totalInstructions() const
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{
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return numInst - startNumInst;
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}
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private:
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// number of simulated loads
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Counter numLoad;
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Counter startNumLoad;
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// number of idle cycles
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Stats::Average<> notIdleFraction;
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Stats::Formula idleFraction;
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public:
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virtual void serialize(std::ostream &os);
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virtual void unserialize(Checkpoint *cp, const std::string §ion);
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#if FULL_SYSTEM
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/** Translates instruction requestion. */
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Fault translateInstReq(RequestPtr &req, OzoneThreadState<Impl> *thread)
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{
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return itb->translate(req, thread->getTC());
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}
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/** Translates data read request. */
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Fault translateDataReadReq(RequestPtr &req, OzoneThreadState<Impl> *thread)
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{
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return dtb->translate(req, thread->getTC(), false);
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}
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/** Translates data write request. */
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Fault translateDataWriteReq(RequestPtr &req, OzoneThreadState<Impl> *thread)
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{
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return dtb->translate(req, thread->getTC(), true);
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}
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#else
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/** Translates instruction requestion in syscall emulation mode. */
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Fault translateInstReq(RequestPtr &req, OzoneThreadState<Impl> *thread)
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{
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return thread->getProcessPtr()->pTable->translate(req);
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}
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/** Translates data read request in syscall emulation mode. */
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Fault translateDataReadReq(RequestPtr &req, OzoneThreadState<Impl> *thread)
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{
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return thread->getProcessPtr()->pTable->translate(req);
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}
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/** Translates data write request in syscall emulation mode. */
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Fault translateDataWriteReq(RequestPtr &req, OzoneThreadState<Impl> *thread)
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{
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return thread->getProcessPtr()->pTable->translate(req);
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}
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#endif
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/** Old CPU read from memory function. No longer used. */
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template <class T>
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Fault read(Request *req, T &data)
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{
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#if 0
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#if FULL_SYSTEM && defined(TARGET_ALPHA)
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if (req->isLocked()) {
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req->xc->setMiscReg(TheISA::Lock_Addr_DepTag, req->paddr);
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req->xc->setMiscReg(TheISA::Lock_Flag_DepTag, true);
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}
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#endif
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if (req->isLocked()) {
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lockAddrList.insert(req->paddr);
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lockFlag = true;
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}
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#endif
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Fault error;
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error = this->mem->read(req, data);
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data = gtoh(data);
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return error;
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}
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/** CPU read function, forwards read to LSQ. */
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template <class T>
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Fault read(Request *req, T &data, int load_idx)
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{
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return backEnd->read(req, data, load_idx);
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}
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/** Old CPU write to memory function. No longer used. */
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template <class T>
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Fault write(Request *req, T &data)
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{
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#if 0
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#if FULL_SYSTEM && defined(TARGET_ALPHA)
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ExecContext *xc;
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// If this is a store conditional, act appropriately
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if (req->isLocked()) {
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xc = req->xc;
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if (req->isUncacheable()) {
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// Don't update result register (see stq_c in isa_desc)
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req->result = 2;
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xc->setStCondFailures(0);//Needed? [RGD]
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} else {
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bool lock_flag = xc->readMiscReg(TheISA::Lock_Flag_DepTag);
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Addr lock_addr = xc->readMiscReg(TheISA::Lock_Addr_DepTag);
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req->result = lock_flag;
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if (!lock_flag ||
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((lock_addr & ~0xf) != (req->paddr & ~0xf))) {
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xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
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xc->setStCondFailures(xc->readStCondFailures() + 1);
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if (((xc->readStCondFailures()) % 100000) == 0) {
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std::cerr << "Warning: "
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<< xc->readStCondFailures()
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<< " consecutive store conditional failures "
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<< "on cpu " << req->xc->readCpuId()
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<< std::endl;
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}
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return NoFault;
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}
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else xc->setStCondFailures(0);
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}
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}
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// Need to clear any locked flags on other proccessors for
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// this address. Only do this for succsful Store Conditionals
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// and all other stores (WH64?). Unsuccessful Store
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// Conditionals would have returned above, and wouldn't fall
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// through.
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for (int i = 0; i < this->system->threadContexts.size(); i++){
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xc = this->system->threadContexts[i];
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if ((xc->readMiscReg(TheISA::Lock_Addr_DepTag) & ~0xf) ==
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(req->paddr & ~0xf)) {
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xc->setMiscReg(TheISA::Lock_Flag_DepTag, false);
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}
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}
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#endif
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if (req->isLocked()) {
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if (req->isUncacheable()) {
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req->result = 2;
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} else {
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if (this->lockFlag) {
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if (lockAddrList.find(req->paddr) !=
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lockAddrList.end()) {
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req->result = 1;
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} else {
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req->result = 0;
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return NoFault;
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}
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} else {
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req->result = 0;
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return NoFault;
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}
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}
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}
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#endif
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return this->mem->write(req, (T)htog(data));
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}
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/** CPU write function, forwards write to LSQ. */
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template <class T>
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Fault write(Request *req, T &data, int store_idx)
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{
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return backEnd->write(req, data, store_idx);
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}
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void prefetch(Addr addr, unsigned flags)
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{
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// need to do this...
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}
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void writeHint(Addr addr, int size, unsigned flags)
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{
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// need to do this...
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}
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Fault copySrcTranslate(Addr src);
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Fault copy(Addr dest);
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public:
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void squashFromTC();
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void dumpInsts() { frontEnd->dumpInsts(); }
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#if FULL_SYSTEM
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Fault hwrei();
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bool inPalMode() { return AlphaISA::PcPAL(thread.PC); }
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bool inPalMode(Addr pc) { return AlphaISA::PcPAL(pc); }
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bool simPalCheck(int palFunc);
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void processInterrupts();
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#else
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void syscall(uint64_t &callnum);
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void setSyscallReturn(SyscallReturn return_value, int tid);
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#endif
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ThreadContext *tcBase() { return tc; }
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struct CommStruct {
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InstSeqNum doneSeqNum;
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InstSeqNum nonSpecSeqNum;
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bool uncached;
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unsigned lqIdx;
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bool stall;
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};
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InstSeqNum globalSeqNum;
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TimeBuffer<CommStruct> comm;
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bool decoupledFrontEnd;
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bool lockFlag;
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Stats::Scalar<> quiesceCycles;
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Checker<DynInstPtr> *checker;
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};
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#endif // __CPU_OZONE_CPU_HH__
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