2231 lines
256 KiB
Plaintext
2231 lines
256 KiB
Plaintext
|
|
---------- Begin Simulation Statistics ----------
|
|
sim_seconds 2.817967 # Number of seconds simulated
|
|
sim_ticks 2817967230500 # Number of ticks simulated
|
|
final_tick 2817967230500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
|
|
sim_freq 1000000000000 # Frequency of simulated ticks
|
|
host_inst_rate 295085 # Simulator instruction rate (inst/s)
|
|
host_op_rate 358305 # Simulator op (including micro ops) rate (op/s)
|
|
host_tick_rate 6587585543 # Simulator tick rate (ticks/s)
|
|
host_mem_usage 567284 # Number of bytes of host memory used
|
|
host_seconds 427.77 # Real time elapsed on the host
|
|
sim_insts 126228232 # Number of instructions simulated
|
|
sim_ops 153272049 # Number of ops (including micro ops) simulated
|
|
system.voltage_domain.voltage 1 # Voltage in Volts
|
|
system.clk_domain.clock 1000 # Clock period in ticks
|
|
system.physmem.bytes_read::cpu0.dtb.walker 256 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu0.itb.walker 64 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu0.inst 652964 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu0.data 4386528 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu1.inst 130944 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu1.data 1051396 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu2.dtb.walker 6080 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu2.inst 516736 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::cpu2.data 4232960 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::realview.ide 960 # Number of bytes read from this memory
|
|
system.physmem.bytes_read::total 10978952 # Number of bytes read from this memory
|
|
system.physmem.bytes_inst_read::cpu0.inst 652964 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_inst_read::cpu1.inst 130944 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_inst_read::cpu2.inst 516736 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_inst_read::total 1300644 # Number of instructions bytes read from this memory
|
|
system.physmem.bytes_written::writebacks 5946048 # Number of bytes written to this memory
|
|
system.physmem.bytes_written::cpu0.data 17516 # Number of bytes written to this memory
|
|
system.physmem.bytes_written::cpu1.data 8 # Number of bytes written to this memory
|
|
system.physmem.bytes_written::realview.ide 2318336 # Number of bytes written to this memory
|
|
system.physmem.bytes_written::total 8281908 # Number of bytes written to this memory
|
|
system.physmem.num_reads::cpu0.dtb.walker 4 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu0.itb.walker 1 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu0.inst 18656 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu0.data 69058 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu1.inst 2046 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu1.data 16429 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu2.dtb.walker 95 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu2.inst 8074 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::cpu2.data 66140 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::realview.ide 15 # Number of read requests responded to by this memory
|
|
system.physmem.num_reads::total 180519 # Number of read requests responded to by this memory
|
|
system.physmem.num_writes::writebacks 92907 # Number of write requests responded to by this memory
|
|
system.physmem.num_writes::cpu0.data 4379 # Number of write requests responded to by this memory
|
|
system.physmem.num_writes::cpu1.data 2 # Number of write requests responded to by this memory
|
|
system.physmem.num_writes::realview.ide 36224 # Number of write requests responded to by this memory
|
|
system.physmem.num_writes::total 133512 # Number of write requests responded to by this memory
|
|
system.physmem.bw_read::cpu0.dtb.walker 91 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu0.itb.walker 23 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu0.inst 231715 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu0.data 1556628 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu1.dtb.walker 23 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu1.inst 46468 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu1.data 373104 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu2.dtb.walker 2158 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu2.inst 183372 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::cpu2.data 1502132 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::realview.ide 341 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_read::total 3896054 # Total read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::cpu0.inst 231715 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::cpu1.inst 46468 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::cpu2.inst 183372 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_inst_read::total 461554 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::writebacks 2110049 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::cpu0.data 6216 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::cpu1.data 3 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::realview.ide 822698 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_write::total 2938965 # Write bandwidth from this memory (bytes/s)
|
|
system.physmem.bw_total::writebacks 2110049 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu0.dtb.walker 91 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu0.itb.walker 23 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu0.inst 231715 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu0.data 1562844 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu1.dtb.walker 23 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu1.inst 46468 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu1.data 373107 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu2.dtb.walker 2158 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu2.inst 183372 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::cpu2.data 1502132 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::realview.ide 823039 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.bw_total::total 6835019 # Total bandwidth to/from this memory (bytes/s)
|
|
system.physmem.readReqs 92786 # Number of read requests accepted
|
|
system.physmem.writeReqs 67811 # Number of write requests accepted
|
|
system.physmem.readBursts 92786 # Number of DRAM read bursts, including those serviced by the write queue
|
|
system.physmem.writeBursts 67811 # Number of DRAM write bursts, including those merged in the write queue
|
|
system.physmem.bytesReadDRAM 5933952 # Total number of bytes read from DRAM
|
|
system.physmem.bytesReadWrQ 4352 # Total number of bytes read from write queue
|
|
system.physmem.bytesWritten 4338688 # Total number of bytes written to DRAM
|
|
system.physmem.bytesReadSys 5938244 # Total read bytes from the system interface side
|
|
system.physmem.bytesWrittenSys 4339784 # Total written bytes from the system interface side
|
|
system.physmem.servicedByWrQ 68 # Number of DRAM read bursts serviced by the write queue
|
|
system.physmem.mergedWrBursts 1 # Number of DRAM write bursts merged with an existing one
|
|
system.physmem.neitherReadNorWriteReqs 2462 # Number of requests that are neither read nor write
|
|
system.physmem.perBankRdBursts::0 6041 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::1 5815 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::2 5576 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::3 6089 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::4 5555 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::5 5469 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::6 6176 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::7 6795 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::8 6466 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::9 6395 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::10 5737 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::11 5121 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::12 5306 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::13 5463 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::14 5326 # Per bank write bursts
|
|
system.physmem.perBankRdBursts::15 5388 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::0 4259 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::1 3941 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::2 4227 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::3 4690 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::4 4139 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::5 4140 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::6 4396 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::7 4907 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::8 4559 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::9 4641 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::10 4210 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::11 3556 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::12 4023 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::13 4273 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::14 3931 # Per bank write bursts
|
|
system.physmem.perBankWrBursts::15 3900 # Per bank write bursts
|
|
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
|
|
system.physmem.numWrRetry 8 # Number of times write queue was full causing retry
|
|
system.physmem.totGap 2816401088000 # Total gap between requests
|
|
system.physmem.readPktSize::0 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::1 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::2 1 # Read request sizes (log2)
|
|
system.physmem.readPktSize::3 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::4 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::5 0 # Read request sizes (log2)
|
|
system.physmem.readPktSize::6 92785 # Read request sizes (log2)
|
|
system.physmem.writePktSize::0 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::1 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::2 2 # Write request sizes (log2)
|
|
system.physmem.writePktSize::3 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::4 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::5 0 # Write request sizes (log2)
|
|
system.physmem.writePktSize::6 67809 # Write request sizes (log2)
|
|
system.physmem.rdQLenPdf::0 61124 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::1 28127 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::2 2946 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::3 516 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
|
|
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::0 57 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::1 54 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::2 53 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::3 53 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::4 53 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::5 51 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::6 51 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::7 51 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::8 51 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::9 52 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::10 49 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::11 49 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::12 49 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::13 49 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::14 49 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::15 1108 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::16 1440 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::17 2578 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::18 3235 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::19 3366 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::20 3812 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::21 3970 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::22 4286 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::23 4627 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::24 5132 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::25 4766 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::26 4458 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::27 4166 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::28 4221 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::29 3504 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::30 3413 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::31 3495 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::32 3325 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::33 165 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::34 138 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::35 132 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::36 127 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::37 120 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::38 109 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::39 122 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::40 111 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::41 107 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::42 96 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::43 96 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::44 85 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::45 84 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::46 81 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::47 77 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::48 60 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::49 60 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::50 55 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::51 41 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::52 34 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::53 28 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::54 27 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::55 22 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::56 25 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::57 23 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::58 20 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::59 22 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::60 24 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::61 19 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::62 12 # What write queue length does an incoming req see
|
|
system.physmem.wrQLenPdf::63 15 # What write queue length does an incoming req see
|
|
system.physmem.bytesPerActivate::samples 32876 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::mean 312.458450 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::gmean 179.413676 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::stdev 339.664106 # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::0-127 12770 38.84% 38.84% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::128-255 7721 23.49% 62.33% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::256-383 2991 9.10% 71.43% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::384-511 1712 5.21% 76.63% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::512-639 1344 4.09% 80.72% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::640-767 774 2.35% 83.08% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::768-895 537 1.63% 84.71% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::896-1023 552 1.68% 86.39% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::1024-1151 4475 13.61% 100.00% # Bytes accessed per row activation
|
|
system.physmem.bytesPerActivate::total 32876 # Bytes accessed per row activation
|
|
system.physmem.rdPerTurnAround::samples 3255 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::mean 28.482642 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::stdev 540.024143 # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::0-1023 3254 99.97% 99.97% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::30720-31743 1 0.03% 100.00% # Reads before turning the bus around for writes
|
|
system.physmem.rdPerTurnAround::total 3255 # Reads before turning the bus around for writes
|
|
system.physmem.wrPerTurnAround::samples 3255 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::mean 20.827035 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::gmean 18.877074 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::stdev 13.588559 # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::0-3 4 0.12% 0.12% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::4-7 2 0.06% 0.18% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::8-11 2 0.06% 0.25% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::12-15 2 0.06% 0.31% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::16-19 2714 83.38% 83.69% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::20-23 41 1.26% 84.95% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::24-27 32 0.98% 85.93% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::28-31 140 4.30% 90.23% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::32-35 131 4.02% 94.25% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::36-39 8 0.25% 94.50% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::40-43 4 0.12% 94.62% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::44-47 9 0.28% 94.90% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::48-51 18 0.55% 95.45% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::52-55 3 0.09% 95.55% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::56-59 7 0.22% 95.76% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::60-63 4 0.12% 95.88% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::64-67 99 3.04% 98.92% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::68-71 2 0.06% 98.99% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::72-75 4 0.12% 99.11% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::76-79 3 0.09% 99.20% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::80-83 3 0.09% 99.29% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::88-91 1 0.03% 99.32% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::96-99 3 0.09% 99.42% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::108-111 2 0.06% 99.48% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::112-115 2 0.06% 99.54% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::128-131 9 0.28% 99.82% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::132-135 1 0.03% 99.85% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::136-139 1 0.03% 99.88% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::140-143 2 0.06% 99.94% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::144-147 1 0.03% 99.97% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::152-155 1 0.03% 100.00% # Writes before turning the bus around for reads
|
|
system.physmem.wrPerTurnAround::total 3255 # Writes before turning the bus around for reads
|
|
system.physmem.totQLat 1187084500 # Total ticks spent queuing
|
|
system.physmem.totMemAccLat 2925547000 # Total ticks spent from burst creation until serviced by the DRAM
|
|
system.physmem.totBusLat 463590000 # Total ticks spent in databus transfers
|
|
system.physmem.avgQLat 12803.17 # Average queueing delay per DRAM burst
|
|
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
|
|
system.physmem.avgMemAccLat 31553.17 # Average memory access latency per DRAM burst
|
|
system.physmem.avgRdBW 2.11 # Average DRAM read bandwidth in MiByte/s
|
|
system.physmem.avgWrBW 1.54 # Average achieved write bandwidth in MiByte/s
|
|
system.physmem.avgRdBWSys 2.11 # Average system read bandwidth in MiByte/s
|
|
system.physmem.avgWrBWSys 1.54 # Average system write bandwidth in MiByte/s
|
|
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
|
|
system.physmem.busUtil 0.03 # Data bus utilization in percentage
|
|
system.physmem.busUtilRead 0.02 # Data bus utilization in percentage for reads
|
|
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
|
|
system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing
|
|
system.physmem.avgWrQLen 8.01 # Average write queue length when enqueuing
|
|
system.physmem.readRowHits 76742 # Number of row buffer hits during reads
|
|
system.physmem.writeRowHits 50891 # Number of row buffer hits during writes
|
|
system.physmem.readRowHitRate 82.77 # Row buffer hit rate for reads
|
|
system.physmem.writeRowHitRate 75.05 # Row buffer hit rate for writes
|
|
system.physmem.avgGap 17537071.60 # Average gap between requests
|
|
system.physmem.pageHitRate 79.51 # Row buffer hit rate, read and write combined
|
|
system.physmem.memoryStateTime::IDLE 2704795503250 # Time in different power states
|
|
system.physmem.memoryStateTime::REF 94097900000 # Time in different power states
|
|
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem.memoryStateTime::ACT 19068171250 # Time in different power states
|
|
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem.actEnergy::0 130016880 # Energy for activate commands per rank (pJ)
|
|
system.physmem.actEnergy::1 118525680 # Energy for activate commands per rank (pJ)
|
|
system.physmem.preEnergy::0 70941750 # Energy for precharge commands per rank (pJ)
|
|
system.physmem.preEnergy::1 64671750 # Energy for precharge commands per rank (pJ)
|
|
system.physmem.readEnergy::0 370624800 # Energy for read commands per rank (pJ)
|
|
system.physmem.readEnergy::1 352544400 # Energy for read commands per rank (pJ)
|
|
system.physmem.writeEnergy::0 224849520 # Energy for write commands per rank (pJ)
|
|
system.physmem.writeEnergy::1 214442640 # Energy for write commands per rank (pJ)
|
|
system.physmem.refreshEnergy::0 184055492400 # Energy for refresh commands per rank (pJ)
|
|
system.physmem.refreshEnergy::1 184055492400 # Energy for refresh commands per rank (pJ)
|
|
system.physmem.actBackEnergy::0 70844118390 # Energy for active background per rank (pJ)
|
|
system.physmem.actBackEnergy::1 70005569445 # Energy for active background per rank (pJ)
|
|
system.physmem.preBackEnergy::0 1628632585500 # Energy for precharge background per rank (pJ)
|
|
system.physmem.preBackEnergy::1 1629368154750 # Energy for precharge background per rank (pJ)
|
|
system.physmem.totalEnergy::0 1884328629240 # Total energy per rank (pJ)
|
|
system.physmem.totalEnergy::1 1884179401065 # Total energy per rank (pJ)
|
|
system.physmem.averagePower::0 668.685154 # Core power per rank (mW)
|
|
system.physmem.averagePower::1 668.632198 # Core power per rank (mW)
|
|
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
|
|
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
|
|
system.realview.nvmem.bw_read::cpu0.inst 7 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_read::total 7 # Total read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::cpu0.inst 7 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_inst_read::total 7 # Instruction read bandwidth from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::cpu0.inst 7 # Total bandwidth to/from this memory (bytes/s)
|
|
system.realview.nvmem.bw_total::total 7 # Total bandwidth to/from this memory (bytes/s)
|
|
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
|
|
system.cf0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
|
|
system.cf0.dma_read_txs 1 # Number of DMA read transactions (not PRD).
|
|
system.cf0.dma_write_full_pages 540 # Number of full page size DMA writes.
|
|
system.cf0.dma_write_bytes 2318336 # Number of bytes transfered via DMA writes.
|
|
system.cf0.dma_write_txs 631 # Number of DMA write transactions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu0.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.dtb.read_hits 14476193 # DTB read hits
|
|
system.cpu0.dtb.read_misses 4879 # DTB read misses
|
|
system.cpu0.dtb.write_hits 11073999 # DTB write hits
|
|
system.cpu0.dtb.write_misses 930 # DTB write misses
|
|
system.cpu0.dtb.flush_tlb 189 # Number of times complete TLB was flushed
|
|
system.cpu0.dtb.flush_tlb_mva 442 # Number of times TLB was flushed by MVA
|
|
system.cpu0.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.dtb.flush_entries 3272 # Number of entries that have been flushed from TLB
|
|
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.dtb.prefetch_faults 946 # Number of TLB faults due to prefetch
|
|
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.dtb.perms_faults 215 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.dtb.read_accesses 14481072 # DTB read accesses
|
|
system.cpu0.dtb.write_accesses 11074929 # DTB write accesses
|
|
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.dtb.hits 25550192 # DTB hits
|
|
system.cpu0.dtb.misses 5809 # DTB misses
|
|
system.cpu0.dtb.accesses 25556001 # DTB accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu0.itb.inst_hits 67954476 # ITB inst hits
|
|
system.cpu0.itb.inst_misses 2811 # ITB inst misses
|
|
system.cpu0.itb.read_hits 0 # DTB read hits
|
|
system.cpu0.itb.read_misses 0 # DTB read misses
|
|
system.cpu0.itb.write_hits 0 # DTB write hits
|
|
system.cpu0.itb.write_misses 0 # DTB write misses
|
|
system.cpu0.itb.flush_tlb 189 # Number of times complete TLB was flushed
|
|
system.cpu0.itb.flush_tlb_mva 442 # Number of times TLB was flushed by MVA
|
|
system.cpu0.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu0.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu0.itb.flush_entries 2005 # Number of entries that have been flushed from TLB
|
|
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu0.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu0.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu0.itb.inst_accesses 67957287 # ITB inst accesses
|
|
system.cpu0.itb.hits 67954476 # DTB hits
|
|
system.cpu0.itb.misses 2811 # DTB misses
|
|
system.cpu0.itb.accesses 67957287 # DTB accesses
|
|
system.cpu0.numCycles 82556827 # number of cpu cycles simulated
|
|
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu0.committedInsts 66160398 # Number of instructions committed
|
|
system.cpu0.committedOps 80652664 # Number of ops (including micro ops) committed
|
|
system.cpu0.num_int_alu_accesses 70891762 # Number of integer alu accesses
|
|
system.cpu0.num_fp_alu_accesses 5582 # Number of float alu accesses
|
|
system.cpu0.num_func_calls 7292056 # number of times a function call or return occured
|
|
system.cpu0.num_conditional_control_insts 8778747 # number of instructions that are conditional controls
|
|
system.cpu0.num_int_insts 70891762 # number of integer instructions
|
|
system.cpu0.num_fp_insts 5582 # number of float instructions
|
|
system.cpu0.num_int_register_reads 131506051 # number of times the integer registers were read
|
|
system.cpu0.num_int_register_writes 49334508 # number of times the integer registers were written
|
|
system.cpu0.num_fp_register_reads 4358 # number of times the floating registers were read
|
|
system.cpu0.num_fp_register_writes 1228 # number of times the floating registers were written
|
|
system.cpu0.num_cc_register_reads 245869189 # number of times the CC registers were read
|
|
system.cpu0.num_cc_register_writes 29383374 # number of times the CC registers were written
|
|
system.cpu0.num_mem_refs 26220572 # number of memory refs
|
|
system.cpu0.num_load_insts 14652138 # Number of load instructions
|
|
system.cpu0.num_store_insts 11568434 # Number of store instructions
|
|
system.cpu0.num_idle_cycles 77950738.874403 # Number of idle cycles
|
|
system.cpu0.num_busy_cycles 4606088.125597 # Number of busy cycles
|
|
system.cpu0.not_idle_fraction 0.055793 # Percentage of non-idle cycles
|
|
system.cpu0.idle_fraction 0.944207 # Percentage of idle cycles
|
|
system.cpu0.Branches 16465662 # Number of branches fetched
|
|
system.cpu0.op_class::No_OpClass 2193 0.00% 0.00% # Class of executed instruction
|
|
system.cpu0.op_class::IntAlu 55785323 67.97% 67.97% # Class of executed instruction
|
|
system.cpu0.op_class::IntMult 58705 0.07% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::IntDiv 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::FloatAdd 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::FloatCmp 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::FloatCvt 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::FloatMult 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::FloatDiv 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::FloatSqrt 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAdd 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAddAcc 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::SimdAlu 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::SimdCmp 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::SimdCvt 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMisc 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMult 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::SimdMultAcc 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::SimdShift 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::SimdShiftAcc 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::SimdSqrt 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatAdd 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatAlu 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatCmp 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatCvt 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatDiv 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMisc 4540 0.01% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMult 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatMultAcc 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::SimdFloatSqrt 0 0.00% 68.05% # Class of executed instruction
|
|
system.cpu0.op_class::MemRead 14652138 17.85% 85.90% # Class of executed instruction
|
|
system.cpu0.op_class::MemWrite 11568434 14.10% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu0.op_class::total 82071333 # Class of executed instruction
|
|
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu0.kern.inst.quiesce 3056 # number of quiesce instructions executed
|
|
system.cpu0.dcache.tags.replacements 833736 # number of replacements
|
|
system.cpu0.dcache.tags.tagsinuse 511.996800 # Cycle average of tags in use
|
|
system.cpu0.dcache.tags.total_refs 47002068 # Total number of references to valid blocks.
|
|
system.cpu0.dcache.tags.sampled_refs 834248 # Sample count of references to valid blocks.
|
|
system.cpu0.dcache.tags.avg_refs 56.340642 # Average number of references to valid blocks.
|
|
system.cpu0.dcache.tags.warmup_cycle 23053500 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.dcache.tags.occ_blocks::cpu0.data 485.853503 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_blocks::cpu1.data 16.630840 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_blocks::cpu2.data 9.512458 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.948933 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.032482 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::cpu2.data 0.018579 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 304 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 16 # Occupied blocks per task id
|
|
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu0.dcache.tags.tag_accesses 198562219 # Number of tag accesses
|
|
system.cpu0.dcache.tags.data_accesses 198562219 # Number of data accesses
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 13788602 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::cpu1.data 4405053 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::cpu2.data 8513889 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::total 26707544 # number of ReadReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 10680609 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu1.data 3155163 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu2.data 5163362 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::total 18999134 # number of WriteReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::cpu0.data 190594 # number of SoftPFReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::cpu1.data 60628 # number of SoftPFReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::cpu2.data 130484 # number of SoftPFReq hits
|
|
system.cpu0.dcache.SoftPFReq_hits::total 381706 # number of SoftPFReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 235265 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 80498 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 135390 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.LoadLockedReq_hits::total 451153 # number of LoadLockedReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 236615 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 83018 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::cpu2.data 140051 # number of StoreCondReq hits
|
|
system.cpu0.dcache.StoreCondReq_hits::total 459684 # number of StoreCondReq hits
|
|
system.cpu0.dcache.demand_hits::cpu0.data 24469211 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::cpu1.data 7560216 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::cpu2.data 13677251 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::total 45706678 # number of demand (read+write) hits
|
|
system.cpu0.dcache.overall_hits::cpu0.data 24659805 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::cpu1.data 7620844 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::cpu2.data 13807735 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::total 46088384 # number of overall hits
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 190267 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::cpu1.data 59406 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::cpu2.data 315886 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::total 565559 # number of ReadReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 145430 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu1.data 33947 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu2.data 1529690 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::total 1709067 # number of WriteReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::cpu0.data 55022 # number of SoftPFReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::cpu1.data 20138 # number of SoftPFReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::cpu2.data 65538 # number of SoftPFReq misses
|
|
system.cpu0.dcache.SoftPFReq_misses::total 140698 # number of SoftPFReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 4446 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 3285 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 9694 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.LoadLockedReq_misses::total 17425 # number of LoadLockedReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu0.data 2 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::cpu2.data 13 # number of StoreCondReq misses
|
|
system.cpu0.dcache.StoreCondReq_misses::total 15 # number of StoreCondReq misses
|
|
system.cpu0.dcache.demand_misses::cpu0.data 335697 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::cpu1.data 93353 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::cpu2.data 1845576 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::total 2274626 # number of demand (read+write) misses
|
|
system.cpu0.dcache.overall_misses::cpu0.data 390719 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::cpu1.data 113491 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::cpu2.data 1911114 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::total 2415324 # number of overall misses
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 905367250 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 5265516623 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::total 6170883873 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1312551865 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 70768535678 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::total 72081087543 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 46450000 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 132109998 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_miss_latency::total 178559998 # number of LoadLockedReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 181001 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.StoreCondReq_miss_latency::total 181001 # number of StoreCondReq miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu1.data 2217919115 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu2.data 76034052301 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::total 78251971416 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu1.data 2217919115 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu2.data 76034052301 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::total 78251971416 # number of overall miss cycles
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 13978869 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::cpu1.data 4464459 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::cpu2.data 8829775 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::total 27273103 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 10826039 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu1.data 3189110 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu2.data 6693052 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::total 20708201 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::cpu0.data 245616 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::cpu1.data 80766 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::cpu2.data 196022 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.SoftPFReq_accesses::total 522404 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 239711 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 83783 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 145084 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.LoadLockedReq_accesses::total 468578 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 236617 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 83018 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 140064 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.StoreCondReq_accesses::total 459699 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 24804908 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::cpu1.data 7653569 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::cpu2.data 15522827 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::total 47981304 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 25050524 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu1.data 7734335 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu2.data 15718849 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::total 48503708 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.013611 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.013306 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.035775 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.020737 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.013433 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.010645 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.228549 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.082531 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::cpu0.data 0.224016 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::cpu1.data 0.249338 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::cpu2.data 0.334340 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_miss_rate::total 0.269328 # miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.018547 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.039208 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.066816 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.037187 # miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu0.data 0.000008 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000093 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000033 # miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.013533 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.012197 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu2.data 0.118894 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::total 0.047407 # miss rate for demand accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.015597 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.014674 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu2.data 0.121581 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::total 0.049797 # miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 15240.333468 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 16669.040803 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::total 10911.123107 # average ReadReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 38664.738121 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 46263.318501 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::total 42175.694425 # average WriteReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 14140.030441 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13628.017124 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 10247.345653 # average LoadLockedReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13923.153846 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 12066.733333 # average StoreCondReq miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 23758.412852 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 41198.006639 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::total 34402.126510 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 19542.687217 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 39785.199785 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::total 32398.126055 # average overall miss latency
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 376933 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 24988 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_mshrs 25127 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_targets 512 # number of cycles access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 15.001114 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets 48.804688 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.dcache.writebacks::writebacks 692581 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 692581 # number of writebacks
|
|
system.cpu0.dcache.ReadReq_mshr_hits::cpu1.data 108 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 154975 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_hits::total 155083 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 1409869 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::total 1409869 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu1.data 1934 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 6806 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 8740 # number of LoadLockedReq MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::cpu1.data 108 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::cpu2.data 1564844 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::total 1564952 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::cpu1.data 108 # number of overall MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::cpu2.data 1564844 # number of overall MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::total 1564952 # number of overall MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 59298 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 160911 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::total 220209 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 33947 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 119821 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::total 153768 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu1.data 19747 # number of SoftPFReq MSHR misses
|
|
system.cpu0.dcache.SoftPFReq_mshr_misses::cpu2.data 43923 # number of SoftPFReq MSHR misses
|
|
system.cpu0.dcache.SoftPFReq_mshr_misses::total 63670 # number of SoftPFReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1351 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 2888 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 4239 # number of LoadLockedReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 13 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.StoreCondReq_mshr_misses::total 13 # number of StoreCondReq MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu1.data 93245 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu2.data 280732 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::total 373977 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu1.data 112992 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu2.data 324655 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::total 437647 # number of overall MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 784144250 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 2133463687 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2917607937 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 1238610119 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 5440807950 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 6679418069 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu1.data 253219750 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::cpu2.data 658574506 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_latency::total 911794256 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 21611000 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 35862251 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 57473251 # number of LoadLockedReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 154999 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 154999 # number of StoreCondReq MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 2022754369 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 7574271637 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::total 9597026006 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 2275974119 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 8232846143 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::total 10508820262 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 1018414500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 1694074000 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 2712488500 # number of ReadReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 777507500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 1315307000 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2092814500 # number of WriteReq MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 1795922000 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 3009381000 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 4805303000 # number of overall MSHR uncacheable cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.013282 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.018224 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.008074 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.010645 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.017902 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007425 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu1.data 0.244496 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::cpu2.data 0.224072 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.SoftPFReq_mshr_miss_rate::total 0.121879 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.016125 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.019906 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.009047 # mshr miss rate for LoadLockedReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000093 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000028 # mshr miss rate for StoreCondReq accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.012183 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.018085 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.007794 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.014609 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.020654 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.009023 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 13223.789167 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 13258.656568 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 13249.267455 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 36486.585530 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 45407.799551 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 43438.284097 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu1.data 12823.200993 # average SoftPFReq mshr miss latency
|
|
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::cpu2.data 14993.841632 # average SoftPFReq mshr miss latency
|
|
system.cpu0.dcache.SoftPFReq_avg_mshr_miss_latency::total 14320.625978 # average SoftPFReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 15996.299038 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 12417.676939 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 13558.209719 # average LoadLockedReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11923 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11923 # average StoreCondReq mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 21692.899019 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 26980.435565 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 25662.075491 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 20142.789923 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 25358.753578 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24012.092536 # average overall mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.icache.tags.replacements 1798304 # number of replacements
|
|
system.cpu0.icache.tags.tagsinuse 511.545340 # Cycle average of tags in use
|
|
system.cpu0.icache.tags.total_refs 100886115 # Total number of references to valid blocks.
|
|
system.cpu0.icache.tags.sampled_refs 1798815 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.tags.avg_refs 56.084764 # Average number of references to valid blocks.
|
|
system.cpu0.icache.tags.warmup_cycle 10926866250 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.tags.occ_blocks::cpu0.inst 477.674781 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_blocks::cpu1.inst 21.513239 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_blocks::cpu2.inst 12.357321 # Average occupied blocks per requestor
|
|
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.932959 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.042018 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::cpu2.inst 0.024135 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_percent::total 0.999112 # Average percentage of cache occupancy
|
|
system.cpu0.icache.tags.occ_task_id_blocks::1024 511 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::0 115 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::1 235 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.age_task_id_blocks_1024::2 161 # Occupied blocks per task id
|
|
system.cpu0.icache.tags.occ_task_id_percent::1024 0.998047 # Percentage of cache occupancy per task id
|
|
system.cpu0.icache.tags.tag_accesses 104533981 # Number of tag accesses
|
|
system.cpu0.icache.tags.data_accesses 104533981 # Number of data accesses
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 67090111 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::cpu1.inst 21677596 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::cpu2.inst 12118408 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 100886115 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 67090111 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::cpu1.inst 21677596 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::cpu2.inst 12118408 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 100886115 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 67090111 # number of overall hits
|
|
system.cpu0.icache.overall_hits::cpu1.inst 21677596 # number of overall hits
|
|
system.cpu0.icache.overall_hits::cpu2.inst 12118408 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 100886115 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 866406 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::cpu1.inst 250233 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::cpu2.inst 732378 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 1849017 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 866406 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::cpu1.inst 250233 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::cpu2.inst 732378 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 1849017 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 866406 # number of overall misses
|
|
system.cpu0.icache.overall_misses::cpu1.inst 250233 # number of overall misses
|
|
system.cpu0.icache.overall_misses::cpu2.inst 732378 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 1849017 # number of overall misses
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 3390118000 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 10053892166 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::total 13444010166 # number of ReadReq miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu1.inst 3390118000 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu2.inst 10053892166 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::total 13444010166 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu1.inst 3390118000 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu2.inst 10053892166 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::total 13444010166 # number of overall miss cycles
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 67956517 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::cpu1.inst 21927829 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::cpu2.inst 12850786 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 102735132 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 67956517 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::cpu1.inst 21927829 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::cpu2.inst 12850786 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 102735132 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 67956517 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu1.inst 21927829 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu2.inst 12850786 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 102735132 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.012749 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.011412 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.056991 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.017998 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.012749 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.011412 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu2.inst 0.056991 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.017998 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.012749 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.011412 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu2.inst 0.056991 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.017998 # miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13547.845408 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13727.736450 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 7270.895923 # average ReadReq miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13547.845408 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13727.736450 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::total 7270.895923 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13547.845408 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13727.736450 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::total 7270.895923 # average overall miss latency
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 5362 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 334 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs 16.053892 # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 50167 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_hits::total 50167 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::cpu2.inst 50167 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::total 50167 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::cpu2.inst 50167 # number of overall MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::total 50167 # number of overall MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 250233 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 682211 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::total 932444 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu1.inst 250233 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu2.inst 682211 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::total 932444 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu1.inst 250233 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu2.inst 682211 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::total 932444 # number of overall MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 2888910000 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 8203668345 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 11092578345 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 2888910000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 8203668345 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::total 11092578345 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 2888910000 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 8203668345 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::total 11092578345 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.011412 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.053087 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009076 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.011412 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.053087 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::total 0.009076 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.011412 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.053087 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.009076 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11544.880172 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12025.118834 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11896.240788 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11544.880172 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 12025.118834 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11896.240788 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11544.880172 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 12025.118834 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11896.240788 # average overall mshr miss latency
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu1.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.dtb.read_hits 4634797 # DTB read hits
|
|
system.cpu1.dtb.read_misses 1583 # DTB read misses
|
|
system.cpu1.dtb.write_hits 3276695 # DTB write hits
|
|
system.cpu1.dtb.write_misses 231 # DTB write misses
|
|
system.cpu1.dtb.flush_tlb 166 # Number of times complete TLB was flushed
|
|
system.cpu1.dtb.flush_tlb_mva 105 # Number of times TLB was flushed by MVA
|
|
system.cpu1.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.dtb.flush_entries 1209 # Number of entries that have been flushed from TLB
|
|
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.dtb.prefetch_faults 225 # Number of TLB faults due to prefetch
|
|
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.dtb.perms_faults 52 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.dtb.read_accesses 4636380 # DTB read accesses
|
|
system.cpu1.dtb.write_accesses 3276926 # DTB write accesses
|
|
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.dtb.hits 7911492 # DTB hits
|
|
system.cpu1.dtb.misses 1814 # DTB misses
|
|
system.cpu1.dtb.accesses 7913306 # DTB accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu1.itb.inst_hits 21927829 # ITB inst hits
|
|
system.cpu1.itb.inst_misses 850 # ITB inst misses
|
|
system.cpu1.itb.read_hits 0 # DTB read hits
|
|
system.cpu1.itb.read_misses 0 # DTB read misses
|
|
system.cpu1.itb.write_hits 0 # DTB write hits
|
|
system.cpu1.itb.write_misses 0 # DTB write misses
|
|
system.cpu1.itb.flush_tlb 166 # Number of times complete TLB was flushed
|
|
system.cpu1.itb.flush_tlb_mva 105 # Number of times TLB was flushed by MVA
|
|
system.cpu1.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu1.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu1.itb.flush_entries 702 # Number of entries that have been flushed from TLB
|
|
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu1.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu1.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu1.itb.inst_accesses 21928679 # ITB inst accesses
|
|
system.cpu1.itb.hits 21927829 # DTB hits
|
|
system.cpu1.itb.misses 850 # DTB misses
|
|
system.cpu1.itb.accesses 21928679 # DTB accesses
|
|
system.cpu1.numCycles 158012697 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.committedInsts 21219424 # Number of instructions committed
|
|
system.cpu1.committedOps 25417661 # Number of ops (including micro ops) committed
|
|
system.cpu1.num_int_alu_accesses 22602393 # Number of integer alu accesses
|
|
system.cpu1.num_fp_alu_accesses 1642 # Number of float alu accesses
|
|
system.cpu1.num_func_calls 2405355 # number of times a function call or return occured
|
|
system.cpu1.num_conditional_control_insts 2700524 # number of instructions that are conditional controls
|
|
system.cpu1.num_int_insts 22602393 # number of integer instructions
|
|
system.cpu1.num_fp_insts 1642 # number of float instructions
|
|
system.cpu1.num_int_register_reads 41665364 # number of times the integer registers were read
|
|
system.cpu1.num_int_register_writes 15857744 # number of times the integer registers were written
|
|
system.cpu1.num_fp_register_reads 1194 # number of times the floating registers were read
|
|
system.cpu1.num_fp_register_writes 448 # number of times the floating registers were written
|
|
system.cpu1.num_cc_register_reads 92377254 # number of times the CC registers were read
|
|
system.cpu1.num_cc_register_writes 9370530 # number of times the CC registers were written
|
|
system.cpu1.num_mem_refs 8126107 # number of memory refs
|
|
system.cpu1.num_load_insts 4682037 # Number of load instructions
|
|
system.cpu1.num_store_insts 3444070 # Number of store instructions
|
|
system.cpu1.num_idle_cycles 151526887.882406 # Number of idle cycles
|
|
system.cpu1.num_busy_cycles 6485809.117594 # Number of busy cycles
|
|
system.cpu1.not_idle_fraction 0.041046 # Percentage of non-idle cycles
|
|
system.cpu1.idle_fraction 0.958954 # Percentage of idle cycles
|
|
system.cpu1.Branches 5257446 # Number of branches fetched
|
|
system.cpu1.op_class::No_OpClass 36 0.00% 0.00% # Class of executed instruction
|
|
system.cpu1.op_class::IntAlu 17987711 68.83% 68.83% # Class of executed instruction
|
|
system.cpu1.op_class::IntMult 19014 0.07% 68.90% # Class of executed instruction
|
|
system.cpu1.op_class::IntDiv 0 0.00% 68.90% # Class of executed instruction
|
|
system.cpu1.op_class::FloatAdd 0 0.00% 68.90% # Class of executed instruction
|
|
system.cpu1.op_class::FloatCmp 0 0.00% 68.90% # Class of executed instruction
|
|
system.cpu1.op_class::FloatCvt 0 0.00% 68.90% # Class of executed instruction
|
|
system.cpu1.op_class::FloatMult 0 0.00% 68.90% # Class of executed instruction
|
|
system.cpu1.op_class::FloatDiv 0 0.00% 68.90% # Class of executed instruction
|
|
system.cpu1.op_class::FloatSqrt 0 0.00% 68.90% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAdd 0 0.00% 68.90% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAddAcc 0 0.00% 68.90% # Class of executed instruction
|
|
system.cpu1.op_class::SimdAlu 0 0.00% 68.90% # Class of executed instruction
|
|
system.cpu1.op_class::SimdCmp 0 0.00% 68.90% # Class of executed instruction
|
|
system.cpu1.op_class::SimdCvt 0 0.00% 68.90% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMisc 0 0.00% 68.90% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMult 0 0.00% 68.90% # Class of executed instruction
|
|
system.cpu1.op_class::SimdMultAcc 0 0.00% 68.90% # Class of executed instruction
|
|
system.cpu1.op_class::SimdShift 0 0.00% 68.90% # Class of executed instruction
|
|
system.cpu1.op_class::SimdShiftAcc 0 0.00% 68.90% # Class of executed instruction
|
|
system.cpu1.op_class::SimdSqrt 0 0.00% 68.90% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatAdd 0 0.00% 68.90% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatAlu 0 0.00% 68.90% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatCmp 0 0.00% 68.90% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatCvt 0 0.00% 68.90% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatDiv 0 0.00% 68.90% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMisc 1154 0.00% 68.91% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMult 0 0.00% 68.91% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatMultAcc 0 0.00% 68.91% # Class of executed instruction
|
|
system.cpu1.op_class::SimdFloatSqrt 0 0.00% 68.91% # Class of executed instruction
|
|
system.cpu1.op_class::MemRead 4682037 17.92% 86.82% # Class of executed instruction
|
|
system.cpu1.op_class::MemWrite 3444070 13.18% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction
|
|
system.cpu1.op_class::total 26134022 # Class of executed instruction
|
|
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
|
|
system.cpu2.branchPred.lookups 17408373 # Number of BP lookups
|
|
system.cpu2.branchPred.condPredicted 9463731 # Number of conditional branches predicted
|
|
system.cpu2.branchPred.condIncorrect 400017 # Number of conditional branches incorrect
|
|
system.cpu2.branchPred.BTBLookups 10864152 # Number of BTB lookups
|
|
system.cpu2.branchPred.BTBHits 8142904 # Number of BTB hits
|
|
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu2.branchPred.BTBHitPct 74.952044 # BTB Hit Percentage
|
|
system.cpu2.branchPred.usedRAS 4071247 # Number of times the RAS was used to get a target.
|
|
system.cpu2.branchPred.RASInCorrect 21277 # Number of incorrect RAS predictions.
|
|
system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu2.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu2.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu2.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu2.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu2.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu2.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu2.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu2.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu2.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu2.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu2.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu2.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu2.dtb.read_hits 9689518 # DTB read hits
|
|
system.cpu2.dtb.read_misses 37575 # DTB read misses
|
|
system.cpu2.dtb.write_hits 7159699 # DTB write hits
|
|
system.cpu2.dtb.write_misses 5670 # DTB write misses
|
|
system.cpu2.dtb.flush_tlb 181 # Number of times complete TLB was flushed
|
|
system.cpu2.dtb.flush_tlb_mva 370 # Number of times TLB was flushed by MVA
|
|
system.cpu2.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu2.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu2.dtb.flush_entries 2438 # Number of entries that have been flushed from TLB
|
|
system.cpu2.dtb.align_faults 439 # Number of TLB faults due to alignment restrictions
|
|
system.cpu2.dtb.prefetch_faults 968 # Number of TLB faults due to prefetch
|
|
system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu2.dtb.perms_faults 417 # Number of TLB faults due to permissions restrictions
|
|
system.cpu2.dtb.read_accesses 9727093 # DTB read accesses
|
|
system.cpu2.dtb.write_accesses 7165369 # DTB write accesses
|
|
system.cpu2.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu2.dtb.hits 16849217 # DTB hits
|
|
system.cpu2.dtb.misses 43245 # DTB misses
|
|
system.cpu2.dtb.accesses 16892462 # DTB accesses
|
|
system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu2.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu2.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu2.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu2.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu2.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu2.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu2.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu2.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu2.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu2.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu2.itb.inst_hits 12852348 # ITB inst hits
|
|
system.cpu2.itb.inst_misses 6327 # ITB inst misses
|
|
system.cpu2.itb.read_hits 0 # DTB read hits
|
|
system.cpu2.itb.read_misses 0 # DTB read misses
|
|
system.cpu2.itb.write_hits 0 # DTB write hits
|
|
system.cpu2.itb.write_misses 0 # DTB write misses
|
|
system.cpu2.itb.flush_tlb 181 # Number of times complete TLB was flushed
|
|
system.cpu2.itb.flush_tlb_mva 370 # Number of times TLB was flushed by MVA
|
|
system.cpu2.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu2.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu2.itb.flush_entries 1763 # Number of entries that have been flushed from TLB
|
|
system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu2.itb.perms_faults 1147 # Number of TLB faults due to permissions restrictions
|
|
system.cpu2.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu2.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu2.itb.inst_accesses 12858675 # ITB inst accesses
|
|
system.cpu2.itb.hits 12852348 # DTB hits
|
|
system.cpu2.itb.misses 6327 # DTB misses
|
|
system.cpu2.itb.accesses 12858675 # DTB accesses
|
|
system.cpu2.numCycles 69828422 # number of cpu cycles simulated
|
|
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu2.fetch.icacheStallCycles 26736882 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu2.fetch.Insts 69116574 # Number of instructions fetch has processed
|
|
system.cpu2.fetch.Branches 17408373 # Number of branches that fetch encountered
|
|
system.cpu2.fetch.predictedBranches 12214151 # Number of branches that fetch has predicted taken
|
|
system.cpu2.fetch.Cycles 39634943 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu2.fetch.SquashCycles 2070237 # Number of cycles fetch has spent squashing
|
|
system.cpu2.fetch.TlbCycles 91943 # Number of cycles fetch has spent waiting for tlb
|
|
system.cpu2.fetch.MiscStallCycles 882 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu2.fetch.PendingDrainCycles 273 # Number of cycles fetch has spent waiting on pipes to drain
|
|
system.cpu2.fetch.PendingTrapStallCycles 329325 # Number of stall cycles due to pending traps
|
|
system.cpu2.fetch.PendingQuiesceStallCycles 101475 # Number of stall cycles due to pending quiesce instructions
|
|
system.cpu2.fetch.IcacheWaitRetryStallCycles 454 # Number of stall cycles due to full MSHR
|
|
system.cpu2.fetch.CacheLines 12850788 # Number of cache lines fetched
|
|
system.cpu2.fetch.IcacheSquashes 270289 # Number of outstanding Icache misses that were squashed
|
|
system.cpu2.fetch.ItlbSquashes 2773 # Number of outstanding ITLB misses that were squashed
|
|
system.cpu2.fetch.rateDist::samples 67931271 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::mean 1.222867 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::stdev 2.347613 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::0 49354668 72.65% 72.65% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::1 2396025 3.53% 76.18% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::2 1561758 2.30% 78.48% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::3 4875455 7.18% 85.66% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::4 1102436 1.62% 87.28% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::5 704861 1.04% 88.32% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::6 3873045 5.70% 94.02% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::7 751493 1.11% 95.13% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::8 3311530 4.87% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::total 67931271 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.branchRate 0.249302 # Number of branch fetches per cycle
|
|
system.cpu2.fetch.rate 0.989806 # Number of inst fetches per cycle
|
|
system.cpu2.decode.IdleCycles 18645308 # Number of cycles decode is idle
|
|
system.cpu2.decode.BlockedCycles 36894831 # Number of cycles decode is blocked
|
|
system.cpu2.decode.RunCycles 10382963 # Number of cycles decode is running
|
|
system.cpu2.decode.UnblockCycles 1080745 # Number of cycles decode is unblocking
|
|
system.cpu2.decode.SquashCycles 927203 # Number of cycles decode is squashing
|
|
system.cpu2.decode.BranchResolved 1311099 # Number of times decode resolved a branch
|
|
system.cpu2.decode.BranchMispred 109436 # Number of times decode detected a branch misprediction
|
|
system.cpu2.decode.DecodedInsts 59339671 # Number of instructions handled by decode
|
|
system.cpu2.decode.SquashedInsts 354865 # Number of squashed instructions handled by decode
|
|
system.cpu2.rename.SquashCycles 927203 # Number of cycles rename is squashing
|
|
system.cpu2.rename.IdleCycles 19270411 # Number of cycles rename is idle
|
|
system.cpu2.rename.BlockCycles 4356096 # Number of cycles rename is blocking
|
|
system.cpu2.rename.serializeStallCycles 27085706 # count of cycles rename stalled for serializing inst
|
|
system.cpu2.rename.RunCycles 10825258 # Number of cycles rename is running
|
|
system.cpu2.rename.UnblockCycles 5466363 # Number of cycles rename is unblocking
|
|
system.cpu2.rename.RenamedInsts 56871138 # Number of instructions processed by rename
|
|
system.cpu2.rename.ROBFullEvents 2407 # Number of times rename has blocked due to ROB full
|
|
system.cpu2.rename.IQFullEvents 944494 # Number of times rename has blocked due to IQ full
|
|
system.cpu2.rename.LQFullEvents 157128 # Number of times rename has blocked due to LQ full
|
|
system.cpu2.rename.SQFullEvents 3862497 # Number of times rename has blocked due to SQ full
|
|
system.cpu2.rename.RenamedOperands 58808456 # Number of destination operands rename has renamed
|
|
system.cpu2.rename.RenameLookups 261172418 # Number of register rename lookups that rename has made
|
|
system.cpu2.rename.int_rename_lookups 63777133 # Number of integer rename lookups
|
|
system.cpu2.rename.fp_rename_lookups 4183 # Number of floating rename lookups
|
|
system.cpu2.rename.CommittedMaps 48694532 # Number of HB maps that are committed
|
|
system.cpu2.rename.UndoneMaps 10113908 # Number of HB maps that are undone due to squashing
|
|
system.cpu2.rename.serializingInsts 954202 # count of serializing insts renamed
|
|
system.cpu2.rename.tempSerializingInsts 890607 # count of temporary serializing insts renamed
|
|
system.cpu2.rename.skidInsts 6274956 # count of insts added to the skid buffer
|
|
system.cpu2.memDep0.insertedLoads 10279229 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu2.memDep0.insertedStores 7930666 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu2.memDep0.conflictingLoads 1385426 # Number of conflicting loads.
|
|
system.cpu2.memDep0.conflictingStores 1931872 # Number of conflicting stores.
|
|
system.cpu2.iq.iqInstsAdded 54639620 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu2.iq.iqNonSpecInstsAdded 672070 # Number of non-speculative instructions added to the IQ
|
|
system.cpu2.iq.iqInstsIssued 52007794 # Number of instructions issued
|
|
system.cpu2.iq.iqSquashedInstsIssued 68359 # Number of squashed instructions issued
|
|
system.cpu2.iq.iqSquashedInstsExamined 7304876 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu2.iq.iqSquashedOperandsExamined 18433205 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu2.iq.iqSquashedNonSpecRemoved 69298 # Number of squashed non-spec instructions that were removed
|
|
system.cpu2.iq.issued_per_cycle::samples 67931271 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::mean 0.765594 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::stdev 1.467899 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::0 47467453 69.88% 69.88% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::1 6844404 10.08% 79.95% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::2 5089744 7.49% 87.44% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::3 4188713 6.17% 93.61% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::4 1618102 2.38% 95.99% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::5 1074322 1.58% 97.57% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::6 1126267 1.66% 99.23% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::7 361985 0.53% 99.76% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::8 160281 0.24% 100.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::total 67931271 # Number of insts issued each cycle
|
|
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IntAlu 78971 9.77% 9.77% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IntMult 1 0.00% 9.77% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IntDiv 0 0.00% 9.77% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatAdd 0 0.00% 9.77% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatCmp 0 0.00% 9.77% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatCvt 0 0.00% 9.77% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatMult 0 0.00% 9.77% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatDiv 0 0.00% 9.77% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 9.77% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdAdd 0 0.00% 9.77% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 9.77% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdAlu 0 0.00% 9.77% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdCmp 0 0.00% 9.77% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdCvt 0 0.00% 9.77% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdMisc 0 0.00% 9.77% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdMult 0 0.00% 9.77% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 9.77% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdShift 0 0.00% 9.77% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 9.77% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 9.77% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 9.77% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 9.77% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 9.77% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 9.77% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 9.77% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 9.77% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 9.77% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 9.77% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 9.77% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::MemRead 376071 46.54% 56.32% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::MemWrite 352950 43.68% 100.00% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu2.iq.FU_type_0::No_OpClass 108 0.00% 0.00% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IntAlu 34454774 66.25% 66.25% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IntMult 39220 0.08% 66.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdAlu 1 0.00% 66.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatCmp 1 0.00% 66.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatDiv 1 0.00% 66.32% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatMisc 2865 0.01% 66.33% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 66.33% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 3 0.00% 66.33% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.33% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::MemRead 9972711 19.18% 85.51% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::MemWrite 7538110 14.49% 100.00% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::total 52007794 # Type of FU issued
|
|
system.cpu2.iq.rate 0.744794 # Inst issue rate
|
|
system.cpu2.iq.fu_busy_cnt 807993 # FU busy when requested
|
|
system.cpu2.iq.fu_busy_rate 0.015536 # FU busy rate (busy events/executed inst)
|
|
system.cpu2.iq.int_inst_queue_reads 172813810 # Number of integer instruction queue reads
|
|
system.cpu2.iq.int_inst_queue_writes 62649489 # Number of integer instruction queue writes
|
|
system.cpu2.iq.int_inst_queue_wakeup_accesses 50408450 # Number of integer instruction queue wakeup accesses
|
|
system.cpu2.iq.fp_inst_queue_reads 9401 # Number of floating instruction queue reads
|
|
system.cpu2.iq.fp_inst_queue_writes 4928 # Number of floating instruction queue writes
|
|
system.cpu2.iq.fp_inst_queue_wakeup_accesses 4143 # Number of floating instruction queue wakeup accesses
|
|
system.cpu2.iq.int_alu_accesses 52810613 # Number of integer alu accesses
|
|
system.cpu2.iq.fp_alu_accesses 5066 # Number of floating point alu accesses
|
|
system.cpu2.iew.lsq.thread0.forwLoads 267388 # Number of loads that had data forwarded from stores
|
|
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu2.iew.lsq.thread0.squashedLoads 1612297 # Number of loads squashed
|
|
system.cpu2.iew.lsq.thread0.ignoredResponses 1915 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu2.iew.lsq.thread0.memOrderViolation 38614 # Number of memory ordering violations
|
|
system.cpu2.iew.lsq.thread0.squashedStores 794248 # Number of stores squashed
|
|
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu2.iew.lsq.thread0.rescheduledLoads 131416 # Number of loads that were rescheduled
|
|
system.cpu2.iew.lsq.thread0.cacheBlocked 121570 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu2.iew.iewSquashCycles 927203 # Number of cycles IEW is squashing
|
|
system.cpu2.iew.iewBlockCycles 3248790 # Number of cycles IEW is blocking
|
|
system.cpu2.iew.iewUnblockCycles 940039 # Number of cycles IEW is unblocking
|
|
system.cpu2.iew.iewDispatchedInsts 55419045 # Number of instructions dispatched to IQ
|
|
system.cpu2.iew.iewDispSquashedInsts 93730 # Number of squashed instructions skipped by dispatch
|
|
system.cpu2.iew.iewDispLoadInsts 10279229 # Number of dispatched load instructions
|
|
system.cpu2.iew.iewDispStoreInsts 7930666 # Number of dispatched store instructions
|
|
system.cpu2.iew.iewDispNonSpecInsts 359745 # Number of dispatched non-speculative instructions
|
|
system.cpu2.iew.iewIQFullEvents 34744 # Number of times the IQ has become full, causing a stall
|
|
system.cpu2.iew.iewLSQFullEvents 896292 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu2.iew.memOrderViolationEvents 38614 # Number of memory order violations
|
|
system.cpu2.iew.predictedTakenIncorrect 184316 # Number of branches that were predicted taken incorrectly
|
|
system.cpu2.iew.predictedNotTakenIncorrect 163000 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu2.iew.branchMispredicts 347316 # Number of branch mispredicts detected at execute
|
|
system.cpu2.iew.iewExecutedInsts 51571999 # Number of executed instructions
|
|
system.cpu2.iew.iewExecLoadInsts 9796032 # Number of load instructions executed
|
|
system.cpu2.iew.iewExecSquashedInsts 392652 # Number of squashed instructions skipped in execute
|
|
system.cpu2.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu2.iew.exec_nop 107355 # number of nop insts executed
|
|
system.cpu2.iew.exec_refs 17260233 # number of memory reference insts executed
|
|
system.cpu2.iew.exec_branches 9488063 # Number of branches executed
|
|
system.cpu2.iew.exec_stores 7464201 # Number of stores executed
|
|
system.cpu2.iew.exec_rate 0.738553 # Inst execution rate
|
|
system.cpu2.iew.wb_sent 51114762 # cumulative count of insts sent to commit
|
|
system.cpu2.iew.wb_count 50412593 # cumulative count of insts written-back
|
|
system.cpu2.iew.wb_producers 26484469 # num instructions producing a value
|
|
system.cpu2.iew.wb_consumers 46017701 # num instructions consuming a value
|
|
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu2.iew.wb_rate 0.721949 # insts written-back per cycle
|
|
system.cpu2.iew.wb_fanout 0.575528 # average fanout of values written-back
|
|
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu2.commit.commitSquashedInsts 8145270 # The number of squashed insts skipped by commit
|
|
system.cpu2.commit.commitNonSpecStalls 602772 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu2.commit.branchMispredicts 292077 # The number of times a branch was mispredicted
|
|
system.cpu2.commit.committed_per_cycle::samples 66207003 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::mean 0.713906 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::stdev 1.618708 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::0 48127722 72.69% 72.69% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::1 8087932 12.22% 84.91% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::2 3990373 6.03% 90.94% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::3 1725495 2.61% 93.54% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::4 876020 1.32% 94.87% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::5 623327 0.94% 95.81% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::6 1254839 1.90% 97.70% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::7 299711 0.45% 98.15% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::8 1221584 1.85% 100.00% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::total 66207003 # Number of insts commited each cycle
|
|
system.cpu2.commit.committedInsts 38912247 # Number of instructions committed
|
|
system.cpu2.commit.committedOps 47265561 # Number of ops (including micro ops) committed
|
|
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu2.commit.refs 15803350 # Number of memory references committed
|
|
system.cpu2.commit.loads 8666932 # Number of loads committed
|
|
system.cpu2.commit.membars 226535 # Number of memory barriers committed
|
|
system.cpu2.commit.branches 8911403 # Number of branches committed
|
|
system.cpu2.commit.fp_insts 4112 # Number of committed floating point instructions.
|
|
system.cpu2.commit.int_insts 41364475 # Number of committed integer instructions.
|
|
system.cpu2.commit.function_calls 1635441 # Number of function calls committed.
|
|
system.cpu2.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::IntAlu 31421440 66.48% 66.48% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::IntMult 37906 0.08% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::IntDiv 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::FloatMult 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdMult 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdShift 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatMisc 2865 0.01% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 66.56% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::MemRead 8666932 18.34% 84.90% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::MemWrite 7136418 15.10% 100.00% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
|
|
system.cpu2.commit.op_class_0::total 47265561 # Class of committed instruction
|
|
system.cpu2.commit.bw_lim_events 1221584 # number cycles where commit BW limit reached
|
|
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu2.rob.rob_reads 113032454 # The number of ROB reads
|
|
system.cpu2.rob.rob_writes 112549271 # The number of ROB writes
|
|
system.cpu2.timesIdled 280538 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu2.idleCycles 1897151 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu2.quiesceCycles 5250079706 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu2.committedInsts 38848410 # Number of Instructions Simulated
|
|
system.cpu2.committedOps 47201724 # Number of Ops (including micro ops) Simulated
|
|
system.cpu2.cpi 1.797459 # CPI: Cycles Per Instruction
|
|
system.cpu2.cpi_total 1.797459 # CPI: Total CPI of All Threads
|
|
system.cpu2.ipc 0.556341 # IPC: Instructions Per Cycle
|
|
system.cpu2.ipc_total 0.556341 # IPC: Total IPC of All Threads
|
|
system.cpu2.int_regfile_reads 56460891 # number of integer regfile reads
|
|
system.cpu2.int_regfile_writes 31949429 # number of integer regfile writes
|
|
system.cpu2.fp_regfile_reads 15783 # number of floating regfile reads
|
|
system.cpu2.fp_regfile_writes 13692 # number of floating regfile writes
|
|
system.cpu2.cc_regfile_reads 182431289 # number of cc regfile reads
|
|
system.cpu2.cc_regfile_writes 19284860 # number of cc regfile writes
|
|
system.cpu2.misc_regfile_reads 124219174 # number of misc regfile reads
|
|
system.cpu2.misc_regfile_writes 483131 # number of misc regfile writes
|
|
system.iobus.trans_dist::ReadReq 30188 # Transaction distribution
|
|
system.iobus.trans_dist::ReadResp 30188 # Transaction distribution
|
|
system.iobus.trans_dist::WriteReq 59010 # Transaction distribution
|
|
system.iobus.trans_dist::WriteResp 45563 # Transaction distribution
|
|
system.iobus.trans_dist::WriteInvalidateReq 9 # Transaction distribution
|
|
system.iobus.trans_dist::WriteInvalidateResp 13456 # Transaction distribution
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 54174 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 116 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 34 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 20 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 120 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 834 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 32 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 76 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.lan_fake.pio 4 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.usb_fake.pio 10 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ide.pio 7244 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ide-pciconf 210 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet.pio 42268 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.ethernet-pciconf 164 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::system.realview.pciconfig.pio 60 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.bridge.master::total 105462 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::system.iocache.cpu_side 72952 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count_system.realview.ide.dma::total 72952 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_count::total 178414 # Packet count per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart.pio 67891 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.realview_io.pio 232 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer0.pio 68 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.timer1.pio 40 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.kmi0.pio 84 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.kmi1.pio 441 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.rtc.pio 64 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.sp810_fake.pio 152 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.lan_fake.pio 8 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.usb_fake.pio 20 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ide.pio 4753 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ide-pciconf 265 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet.pio 84536 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.ethernet-pciconf 253 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::system.realview.pciconfig.pio 120 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.bridge.master::total 159119 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::system.iocache.cpu_side 2321248 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size_system.realview.ide.dma::total 2321248 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.pkt_size::total 2480367 # Cumulative packet size per connected master and slave (bytes)
|
|
system.iobus.reqLayer0.occupancy 18213000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer1.occupancy 1000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer2.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer3.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer19.occupancy 2000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer23.occupancy 2719000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer24.occupancy 1000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer24.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer25.occupancy 15730000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer25.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer26.occupancy 25000 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer26.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.reqLayer27.occupancy 205242577 # Layer occupancy (ticks)
|
|
system.iobus.reqLayer27.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer0.occupancy 39802000 # Layer occupancy (ticks)
|
|
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.iobus.respLayer3.occupancy 23020273 # Layer occupancy (ticks)
|
|
system.iobus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.iocache.tags.replacements 36442 # number of replacements
|
|
system.iocache.tags.tagsinuse 0.992769 # Cycle average of tags in use
|
|
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
|
|
system.iocache.tags.sampled_refs 36458 # Sample count of references to valid blocks.
|
|
system.iocache.tags.avg_refs 0 # Average number of references to valid blocks.
|
|
system.iocache.tags.warmup_cycle 245004243009 # Cycle when the warmup percentage was hit.
|
|
system.iocache.tags.occ_blocks::realview.ide 0.992769 # Average occupied blocks per requestor
|
|
system.iocache.tags.occ_percent::realview.ide 0.062048 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_percent::total 0.062048 # Average percentage of cache occupancy
|
|
system.iocache.tags.occ_task_id_blocks::1023 16 # Occupied blocks per task id
|
|
system.iocache.tags.age_task_id_blocks_1023::3 16 # Occupied blocks per task id
|
|
system.iocache.tags.occ_task_id_percent::1023 1 # Percentage of cache occupancy per task id
|
|
system.iocache.tags.tag_accesses 328356 # Number of tag accesses
|
|
system.iocache.tags.data_accesses 328356 # Number of data accesses
|
|
system.iocache.WriteInvalidateReq_hits::realview.ide 36224 # number of WriteInvalidateReq hits
|
|
system.iocache.WriteInvalidateReq_hits::total 36224 # number of WriteInvalidateReq hits
|
|
system.iocache.ReadReq_misses::realview.ide 252 # number of ReadReq misses
|
|
system.iocache.ReadReq_misses::total 252 # number of ReadReq misses
|
|
system.iocache.WriteInvalidateReq_misses::realview.ide 9 # number of WriteInvalidateReq misses
|
|
system.iocache.WriteInvalidateReq_misses::total 9 # number of WriteInvalidateReq misses
|
|
system.iocache.demand_misses::realview.ide 252 # number of demand (read+write) misses
|
|
system.iocache.demand_misses::total 252 # number of demand (read+write) misses
|
|
system.iocache.overall_misses::realview.ide 252 # number of overall misses
|
|
system.iocache.overall_misses::total 252 # number of overall misses
|
|
system.iocache.ReadReq_miss_latency::realview.ide 14192930 # number of ReadReq miss cycles
|
|
system.iocache.ReadReq_miss_latency::total 14192930 # number of ReadReq miss cycles
|
|
system.iocache.demand_miss_latency::realview.ide 14192930 # number of demand (read+write) miss cycles
|
|
system.iocache.demand_miss_latency::total 14192930 # number of demand (read+write) miss cycles
|
|
system.iocache.overall_miss_latency::realview.ide 14192930 # number of overall miss cycles
|
|
system.iocache.overall_miss_latency::total 14192930 # number of overall miss cycles
|
|
system.iocache.ReadReq_accesses::realview.ide 252 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.ReadReq_accesses::total 252 # number of ReadReq accesses(hits+misses)
|
|
system.iocache.WriteInvalidateReq_accesses::realview.ide 36233 # number of WriteInvalidateReq accesses(hits+misses)
|
|
system.iocache.WriteInvalidateReq_accesses::total 36233 # number of WriteInvalidateReq accesses(hits+misses)
|
|
system.iocache.demand_accesses::realview.ide 252 # number of demand (read+write) accesses
|
|
system.iocache.demand_accesses::total 252 # number of demand (read+write) accesses
|
|
system.iocache.overall_accesses::realview.ide 252 # number of overall (read+write) accesses
|
|
system.iocache.overall_accesses::total 252 # number of overall (read+write) accesses
|
|
system.iocache.ReadReq_miss_rate::realview.ide 1 # miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
|
|
system.iocache.WriteInvalidateReq_miss_rate::realview.ide 0.000248 # miss rate for WriteInvalidateReq accesses
|
|
system.iocache.WriteInvalidateReq_miss_rate::total 0.000248 # miss rate for WriteInvalidateReq accesses
|
|
system.iocache.demand_miss_rate::realview.ide 1 # miss rate for demand accesses
|
|
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
|
|
system.iocache.overall_miss_rate::realview.ide 1 # miss rate for overall accesses
|
|
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_miss_latency::realview.ide 56321.150794 # average ReadReq miss latency
|
|
system.iocache.ReadReq_avg_miss_latency::total 56321.150794 # average ReadReq miss latency
|
|
system.iocache.demand_avg_miss_latency::realview.ide 56321.150794 # average overall miss latency
|
|
system.iocache.demand_avg_miss_latency::total 56321.150794 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::realview.ide 56321.150794 # average overall miss latency
|
|
system.iocache.overall_avg_miss_latency::total 56321.150794 # average overall miss latency
|
|
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.iocache.fast_writes 36224 # number of fast writes performed
|
|
system.iocache.cache_copies 0 # number of cache copies performed
|
|
system.iocache.ReadReq_mshr_misses::realview.ide 125 # number of ReadReq MSHR misses
|
|
system.iocache.ReadReq_mshr_misses::total 125 # number of ReadReq MSHR misses
|
|
system.iocache.demand_mshr_misses::realview.ide 125 # number of demand (read+write) MSHR misses
|
|
system.iocache.demand_mshr_misses::total 125 # number of demand (read+write) MSHR misses
|
|
system.iocache.overall_mshr_misses::realview.ide 125 # number of overall MSHR misses
|
|
system.iocache.overall_mshr_misses::total 125 # number of overall MSHR misses
|
|
system.iocache.ReadReq_mshr_miss_latency::realview.ide 7692930 # number of ReadReq MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_latency::total 7692930 # number of ReadReq MSHR miss cycles
|
|
system.iocache.WriteInvalidateReq_mshr_miss_latency::realview.ide 1401235920 # number of WriteInvalidateReq MSHR miss cycles
|
|
system.iocache.WriteInvalidateReq_mshr_miss_latency::total 1401235920 # number of WriteInvalidateReq MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::realview.ide 7692930 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.demand_mshr_miss_latency::total 7692930 # number of demand (read+write) MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::realview.ide 7692930 # number of overall MSHR miss cycles
|
|
system.iocache.overall_mshr_miss_latency::total 7692930 # number of overall MSHR miss cycles
|
|
system.iocache.ReadReq_mshr_miss_rate::realview.ide 0.496032 # mshr miss rate for ReadReq accesses
|
|
system.iocache.ReadReq_mshr_miss_rate::total 0.496032 # mshr miss rate for ReadReq accesses
|
|
system.iocache.demand_mshr_miss_rate::realview.ide 0.496032 # mshr miss rate for demand accesses
|
|
system.iocache.demand_mshr_miss_rate::total 0.496032 # mshr miss rate for demand accesses
|
|
system.iocache.overall_mshr_miss_rate::realview.ide 0.496032 # mshr miss rate for overall accesses
|
|
system.iocache.overall_mshr_miss_rate::total 0.496032 # mshr miss rate for overall accesses
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::realview.ide 61543.440000 # average ReadReq mshr miss latency
|
|
system.iocache.ReadReq_avg_mshr_miss_latency::total 61543.440000 # average ReadReq mshr miss latency
|
|
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::realview.ide inf # average WriteInvalidateReq mshr miss latency
|
|
system.iocache.WriteInvalidateReq_avg_mshr_miss_latency::total inf # average WriteInvalidateReq mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::realview.ide 61543.440000 # average overall mshr miss latency
|
|
system.iocache.demand_avg_mshr_miss_latency::total 61543.440000 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::realview.ide 61543.440000 # average overall mshr miss latency
|
|
system.iocache.overall_avg_mshr_miss_latency::total 61543.440000 # average overall mshr miss latency
|
|
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.l2c.tags.replacements 100842 # number of replacements
|
|
system.l2c.tags.tagsinuse 65118.786988 # Cycle average of tags in use
|
|
system.l2c.tags.total_refs 2894514 # Total number of references to valid blocks.
|
|
system.l2c.tags.sampled_refs 166082 # Sample count of references to valid blocks.
|
|
system.l2c.tags.avg_refs 17.428222 # Average number of references to valid blocks.
|
|
system.l2c.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.l2c.tags.occ_blocks::writebacks 49797.172619 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.dtb.walker 1.939323 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000095 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.inst 5291.834831 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu0.data 2854.505423 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.969196 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.inst 1121.422857 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu1.data 949.240769 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu2.dtb.walker 58.966175 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu2.inst 3505.217048 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_blocks::cpu2.data 1537.518652 # Average occupied blocks per requestor
|
|
system.l2c.tags.occ_percent::writebacks 0.759845 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000030 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.inst 0.080747 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu0.data 0.043556 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.inst 0.017112 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu1.data 0.014484 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000900 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu2.inst 0.053485 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::cpu2.data 0.023461 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_percent::total 0.993634 # Average percentage of cache occupancy
|
|
system.l2c.tags.occ_task_id_blocks::1023 47 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_blocks::1024 65193 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1023::4 47 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::1 319 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::2 3121 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::3 8094 # Occupied blocks per task id
|
|
system.l2c.tags.age_task_id_blocks_1024::4 53637 # Occupied blocks per task id
|
|
system.l2c.tags.occ_task_id_percent::1023 0.000717 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.occ_task_id_percent::1024 0.994766 # Percentage of cache occupancy per task id
|
|
system.l2c.tags.tag_accesses 27443398 # Number of tag accesses
|
|
system.l2c.tags.data_accesses 27443398 # Number of data accesses
|
|
system.l2c.ReadReq_hits::cpu0.dtb.walker 4964 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.itb.walker 2546 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.inst 856761 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.data 242820 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.dtb.walker 1454 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.itb.walker 747 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.inst 248185 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.data 77821 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu2.dtb.walker 27355 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu2.itb.walker 6441 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu2.inst 674046 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu2.data 203120 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::total 2346260 # number of ReadReq hits
|
|
system.l2c.Writeback_hits::writebacks 692581 # number of Writeback hits
|
|
system.l2c.Writeback_hits::total 692581 # number of Writeback hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 10 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::cpu2.data 41 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 55 # number of UpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::cpu2.data 12 # number of SCUpgradeReq hits
|
|
system.l2c.SCUpgradeReq_hits::total 12 # number of SCUpgradeReq hits
|
|
system.l2c.ReadExReq_hits::cpu0.data 81743 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu1.data 19467 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::cpu2.data 56360 # number of ReadExReq hits
|
|
system.l2c.ReadExReq_hits::total 157570 # number of ReadExReq hits
|
|
system.l2c.demand_hits::cpu0.dtb.walker 4964 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.itb.walker 2546 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.inst 856761 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 324563 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.dtb.walker 1454 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.itb.walker 747 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 248185 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 97288 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.dtb.walker 27355 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.itb.walker 6441 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.inst 674046 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.data 259480 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 2503830 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.dtb.walker 4964 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.itb.walker 2546 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.inst 856761 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 324563 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.dtb.walker 1454 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.itb.walker 747 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 248185 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 97288 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.dtb.walker 27355 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.itb.walker 6441 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.inst 674046 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.data 259480 # number of overall hits
|
|
system.l2c.overall_hits::total 2503830 # number of overall hits
|
|
system.l2c.ReadReq_misses::cpu0.dtb.walker 4 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.itb.walker 1 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.inst 9639 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.data 6915 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.inst 2046 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.data 2575 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu2.dtb.walker 95 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu2.inst 8081 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu2.data 4586 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::total 33943 # number of ReadReq misses
|
|
system.l2c.UpgradeReq_misses::cpu0.data 1284 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu1.data 369 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu2.data 1064 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 2717 # number of UpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu0.data 2 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::cpu2.data 1 # number of SCUpgradeReq misses
|
|
system.l2c.SCUpgradeReq_misses::total 3 # number of SCUpgradeReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 62393 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 14107 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu2.data 62372 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 138872 # number of ReadExReq misses
|
|
system.l2c.demand_misses::cpu0.dtb.walker 4 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.itb.walker 1 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.inst 9639 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 69308 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 2046 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 16682 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.dtb.walker 95 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.inst 8081 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.data 66958 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 172815 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.dtb.walker 4 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.itb.walker 1 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.inst 9639 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 69308 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 2046 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 16682 # number of overall misses
|
|
system.l2c.overall_misses::cpu2.dtb.walker 95 # number of overall misses
|
|
system.l2c.overall_misses::cpu2.inst 8081 # number of overall misses
|
|
system.l2c.overall_misses::cpu2.data 66958 # number of overall misses
|
|
system.l2c.overall_misses::total 172815 # number of overall misses
|
|
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 74500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.inst 148469000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.data 192657500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 7339250 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu2.inst 615860500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu2.data 368031996 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::total 1332432746 # number of ReadReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu1.data 22999 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::cpu2.data 326986 # number of UpgradeReq miss cycles
|
|
system.l2c.UpgradeReq_miss_latency::total 349985 # number of UpgradeReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu1.data 994427496 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu2.data 4664036226 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::total 5658463722 # number of ReadExReq miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.dtb.walker 74500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.inst 148469000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.data 1187084996 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu2.dtb.walker 7339250 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu2.inst 615860500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu2.data 5032068222 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::total 6990896468 # number of demand (read+write) miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.dtb.walker 74500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.inst 148469000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.data 1187084996 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu2.dtb.walker 7339250 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu2.inst 615860500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu2.data 5032068222 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::total 6990896468 # number of overall miss cycles
|
|
system.l2c.ReadReq_accesses::cpu0.dtb.walker 4968 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.itb.walker 2547 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.inst 866400 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.data 249735 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.dtb.walker 1455 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.itb.walker 747 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.inst 250231 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.data 80396 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu2.dtb.walker 27450 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu2.itb.walker 6441 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu2.inst 682127 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu2.data 207706 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::total 2380203 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::writebacks 692581 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::total 692581 # number of Writeback accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu0.data 1294 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu1.data 373 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu2.data 1105 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 2772 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu0.data 2 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::cpu2.data 13 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.SCUpgradeReq_accesses::total 15 # number of SCUpgradeReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu0.data 144136 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu1.data 33574 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu2.data 118732 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 296442 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.demand_accesses::cpu0.dtb.walker 4968 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.itb.walker 2547 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.inst 866400 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.data 393871 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.dtb.walker 1455 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.itb.walker 747 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.inst 250231 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.data 113970 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu2.dtb.walker 27450 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu2.itb.walker 6441 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu2.inst 682127 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu2.data 326438 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 2676645 # number of demand (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.dtb.walker 4968 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.itb.walker 2547 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.inst 866400 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.data 393871 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.dtb.walker 1455 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.itb.walker 747 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.inst 250231 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.data 113970 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu2.dtb.walker 27450 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu2.itb.walker 6441 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu2.inst 682127 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu2.data 326438 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 2676645 # number of overall (read+write) accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000805 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000393 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.inst 0.011125 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.data 0.027689 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000687 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.inst 0.008176 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.data 0.032029 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.003461 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu2.inst 0.011847 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu2.data 0.022079 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::total 0.014261 # miss rate for ReadReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.992272 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.989276 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu2.data 0.962896 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::total 0.980159 # miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu0.data 1 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::cpu2.data 0.076923 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_miss_rate::total 0.200000 # miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu0.data 0.432876 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu1.data 0.420176 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu2.data 0.525318 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::total 0.468463 # miss rate for ReadExReq accesses
|
|
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000805 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.itb.walker 0.000393 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.inst 0.011125 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.data 0.175966 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000687 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.inst 0.008176 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.data 0.146372 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu2.dtb.walker 0.003461 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu2.inst 0.011847 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu2.data 0.205117 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total 0.064564 # miss rate for demand accesses
|
|
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000805 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.itb.walker 0.000393 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.inst 0.011125 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.data 0.175966 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000687 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.inst 0.008176 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.data 0.146372 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu2.dtb.walker 0.003461 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu2.inst 0.011847 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu2.data 0.205117 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total 0.064564 # miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 74500 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72565.493646 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.data 74818.446602 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 77255.263158 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 76210.926865 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu2.data 80251.198430 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::total 39255.008279 # average ReadReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 62.327913 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 307.317669 # average UpgradeReq miss latency
|
|
system.l2c.UpgradeReq_avg_miss_latency::total 128.813029 # average UpgradeReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 70491.776848 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 74777.724396 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::total 40745.893499 # average ReadExReq miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 74500 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.inst 72565.493646 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.data 71159.632898 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 77255.263158 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu2.inst 76210.926865 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu2.data 75152.606440 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::total 40453.065232 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 74500 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.inst 72565.493646 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.data 71159.632898 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 77255.263158 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu2.inst 76210.926865 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu2.data 75152.606440 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::total 40453.065232 # average overall miss latency
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
system.l2c.writebacks::writebacks 92907 # number of writebacks
|
|
system.l2c.writebacks::total 92907 # number of writebacks
|
|
system.l2c.ReadReq_mshr_hits::cpu2.inst 6 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_hits::cpu2.data 44 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_hits::total 50 # number of ReadReq MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu2.inst 6 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu2.data 44 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::total 50 # number of demand (read+write) MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu2.inst 6 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu2.data 44 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::total 50 # number of overall MSHR hits
|
|
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu1.inst 2046 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu1.data 2575 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 95 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu2.inst 8075 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu2.data 4542 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::total 17334 # number of ReadReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu1.data 369 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu2.data 1064 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::total 1433 # number of UpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::cpu2.data 1 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.SCUpgradeReq_mshr_misses::total 1 # number of SCUpgradeReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu1.data 14107 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu2.data 62372 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::total 76479 # number of ReadExReq MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.inst 2046 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.data 16682 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu2.dtb.walker 95 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu2.inst 8075 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu2.data 66914 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::total 93813 # number of demand (read+write) MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.inst 2046 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.data 16682 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu2.dtb.walker 95 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu2.inst 8075 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu2.data 66914 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::total 93813 # number of overall MSHR misses
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 62500 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 122615000 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 160444500 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 6163250 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 514015500 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu2.data 308547996 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::total 1111848746 # number of ReadReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 3690369 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 10646564 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::total 14336933 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::cpu2.data 10001 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.SCUpgradeReq_mshr_miss_latency::total 10001 # number of SCUpgradeReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 813978004 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 3894067274 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::total 4708045278 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 62500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.inst 122615000 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.data 974422504 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 6163250 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu2.inst 514015500 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu2.data 4202615270 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::total 5819894024 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 62500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.inst 122615000 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.data 974422504 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 6163250 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu2.inst 514015500 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu2.data 4202615270 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::total 5819894024 # number of overall MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 943135000 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 1581115000 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_uncacheable_latency::total 2524250000 # number of ReadReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 723317000 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 1233415500 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.WriteReq_mshr_uncacheable_latency::total 1956732500 # number of WriteReq MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 1666452000 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::cpu2.data 2814530500 # number of overall MSHR uncacheable cycles
|
|
system.l2c.overall_mshr_uncacheable_latency::total 4480982500 # number of overall MSHR uncacheable cycles
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000687 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.008176 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.032029 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.003461 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.011838 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.021867 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::total 0.007283 # mshr miss rate for ReadReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.989276 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.962896 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total 0.516955 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::cpu2.data 0.076923 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.SCUpgradeReq_mshr_miss_rate::total 0.066667 # mshr miss rate for SCUpgradeReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.420176 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.525318 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 0.257990 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000687 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.008176 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.data 0.146372 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.003461 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.011838 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.data 0.204982 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 0.035049 # mshr miss rate for demand accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000687 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.008176 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.data 0.146372 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.003461 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.011838 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.data 0.204982 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 0.035049 # mshr miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59929.130010 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 62308.543689 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 64876.315789 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63655.170279 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 67932.187583 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::total 64142.652936 # average ReadReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10006.169173 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10004.838102 # average UpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10001 # average SCUpgradeReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 57700.290919 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 62432.939043 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 61559.974346 # average ReadExReq mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59929.130010 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 58411.611557 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 64876.315789 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63655.170279 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62806.217981 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::total 62037.180604 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59929.130010 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 58411.611557 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 64876.315789 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63655.170279 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62806.217981 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::total 62037.180604 # average overall mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
|
|
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.membus.trans_dist::ReadReq 74258 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 74257 # Transaction distribution
|
|
system.membus.trans_dist::WriteReq 27571 # Transaction distribution
|
|
system.membus.trans_dist::WriteResp 27571 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 92907 # Transaction distribution
|
|
system.membus.trans_dist::WriteInvalidateReq 36224 # Transaction distribution
|
|
system.membus.trans_dist::WriteInvalidateResp 36224 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeReq 4549 # Transaction distribution
|
|
system.membus.trans_dist::SCUpgradeReq 3 # Transaction distribution
|
|
system.membus.trans_dist::UpgradeResp 4552 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 137040 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 137040 # Transaction distribution
|
|
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 105462 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 1990 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 471782 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.l2c.mem_side::total 579244 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 72827 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count_system.iocache.mem_side::total 72827 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 652071 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.bridge.slave 159119 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.realview.gic.pio 3980 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 16941564 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.l2c.mem_side::total 17104683 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::system.physmem.port 2326464 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.iocache.mem_side::total 2326464 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 19431147 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 125 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 304876 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 304876 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 1 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 304876 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 40704500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer2.occupancy 459000 # Layer occupancy (ticks)
|
|
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.reqLayer5.occupancy 735607750 # Layer occupancy (ticks)
|
|
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer2.occupancy 907107038 # Layer occupancy (ticks)
|
|
system.membus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.membus.respLayer3.occupancy 23918727 # Layer occupancy (ticks)
|
|
system.membus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.realview.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
|
|
system.realview.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
|
|
system.realview.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
|
|
system.realview.ethernet.descDmaWriteBytes 0 # number of descriptor bytes write w/ DMA
|
|
system.realview.ethernet.postedSwi 0 # number of software interrupts posted to CPU
|
|
system.realview.ethernet.coalescedSwi nan # average number of Swi's coalesced into each post
|
|
system.realview.ethernet.totalSwi 0 # total number of Swi written to ISR
|
|
system.realview.ethernet.postedRxIdle 0 # number of rxIdle interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxIdle nan # average number of RxIdle's coalesced into each post
|
|
system.realview.ethernet.totalRxIdle 0 # total number of RxIdle written to ISR
|
|
system.realview.ethernet.postedRxOk 0 # number of RxOk interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxOk nan # average number of RxOk's coalesced into each post
|
|
system.realview.ethernet.totalRxOk 0 # total number of RxOk written to ISR
|
|
system.realview.ethernet.postedRxDesc 0 # number of RxDesc interrupts posted to CPU
|
|
system.realview.ethernet.coalescedRxDesc nan # average number of RxDesc's coalesced into each post
|
|
system.realview.ethernet.totalRxDesc 0 # total number of RxDesc written to ISR
|
|
system.realview.ethernet.postedTxOk 0 # number of TxOk interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxOk nan # average number of TxOk's coalesced into each post
|
|
system.realview.ethernet.totalTxOk 0 # total number of TxOk written to ISR
|
|
system.realview.ethernet.postedTxIdle 0 # number of TxIdle interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxIdle nan # average number of TxIdle's coalesced into each post
|
|
system.realview.ethernet.totalTxIdle 0 # total number of TxIdle written to ISR
|
|
system.realview.ethernet.postedTxDesc 0 # number of TxDesc interrupts posted to CPU
|
|
system.realview.ethernet.coalescedTxDesc nan # average number of TxDesc's coalesced into each post
|
|
system.realview.ethernet.totalTxDesc 0 # total number of TxDesc written to ISR
|
|
system.realview.ethernet.postedRxOrn 0 # number of RxOrn posted to CPU
|
|
system.realview.ethernet.coalescedRxOrn nan # average number of RxOrn's coalesced into each post
|
|
system.realview.ethernet.totalRxOrn 0 # total number of RxOrn written to ISR
|
|
system.realview.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
|
|
system.realview.ethernet.postedInterrupts 0 # number of posts to CPU
|
|
system.realview.ethernet.droppedPackets 0 # number of packets dropped
|
|
system.toL2Bus.trans_dist::ReadReq 2443155 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadResp 2443152 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteReq 27571 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteResp 27571 # Transaction distribution
|
|
system.toL2Bus.trans_dist::Writeback 692581 # Transaction distribution
|
|
system.toL2Bus.trans_dist::WriteInvalidateReq 22776 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeReq 2772 # Transaction distribution
|
|
system.toL2Bus.trans_dist::SCUpgradeReq 15 # Transaction distribution
|
|
system.toL2Bus.trans_dist::UpgradeResp 2787 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExReq 296442 # Transaction distribution
|
|
system.toL2Bus.trans_dist::ReadExResp 296442 # Transaction distribution
|
|
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 3615657 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2484160 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 29265 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 88229 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_count::total 6217311 # Packet count per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 115156920 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 97909811 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 49244 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 155812 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.pkt_size::total 213271787 # Cumulative packet size per connected master and slave (bytes)
|
|
system.toL2Bus.snoops 51771 # Total snoops (count)
|
|
system.toL2Bus.snoop_fanout::samples 3431211 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::mean 5.010633 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::stdev 0.102567 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::3 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::4 0 0.00% 0.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::5 3394727 98.94% 98.94% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::6 36484 1.06% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::min_value 5 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::max_value 6 # Request fanout histogram
|
|
system.toL2Bus.snoop_fanout::total 3431211 # Request fanout histogram
|
|
system.toL2Bus.reqLayer0.occupancy 2367804213 # Layer occupancy (ticks)
|
|
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.toL2Bus.snoopLayer0.occupancy 553500 # Layer occupancy (ticks)
|
|
system.toL2Bus.snoopLayer0.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer0.occupancy 4198919632 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.toL2Bus.respLayer1.occupancy 2015022352 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
|
|
system.toL2Bus.respLayer2.occupancy 11862428 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
|
|
system.toL2Bus.respLayer3.occupancy 39524153 # Layer occupancy (ticks)
|
|
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
|
|
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
|
|
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
|
|
|
|
---------- End Simulation Statistics ----------
|