gem5/src/mem/ruby/system/RubyPort.hh

/*
 * Copyright (c) 2009 Advanced Micro Devices, Inc.
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */

#ifndef RUBYPORT_H
#define RUBYPORT_H

#include "mem/ruby/libruby.hh"
#include <string>
#include <assert.h>

#include "mem/mem_object.hh"
#include "mem/tport.hh"
#include "mem/physical.hh"

#include "params/RubyPort.hh"

using namespace std;

class MessageBuffer;
class AbstractController;

class RubyPort : public MemObject {
public:

    class M5Port : public SimpleTimingPort
    {

        RubyPort *ruby_port;

      public:
        M5Port(const std::string &_name, 
               RubyPort *_port);
        bool sendTiming(PacketPtr pkt);
        void hitCallback(PacketPtr pkt);

      protected:
        virtual bool recvTiming(PacketPtr pkt);
        virtual Tick recvAtomic(PacketPtr pkt);

      private:
        bool isPhysMemAddress(Addr addr);
    };

    friend class M5Port;

    class PioPort : public SimpleTimingPort
    {

        RubyPort *ruby_port;

      public:
        PioPort(const std::string &_name, 
                RubyPort *_port);
        bool sendTiming(PacketPtr pkt);

      protected:
        virtual bool recvTiming(PacketPtr pkt);
        virtual Tick recvAtomic(PacketPtr pkt);
    };

    friend class PioPort;

    struct SenderState : public Packet::SenderState
    {
        M5Port* port;
        Packet::SenderState *saved;

        SenderState(M5Port* _port, 
                    Packet::SenderState *sender_state = NULL)
            : port(_port), saved(sender_state)
        {}
    };

    typedef RubyPortParams Params;
    RubyPort(const Params *p);
    virtual ~RubyPort() {}

    void init();

    Port *getPort(const std::string &if_name, int idx);

    virtual int64_t makeRequest(const RubyRequest & request) = 0;

    void registerHitCallback(void (*hit_callback)(int64_t request_id)) {
        //
        // Can't assign hit_callback twice and by default it is set to the
        // RubyPort's default callback function.
        //
        assert(m_hit_callback == ruby_hit_callback); 
        m_hit_callback = hit_callback;
    }

    //
    // Called by the controller to give the sequencer a pointer.
    // A pointer to the controller is needed for atomic support.
    //
    void setController(AbstractController* _cntrl) { m_controller = _cntrl; }

protected:
  const string m_name;
  void (*m_hit_callback)(int64_t);

  int64_t makeUniqueRequestID() {
    // The request ID is generated by combining the port ID with a request count
    // so that request IDs can be formed concurrently by multiple threads.
    // IDs are formed as follows:
    //
    //
    //   0        PortID                         Request Count
    // +----+---------------+-----------------------------------------------------+
    // | 63 |     62-48     |                         47-0                        |
    // +----+---------------+-----------------------------------------------------+
    //
    //
    //  This limits the system to a maximum of 2^11 == 2048 components
    //  and 2^48 ~= 3x10^14 requests per component

    int64_t id = (static_cast<uint64_t>(m_port_id) << 48) | m_request_cnt;
    m_request_cnt++;
    // assert((m_request_cnt & (1<<48)) == 0);
    return id;
  }

  int m_version;
  AbstractController* m_controller;
  MessageBuffer* m_mandatory_q_ptr;
    PioPort* pio_port;

    //
    // The pending request map is protected so that the Sequencer can access it.
    // This is a temporary fix until the libruby inteface is cleaned
    //
    struct RequestCookie {
        Packet *pkt;
        M5Port *m5Port;
        RequestCookie(Packet *p, M5Port *m5p)
            : pkt(p), m5Port(m5p)
        {}
    };

    typedef std::map<int64_t, RequestCookie*> RequestMap;
    static RequestMap pending_cpu_requests;

private:
  static uint16_t m_num_ports;
  uint16_t m_port_id;
  uint64_t m_request_cnt;

    static void ruby_hit_callback(int64_t req_id);

    M5Port* physMemPort;

    PhysicalMemory* physmem;
};

#endif