2c9ca672df
This patch includes a rather substantial change to the memory controller profiler in order to work with the new configuration system. Most noteably, the mem_cntrl_profiler no longer uses a string map, but instead a vector. Eventually this support should be removed from the main profiler and go into a separate object. Each memory controller should have a pointer to that new mem_cntrl profile object.
24 lines
868 B
Python
24 lines
868 B
Python
from m5.params import *
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from m5.SimObject import SimObject
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class RubyMemoryControl(SimObject):
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type = 'RubyMemoryControl'
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cxx_class = 'MemoryControl'
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version = Param.Int("");
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mem_bus_cycle_multiplier = Param.Int(10, "");
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banks_per_rank = Param.Int(8, "");
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ranks_per_dimm = Param.Int(2, "");
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dimms_per_channel = Param.Int(2, "");
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bank_bit_0 = Param.Int(8, "");
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rank_bit_0 = Param.Int(11, "");
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dimm_bit_0 = Param.Int(12, "");
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bank_queue_size = Param.Int(12, "");
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bank_busy_time = Param.Int(11, "");
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rank_rank_delay = Param.Int(1, "");
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read_write_delay = Param.Int(2, "");
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basic_bus_busy_time = Param.Int(2, "");
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mem_ctl_latency = Param.Int(12, "");
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refresh_period = Param.Int(1560, "");
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tFaw = Param.Int(0, "");
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mem_random_arbitrate = Param.Int(0, "");
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mem_fixed_delay = Param.Int(0, "");
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