68 lines
2.6 KiB
C++
68 lines
2.6 KiB
C++
/*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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* Nathan Binkert
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* Jaidev Patwardhan
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*/
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#ifndef __ARCH_MIPS_VTOPHYS_H__
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#define __ARCH_MIPS_VTOPHYS_H__
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#include "arch/mips/isa_traits.hh"
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#include "arch/mips/utility.hh"
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class ThreadContext;
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class FunctionalPort;
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namespace MipsISA {
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inline Addr PteAddr(Addr a) { return (a & PteMask) << PteShift; }
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// User Virtual
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inline bool IsUSeg(Addr a) { return USegBase <= a && a <= USegEnd; }
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inline bool IsKSeg0(Addr a) { return KSeg0Base <= a && a <= KSeg0End; }
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inline Addr KSeg02Phys(Addr addr) { return addr & KSeg0Mask; }
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inline Addr KSeg12Phys(Addr addr) { return addr & KSeg1Mask; }
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inline bool IsKSeg1(Addr a) { return KSeg1Base <= a && a <= KSeg1End; }
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inline bool IsKSSeg(Addr a) { return KSSegBase <= a && a <= KSSegEnd; }
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inline bool IsKSeg3(Addr a) { return KSeg3Base <= a && a <= KSeg3End; }
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Addr vtophys(Addr vaddr);
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Addr vtophys(ThreadContext *tc, Addr vaddr);
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};
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#endif // __ARCH_MIPS_VTOPHYS_H__
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