86d6b788f6
This patch models a cache as separate tag and data arrays. The patch exposes the banked array as another resource that is checked by SLICC before a transition is allowed to execute. This is similar to how TBE entries and slots in output ports are modeled.
58 lines
2.2 KiB
Python
58 lines
2.2 KiB
Python
# -*- mode:python -*-
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# Copyright (c) 2009 The Hewlett-Packard Development Company
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Nathan Binkert
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Import('*')
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if env['PROTOCOL'] == 'None':
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Return()
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SimObject('Cache.py')
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SimObject('Sequencer.py')
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SimObject('DirectoryMemory.py')
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SimObject('MemoryControl.py')
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SimObject('WireBuffer.py')
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SimObject('RubySystem.py')
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SimObject('RubyMemoryControl.py')
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Source('DMASequencer.cc')
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Source('DirectoryMemory.cc')
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Source('SparseMemory.cc')
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Source('CacheMemory.cc')
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Source('MemoryControl.cc')
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Source('WireBuffer.cc')
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Source('RubyMemoryControl.cc')
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Source('MemoryNode.cc')
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Source('PersistentTable.cc')
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Source('RubyPort.cc')
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Source('RubyPortProxy.cc')
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Source('Sequencer.cc')
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Source('System.cc')
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Source('TimerTable.cc')
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Source('BankedArray.cc')
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