250 lines
7.8 KiB
C++
250 lines
7.8 KiB
C++
/*
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* Copyright (c) 2012 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Korey Sewell
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*
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*/
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#ifndef __CPU_INORDER_RESOURCE_POOL_HH__
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#define __CPU_INORDER_RESOURCE_POOL_HH__
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#include <string>
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#include <vector>
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#include "cpu/inorder/cpu.hh"
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#include "cpu/inorder/inorder_dyn_inst.hh"
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#include "cpu/inorder/pipeline_traits.hh"
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#include "cpu/inorder/resource.hh"
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#include "cpu/inst_seq.hh"
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#include "params/InOrderCPU.hh"
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#include "sim/eventq.hh"
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#include "sim/sim_object.hh"
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class CacheUnit;
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class Event;
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class FetchUnit;
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class ResourceEvent;
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class ResourcePool {
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public:
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typedef InOrderDynInst::DynInstPtr DynInstPtr;
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public:
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// List of Resource Pool Events that extends
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// the list started by the CPU
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// NOTE(1): Resource Pool also uses event list
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// CPUEventType defined in inorder/cpu.hh
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enum ResPoolEventType {
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InstGraduated = InOrderCPU::NumCPUEvents,
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SquashAll,
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UpdateAfterContextSwitch,
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Default
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};
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enum ResPoolEventPri {
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ResPool_Pri = InOrderCPU::InOrderCPU_Pri - 5,
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ResGrad_Pri,
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ResSquash_Pri
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};
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class ResPoolEvent : public Event
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{
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protected:
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/** Resource Pool */
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ResourcePool *resPool;
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public:
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InOrderCPU::CPUEventType eventType;
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DynInstPtr inst;
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InstSeqNum seqNum;
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int stageNum;
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ThreadID tid;
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public:
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/** Constructs a resource event. */
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ResPoolEvent(ResourcePool *_resPool,
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InOrderCPU::CPUEventType e_type,
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DynInstPtr _inst,
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int stage_num,
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InstSeqNum seq_num,
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ThreadID _tid,
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ResPoolEventPri res_pri = ResPool_Pri);
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/** Set Type of Event To Be Scheduled */
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void setEvent(InOrderCPU::CPUEventType e_type,
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DynInstPtr _inst,
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int stage_num,
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InstSeqNum seq_num,
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ThreadID _tid)
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{
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eventType = e_type;
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inst = _inst;
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seqNum = seq_num;
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stageNum = stage_num;
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tid = _tid;
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}
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/** Processes a resource event. */
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void process();
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/** Returns the description of the resource event. */
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const char *description() const;
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/** Schedule Event */
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void scheduleEvent(Cycles delay);
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/** Unschedule This Event */
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void unscheduleEvent();
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};
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public:
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ResourcePool(InOrderCPU *_cpu, ThePipeline::Params *params);
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virtual ~ResourcePool();
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std::string name();
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std::string name(int res_idx) { return resources[res_idx]->name(); }
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void init();
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void print();
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/** Register Statistics in All Resources */
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void regStats();
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/** Returns a specific resource. */
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unsigned getResIdx(const ThePipeline::ResourceId &res_id);
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/** Returns a pointer to a resource */
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Resource* getResource(int res_idx) { return resources[res_idx]; }
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/** Request usage of this resource. Returns -1 if not granted and
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* a positive request tag if granted.
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*/
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ResReqPtr request(int res_idx, DynInstPtr inst);
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/** Squash The Resource */
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void squash(DynInstPtr inst, int res_idx, InstSeqNum done_seq_num,
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ThreadID tid);
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/** Squash All Resources in Pool after Done Seq. Num */
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void squashAll(DynInstPtr inst, int stage_num,
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InstSeqNum done_seq_num, ThreadID tid);
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/** Squash Resources in Pool after a memory stall
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* NOTE: Only use during Switch-On-Miss Thread model
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*/
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void squashDueToMemStall(DynInstPtr inst, int stage_num,
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InstSeqNum done_seq_num, ThreadID tid);
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/** Activate Thread in all resources */
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void activateThread(ThreadID tid);
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/** De-Activate Thread in all resources */
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void deactivateThread(ThreadID tid);
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/** Suspend Thread in all resources */
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void suspendThread(ThreadID tid);
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/** Broadcast Context Switch Update to all resources */
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void updateAfterContextSwitch(DynInstPtr inst, ThreadID tid);
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/** Broadcast graduation to all resources */
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void instGraduated(InstSeqNum seq_num, ThreadID tid);
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/** Broadcast trap to all resources */
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void trap(Fault fault, ThreadID tid, DynInstPtr inst);
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/** The number of instructions available that a resource can
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* can still process.
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*/
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int slotsAvail(int res_idx);
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/** The number of instructions using a resource */
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int slotsInUse(int res_idx);
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/** Schedule resource event, regardless of its current state. */
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void scheduleEvent(InOrderCPU::CPUEventType e_type, DynInstPtr inst = NULL,
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Cycles delay = Cycles(0), int res_idx = 0,
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ThreadID tid = 0);
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/** UnSchedule resource event, regardless of its current state. */
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void unscheduleEvent(int res_idx, DynInstPtr inst);
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/** Tasks to perform when simulation starts */
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virtual void startup() { }
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/** The CPU(s) that this resource interacts with */
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InOrderCPU *cpu;
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DynInstPtr dummyInst[ThePipeline::MaxThreads];
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/**
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* Get a pointer to the (always present) instruction fetch unit.
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*
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* @return the instruction unit
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*/
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FetchUnit *getInstUnit() const { return instUnit; }
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/**
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* Get a pointer to the (always present) data load/store unit.
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*
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* @return the data cache unit
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*/
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CacheUnit *getDataUnit() const { return dataUnit; }
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private:
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/** The instruction fetch unit. */
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FetchUnit *instUnit;
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/** The data load/store unit. */
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CacheUnit *dataUnit;
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std::vector<Resource *> resources;
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/** Resources that need to be updated on an inst. graduation */
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std::vector<int> gradObjects;
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};
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#endif //__CPU_INORDER_RESOURCE_HH__
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