f2b46fdb85
Because there are no longer architecture independent but specialized functions in arch/XXX/faults.hh, code that isn't using the faults from a particular ISA no longer needs to be able to include them through the switching header file arch/faults.hh. By removing that header file (arch/faults.hh), the potential interface between ISA code and non ISA code is narrowed.
85 lines
3.1 KiB
C++
85 lines
3.1 KiB
C++
/*
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* Copyright (c) 2007 MIPS Technologies, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Korey Sewell
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*
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*/
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#ifndef __CPU_INORDER_COMM_HH__
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#define __CPU_INORDER_COMM_HH__
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#include <vector>
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#include "arch/isa_traits.hh"
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#include "base/types.hh"
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#include "cpu/inorder/inorder_dyn_inst.hh"
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#include "cpu/inorder/pipeline_traits.hh"
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#include "cpu/inst_seq.hh"
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/** Struct that defines the information passed from in between stages */
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/** This information mainly goes forward through the pipeline. */
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struct InterStageStruct {
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//@todo: probably should make this a list since the amount of
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// instructions that get passed forward per cycle is
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// really dependent on issue width, CPI, etc.
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std::vector<ThePipeline::DynInstPtr> insts;
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// Add any information that needs to be passed forward to stages
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// below ...
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};
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/** Struct that defines all backwards communication. */
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struct TimeStruct {
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struct StageComm {
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bool squash;
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InstSeqNum doneSeqNum;
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bool uncached;
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ThePipeline::DynInstPtr uncachedLoad;
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StageComm()
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: squash(false), doneSeqNum(0), uncached(false), uncachedLoad(NULL)
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{ }
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};
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StageComm stageInfo[ThePipeline::NumStages][ThePipeline::MaxThreads];
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bool stageBlock[ThePipeline::NumStages][ThePipeline::MaxThreads];
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bool stageUnblock[ThePipeline::NumStages][ThePipeline::MaxThreads];
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TimeStruct()
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{
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for (int i = 0; i < ThePipeline::NumStages; i++) {
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for (int j = 0; j < ThePipeline::MaxThreads; j++) {
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stageBlock[i][j] = false;
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stageUnblock[i][j] = false;
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}
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}
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}
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};
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#endif //__CPU_INORDER_COMM_HH__
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