dbeabedaf0
This patch moves the branch predictor files in the o3 and inorder directories to src/cpu/pred. This allows sharing the branch predictor across different cpu models. This patch was originally posted by Timothy Jones in July 2010 but never made it to the repository. --HG-- rename : src/cpu/o3/bpred_unit.cc => src/cpu/pred/bpred_unit.cc rename : src/cpu/o3/bpred_unit.hh => src/cpu/pred/bpred_unit.hh rename : src/cpu/o3/bpred_unit_impl.hh => src/cpu/pred/bpred_unit_impl.hh rename : src/cpu/o3/sat_counter.hh => src/cpu/pred/sat_counter.hh
63 lines
3.1 KiB
Python
63 lines
3.1 KiB
Python
# Copyright (c) 2007 MIPS Technologies, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Korey Sewell
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from m5.params import *
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from m5.proxy import *
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from BaseCPU import BaseCPU
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from BranchPredictor import BranchPredictor
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class ThreadModel(Enum):
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vals = ['Single', 'SMT', 'SwitchOnCacheMiss']
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class InOrderCPU(BaseCPU):
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type = 'InOrderCPU'
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cxx_header = "cpu/inorder/cpu.hh"
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activity = Param.Unsigned(0, "Initial count")
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threadModel = Param.ThreadModel('SMT', "Multithreading model (SE-MODE only)")
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cachePorts = Param.Unsigned(2, "Cache Ports")
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stageWidth = Param.Unsigned(4, "Stage width")
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fetchBuffSize = Param.Unsigned(4, "Fetch Buffer Size (Number of Cache Blocks Stored)")
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memBlockSize = Param.Unsigned(64, "Memory Block Size")
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stageTracing = Param.Bool(False, "Enable tracing of each stage in CPU")
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multLatency = Param.Cycles(1, "Latency for Multiply Operations")
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multRepeatRate = Param.Cycles(1, "Repeat Rate for Multiply Operations")
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div8Latency = Param.Cycles(1, "Latency for 8-bit Divide Operations")
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div8RepeatRate = Param.Cycles(1, "Repeat Rate for 8-bit Divide Operations")
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div16Latency = Param.Cycles(1, "Latency for 16-bit Divide Operations")
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div16RepeatRate = Param.Cycles(1, "Repeat Rate for 16-bit Divide Operations")
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div24Latency = Param.Cycles(1, "Latency for 24-bit Divide Operations")
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div24RepeatRate = Param.Cycles(1, "Repeat Rate for 24-bit Divide Operations")
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div32Latency = Param.Cycles(1, "Latency for 32-bit Divide Operations")
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div32RepeatRate = Param.Cycles(1, "Repeat Rate for 32-bit Divide Operations")
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branchPred = BranchPredictor(numThreads = Parent.numThreads)
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