1483496803
A recent changeset of mine (http://repo.gem5.org/gem5/rev/4cfe55719da5) inadvertently fixed a bug in the Minor CPU model which caused it to treat software prefetches as regular loads. Prior to this changeset, Minor did an ad-hoc generation of memory commands that left out the PF check; because it now uses the common code that the other CPU models use, it generates prefetches properly. These stat changes reflect the fact that the Minor model now issues SoftPFReqs.
856 lines
98 KiB
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856 lines
98 KiB
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.057738 # Number of seconds simulated
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sim_ticks 57738195500 # Number of ticks simulated
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final_tick 57738195500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 113055 # Simulator instruction rate (inst/s)
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host_op_rate 144580 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 92047581 # Simulator tick rate (ticks/s)
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host_mem_usage 250264 # Number of bytes of host memory used
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host_seconds 627.26 # Real time elapsed on the host
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sim_insts 70915127 # Number of instructions simulated
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sim_ops 90690083 # Number of ops (including micro ops) simulated
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system.voltage_domain.voltage 1 # Voltage in Volts
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system.clk_domain.clock 1000 # Clock period in ticks
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system.physmem.bytes_read::cpu.inst 324352 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu.data 7922944 # Number of bytes read from this memory
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system.physmem.bytes_read::total 8247296 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu.inst 324352 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 324352 # Number of instructions bytes read from this memory
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system.physmem.bytes_written::writebacks 5372992 # Number of bytes written to this memory
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system.physmem.bytes_written::total 5372992 # Number of bytes written to this memory
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system.physmem.num_reads::cpu.inst 5068 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu.data 123796 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 128864 # Number of read requests responded to by this memory
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system.physmem.num_writes::writebacks 83953 # Number of write requests responded to by this memory
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system.physmem.num_writes::total 83953 # Number of write requests responded to by this memory
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system.physmem.bw_read::cpu.inst 5617633 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu.data 137221885 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 142839518 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu.inst 5617633 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 5617633 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_write::writebacks 93057844 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_write::total 93057844 # Write bandwidth from this memory (bytes/s)
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system.physmem.bw_total::writebacks 93057844 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.inst 5617633 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu.data 137221885 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 235897362 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 128864 # Number of read requests accepted
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system.physmem.writeReqs 83953 # Number of write requests accepted
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system.physmem.readBursts 128864 # Number of DRAM read bursts, including those serviced by the write queue
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system.physmem.writeBursts 83953 # Number of DRAM write bursts, including those merged in the write queue
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system.physmem.bytesReadDRAM 8246976 # Total number of bytes read from DRAM
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system.physmem.bytesReadWrQ 320 # Total number of bytes read from write queue
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system.physmem.bytesWritten 5371008 # Total number of bytes written to DRAM
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system.physmem.bytesReadSys 8247296 # Total read bytes from the system interface side
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system.physmem.bytesWrittenSys 5372992 # Total written bytes from the system interface side
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system.physmem.servicedByWrQ 5 # Number of DRAM read bursts serviced by the write queue
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system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
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system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
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system.physmem.perBankRdBursts::0 8158 # Per bank write bursts
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system.physmem.perBankRdBursts::1 8374 # Per bank write bursts
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system.physmem.perBankRdBursts::2 8229 # Per bank write bursts
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system.physmem.perBankRdBursts::3 8170 # Per bank write bursts
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system.physmem.perBankRdBursts::4 8316 # Per bank write bursts
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system.physmem.perBankRdBursts::5 8449 # Per bank write bursts
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system.physmem.perBankRdBursts::6 8089 # Per bank write bursts
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system.physmem.perBankRdBursts::7 7971 # Per bank write bursts
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system.physmem.perBankRdBursts::8 8070 # Per bank write bursts
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system.physmem.perBankRdBursts::9 7642 # Per bank write bursts
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system.physmem.perBankRdBursts::10 7819 # Per bank write bursts
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system.physmem.perBankRdBursts::11 7829 # Per bank write bursts
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system.physmem.perBankRdBursts::12 7880 # Per bank write bursts
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system.physmem.perBankRdBursts::13 7877 # Per bank write bursts
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system.physmem.perBankRdBursts::14 7978 # Per bank write bursts
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system.physmem.perBankRdBursts::15 8008 # Per bank write bursts
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system.physmem.perBankWrBursts::0 5182 # Per bank write bursts
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system.physmem.perBankWrBursts::1 5376 # Per bank write bursts
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system.physmem.perBankWrBursts::2 5285 # Per bank write bursts
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system.physmem.perBankWrBursts::3 5155 # Per bank write bursts
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system.physmem.perBankWrBursts::4 5266 # Per bank write bursts
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system.physmem.perBankWrBursts::5 5517 # Per bank write bursts
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system.physmem.perBankWrBursts::6 5197 # Per bank write bursts
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system.physmem.perBankWrBursts::7 5047 # Per bank write bursts
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system.physmem.perBankWrBursts::8 5033 # Per bank write bursts
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system.physmem.perBankWrBursts::9 5088 # Per bank write bursts
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system.physmem.perBankWrBursts::10 5251 # Per bank write bursts
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system.physmem.perBankWrBursts::11 5143 # Per bank write bursts
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system.physmem.perBankWrBursts::12 5343 # Per bank write bursts
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system.physmem.perBankWrBursts::13 5363 # Per bank write bursts
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system.physmem.perBankWrBursts::14 5451 # Per bank write bursts
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system.physmem.perBankWrBursts::15 5225 # Per bank write bursts
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system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
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system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
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system.physmem.totGap 57738161000 # Total gap between requests
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system.physmem.readPktSize::0 0 # Read request sizes (log2)
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system.physmem.readPktSize::1 0 # Read request sizes (log2)
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system.physmem.readPktSize::2 0 # Read request sizes (log2)
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system.physmem.readPktSize::3 0 # Read request sizes (log2)
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system.physmem.readPktSize::4 0 # Read request sizes (log2)
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system.physmem.readPktSize::5 0 # Read request sizes (log2)
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system.physmem.readPktSize::6 128864 # Read request sizes (log2)
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system.physmem.writePktSize::0 0 # Write request sizes (log2)
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system.physmem.writePktSize::1 0 # Write request sizes (log2)
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system.physmem.writePktSize::2 0 # Write request sizes (log2)
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system.physmem.writePktSize::3 0 # Write request sizes (log2)
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system.physmem.writePktSize::4 0 # Write request sizes (log2)
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system.physmem.writePktSize::5 0 # Write request sizes (log2)
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system.physmem.writePktSize::6 83953 # Write request sizes (log2)
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system.physmem.rdQLenPdf::0 116707 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 12131 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 615 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 635 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 4052 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 5049 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 5142 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 5173 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 5172 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 5174 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 5182 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 5194 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 5187 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 5219 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 5363 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 5263 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 5291 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 5723 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 5319 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::32 5166 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::33 19 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
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system.physmem.bytesPerActivate::samples 38462 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::mean 353.991784 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::gmean 215.320111 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::stdev 335.607526 # Bytes accessed per row activation
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system.physmem.bytesPerActivate::0-127 12100 31.46% 31.46% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::128-255 8198 21.31% 52.77% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::256-383 4148 10.78% 63.56% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::384-511 2890 7.51% 71.07% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::512-639 2484 6.46% 77.53% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::640-767 1581 4.11% 81.64% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::768-895 1319 3.43% 85.07% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::896-1023 1187 3.09% 88.16% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::1024-1151 4555 11.84% 100.00% # Bytes accessed per row activation
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system.physmem.bytesPerActivate::total 38462 # Bytes accessed per row activation
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system.physmem.rdPerTurnAround::samples 5156 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::mean 24.974593 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::stdev 361.421207 # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::0-1023 5153 99.94% 99.94% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::1024-2047 1 0.02% 99.96% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::3072-4095 1 0.02% 99.98% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::25600-26623 1 0.02% 100.00% # Reads before turning the bus around for writes
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system.physmem.rdPerTurnAround::total 5156 # Reads before turning the bus around for writes
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system.physmem.wrPerTurnAround::samples 5156 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::mean 16.276571 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::gmean 16.259351 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::stdev 0.782645 # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::16 4530 87.86% 87.86% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::17 9 0.17% 88.03% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::18 479 9.29% 97.32% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::19 112 2.17% 99.50% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::20 15 0.29% 99.79% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::21 8 0.16% 99.94% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::23 2 0.04% 99.98% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::25 1 0.02% 100.00% # Writes before turning the bus around for reads
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system.physmem.wrPerTurnAround::total 5156 # Writes before turning the bus around for reads
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system.physmem.totQLat 1653247250 # Total ticks spent queuing
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system.physmem.totMemAccLat 4069353500 # Total ticks spent from burst creation until serviced by the DRAM
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system.physmem.totBusLat 644295000 # Total ticks spent in databus transfers
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system.physmem.avgQLat 12829.89 # Average queueing delay per DRAM burst
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system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
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system.physmem.avgMemAccLat 31579.89 # Average memory access latency per DRAM burst
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system.physmem.avgRdBW 142.83 # Average DRAM read bandwidth in MiByte/s
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system.physmem.avgWrBW 93.02 # Average achieved write bandwidth in MiByte/s
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system.physmem.avgRdBWSys 142.84 # Average system read bandwidth in MiByte/s
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system.physmem.avgWrBWSys 93.06 # Average system write bandwidth in MiByte/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
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system.physmem.busUtil 1.84 # Data bus utilization in percentage
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system.physmem.busUtilRead 1.12 # Data bus utilization in percentage for reads
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system.physmem.busUtilWrite 0.73 # Data bus utilization in percentage for writes
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system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
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system.physmem.avgWrQLen 23.36 # Average write queue length when enqueuing
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system.physmem.readRowHits 112168 # Number of row buffer hits during reads
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system.physmem.writeRowHits 62144 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 87.05 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate 74.02 # Row buffer hit rate for writes
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system.physmem.avgGap 271304.27 # Average gap between requests
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system.physmem.pageHitRate 81.91 # Row buffer hit rate, read and write combined
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system.physmem_0.actEnergy 151283160 # Energy for activate commands per rank (pJ)
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system.physmem_0.preEnergy 82545375 # Energy for precharge commands per rank (pJ)
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system.physmem_0.readEnergy 512694000 # Energy for read commands per rank (pJ)
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system.physmem_0.writeEnergy 272322000 # Energy for write commands per rank (pJ)
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system.physmem_0.refreshEnergy 3770972400 # Energy for refresh commands per rank (pJ)
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system.physmem_0.actBackEnergy 11678597190 # Energy for active background per rank (pJ)
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system.physmem_0.preBackEnergy 24396798750 # Energy for precharge background per rank (pJ)
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system.physmem_0.totalEnergy 40865212875 # Total energy per rank (pJ)
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system.physmem_0.averagePower 707.802856 # Core power per rank (mW)
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system.physmem_0.memoryStateTime::IDLE 40459125250 # Time in different power states
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system.physmem_0.memoryStateTime::REF 1927900000 # Time in different power states
|
|
system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT 15348292250 # Time in different power states
|
|
system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.physmem_1.actEnergy 139489560 # Energy for activate commands per rank (pJ)
|
|
system.physmem_1.preEnergy 76110375 # Energy for precharge commands per rank (pJ)
|
|
system.physmem_1.readEnergy 492070800 # Energy for read commands per rank (pJ)
|
|
system.physmem_1.writeEnergy 271492560 # Energy for write commands per rank (pJ)
|
|
system.physmem_1.refreshEnergy 3770972400 # Energy for refresh commands per rank (pJ)
|
|
system.physmem_1.actBackEnergy 11151778680 # Energy for active background per rank (pJ)
|
|
system.physmem_1.preBackEnergy 24858920250 # Energy for precharge background per rank (pJ)
|
|
system.physmem_1.totalEnergy 40760834625 # Total energy per rank (pJ)
|
|
system.physmem_1.averagePower 705.994980 # Core power per rank (mW)
|
|
system.physmem_1.memoryStateTime::IDLE 41228847750 # Time in different power states
|
|
system.physmem_1.memoryStateTime::REF 1927900000 # Time in different power states
|
|
system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT 14578569750 # Time in different power states
|
|
system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
|
|
system.cpu.branchPred.lookups 14838314 # Number of BP lookups
|
|
system.cpu.branchPred.condPredicted 9926302 # Number of conditional branches predicted
|
|
system.cpu.branchPred.condIncorrect 397118 # Number of conditional branches incorrect
|
|
system.cpu.branchPred.BTBLookups 9672403 # Number of BTB lookups
|
|
system.cpu.branchPred.BTBHits 6752101 # Number of BTB hits
|
|
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu.branchPred.BTBHitPct 69.807896 # BTB Hit Percentage
|
|
system.cpu.branchPred.usedRAS 1719649 # Number of times the RAS was used to get a target.
|
|
system.cpu.branchPred.RASInCorrect 3 # Number of incorrect RAS predictions.
|
|
system.cpu_clk_domain.clock 500 # Clock period in ticks
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.dtb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.dtb.inst_hits 0 # ITB inst hits
|
|
system.cpu.dtb.inst_misses 0 # ITB inst misses
|
|
system.cpu.dtb.read_hits 0 # DTB read hits
|
|
system.cpu.dtb.read_misses 0 # DTB read misses
|
|
system.cpu.dtb.write_hits 0 # DTB write hits
|
|
system.cpu.dtb.write_misses 0 # DTB write misses
|
|
system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.dtb.read_accesses 0 # DTB read accesses
|
|
system.cpu.dtb.write_accesses 0 # DTB write accesses
|
|
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.dtb.hits 0 # DTB hits
|
|
system.cpu.dtb.misses 0 # DTB misses
|
|
system.cpu.dtb.accesses 0 # DTB accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
|
|
system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
|
|
system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
|
|
system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits
|
|
system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses
|
|
system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
|
|
system.cpu.itb.walker.walks 0 # Table walker walks requested
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst
|
|
system.cpu.itb.inst_hits 0 # ITB inst hits
|
|
system.cpu.itb.inst_misses 0 # ITB inst misses
|
|
system.cpu.itb.read_hits 0 # DTB read hits
|
|
system.cpu.itb.read_misses 0 # DTB read misses
|
|
system.cpu.itb.write_hits 0 # DTB write hits
|
|
system.cpu.itb.write_misses 0 # DTB write misses
|
|
system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed
|
|
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
|
|
system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
|
|
system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
|
|
system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB
|
|
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
|
|
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
|
|
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
|
|
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
|
|
system.cpu.itb.read_accesses 0 # DTB read accesses
|
|
system.cpu.itb.write_accesses 0 # DTB write accesses
|
|
system.cpu.itb.inst_accesses 0 # ITB inst accesses
|
|
system.cpu.itb.hits 0 # DTB hits
|
|
system.cpu.itb.misses 0 # DTB misses
|
|
system.cpu.itb.accesses 0 # DTB accesses
|
|
system.cpu.workload.num_syscalls 1946 # Number of system calls
|
|
system.cpu.numCycles 115476391 # number of cpu cycles simulated
|
|
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu.committedInsts 70915127 # Number of instructions committed
|
|
system.cpu.committedOps 90690083 # Number of ops (including micro ops) committed
|
|
system.cpu.discardedOps 1150638 # Number of ops (including micro ops) which were discarded before commit
|
|
system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching
|
|
system.cpu.cpi 1.628375 # CPI: cycles per instruction
|
|
system.cpu.ipc 0.614109 # IPC: instructions per cycle
|
|
system.cpu.tickCycles 96920862 # Number of cycles that the object actually ticked
|
|
system.cpu.idleCycles 18555529 # Total number of cycles that the object has spent stopped
|
|
system.cpu.dcache.tags.replacements 156418 # number of replacements
|
|
system.cpu.dcache.tags.tagsinuse 4067.282815 # Cycle average of tags in use
|
|
system.cpu.dcache.tags.total_refs 42627759 # Total number of references to valid blocks.
|
|
system.cpu.dcache.tags.sampled_refs 160514 # Sample count of references to valid blocks.
|
|
system.cpu.dcache.tags.avg_refs 265.570349 # Average number of references to valid blocks.
|
|
system.cpu.dcache.tags.warmup_cycle 830513250 # Cycle when the warmup percentage was hit.
|
|
system.cpu.dcache.tags.occ_blocks::cpu.data 4067.282815 # Average occupied blocks per requestor
|
|
system.cpu.dcache.tags.occ_percent::cpu.data 0.992989 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_percent::total 0.992989 # Average percentage of cache occupancy
|
|
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::0 45 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::1 1135 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.age_task_id_blocks_1024::2 2916 # Occupied blocks per task id
|
|
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
|
|
system.cpu.dcache.tags.tag_accesses 86021754 # Number of tag accesses
|
|
system.cpu.dcache.tags.data_accesses 86021754 # Number of data accesses
|
|
system.cpu.dcache.ReadReq_hits::cpu.data 22869180 # number of ReadReq hits
|
|
system.cpu.dcache.ReadReq_hits::total 22869180 # number of ReadReq hits
|
|
system.cpu.dcache.WriteReq_hits::cpu.data 19642188 # number of WriteReq hits
|
|
system.cpu.dcache.WriteReq_hits::total 19642188 # number of WriteReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::cpu.data 84553 # number of SoftPFReq hits
|
|
system.cpu.dcache.SoftPFReq_hits::total 84553 # number of SoftPFReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::cpu.data 15919 # number of LoadLockedReq hits
|
|
system.cpu.dcache.LoadLockedReq_hits::total 15919 # number of LoadLockedReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::cpu.data 15919 # number of StoreCondReq hits
|
|
system.cpu.dcache.StoreCondReq_hits::total 15919 # number of StoreCondReq hits
|
|
system.cpu.dcache.demand_hits::cpu.data 42511368 # number of demand (read+write) hits
|
|
system.cpu.dcache.demand_hits::total 42511368 # number of demand (read+write) hits
|
|
system.cpu.dcache.overall_hits::cpu.data 42595921 # number of overall hits
|
|
system.cpu.dcache.overall_hits::total 42595921 # number of overall hits
|
|
system.cpu.dcache.ReadReq_misses::cpu.data 51489 # number of ReadReq misses
|
|
system.cpu.dcache.ReadReq_misses::total 51489 # number of ReadReq misses
|
|
system.cpu.dcache.WriteReq_misses::cpu.data 207713 # number of WriteReq misses
|
|
system.cpu.dcache.WriteReq_misses::total 207713 # number of WriteReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::cpu.data 43659 # number of SoftPFReq misses
|
|
system.cpu.dcache.SoftPFReq_misses::total 43659 # number of SoftPFReq misses
|
|
system.cpu.dcache.demand_misses::cpu.data 259202 # number of demand (read+write) misses
|
|
system.cpu.dcache.demand_misses::total 259202 # number of demand (read+write) misses
|
|
system.cpu.dcache.overall_misses::cpu.data 302861 # number of overall misses
|
|
system.cpu.dcache.overall_misses::total 302861 # number of overall misses
|
|
system.cpu.dcache.ReadReq_miss_latency::cpu.data 1477411436 # number of ReadReq miss cycles
|
|
system.cpu.dcache.ReadReq_miss_latency::total 1477411436 # number of ReadReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::cpu.data 16920342250 # number of WriteReq miss cycles
|
|
system.cpu.dcache.WriteReq_miss_latency::total 16920342250 # number of WriteReq miss cycles
|
|
system.cpu.dcache.demand_miss_latency::cpu.data 18397753686 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.demand_miss_latency::total 18397753686 # number of demand (read+write) miss cycles
|
|
system.cpu.dcache.overall_miss_latency::cpu.data 18397753686 # number of overall miss cycles
|
|
system.cpu.dcache.overall_miss_latency::total 18397753686 # number of overall miss cycles
|
|
system.cpu.dcache.ReadReq_accesses::cpu.data 22920669 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.ReadReq_accesses::total 22920669 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::cpu.data 19849901 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.WriteReq_accesses::total 19849901 # number of WriteReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::cpu.data 128212 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.SoftPFReq_accesses::total 128212 # number of SoftPFReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 15919 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.LoadLockedReq_accesses::total 15919 # number of LoadLockedReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::cpu.data 15919 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.StoreCondReq_accesses::total 15919 # number of StoreCondReq accesses(hits+misses)
|
|
system.cpu.dcache.demand_accesses::cpu.data 42770570 # number of demand (read+write) accesses
|
|
system.cpu.dcache.demand_accesses::total 42770570 # number of demand (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::cpu.data 42898782 # number of overall (read+write) accesses
|
|
system.cpu.dcache.overall_accesses::total 42898782 # number of overall (read+write) accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002246 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_miss_rate::total 0.002246 # miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.010464 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_miss_rate::total 0.010464 # miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.340522 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_miss_rate::total 0.340522 # miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.demand_miss_rate::cpu.data 0.006060 # miss rate for demand accesses
|
|
system.cpu.dcache.demand_miss_rate::total 0.006060 # miss rate for demand accesses
|
|
system.cpu.dcache.overall_miss_rate::cpu.data 0.007060 # miss rate for overall accesses
|
|
system.cpu.dcache.overall_miss_rate::total 0.007060 # miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 28693.729457 # average ReadReq miss latency
|
|
system.cpu.dcache.ReadReq_avg_miss_latency::total 28693.729457 # average ReadReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 81460.198688 # average WriteReq miss latency
|
|
system.cpu.dcache.WriteReq_avg_miss_latency::total 81460.198688 # average WriteReq miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::cpu.data 70978.440313 # average overall miss latency
|
|
system.cpu.dcache.demand_avg_miss_latency::total 70978.440313 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::cpu.data 60746.526248 # average overall miss latency
|
|
system.cpu.dcache.overall_avg_miss_latency::total 60746.526248 # average overall miss latency
|
|
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.dcache.writebacks::writebacks 128435 # number of writebacks
|
|
system.cpu.dcache.writebacks::total 128435 # number of writebacks
|
|
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 21989 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_hits::total 21989 # number of ReadReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 100683 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.WriteReq_mshr_hits::total 100683 # number of WriteReq MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::cpu.data 122672 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.demand_mshr_hits::total 122672 # number of demand (read+write) MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::cpu.data 122672 # number of overall MSHR hits
|
|
system.cpu.dcache.overall_mshr_hits::total 122672 # number of overall MSHR hits
|
|
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 29500 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_misses::total 29500 # number of ReadReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 107030 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.WriteReq_mshr_misses::total 107030 # number of WriteReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 23984 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.SoftPFReq_mshr_misses::total 23984 # number of SoftPFReq MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::cpu.data 136530 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.demand_mshr_misses::total 136530 # number of demand (read+write) MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::cpu.data 160514 # number of overall MSHR misses
|
|
system.cpu.dcache.overall_mshr_misses::total 160514 # number of overall MSHR misses
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 558489314 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_latency::total 558489314 # number of ReadReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 8444692500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.WriteReq_mshr_miss_latency::total 8444692500 # number of WriteReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1685620500 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1685620500 # number of SoftPFReq MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 9003181814 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.demand_mshr_miss_latency::total 9003181814 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10688802314 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.overall_mshr_miss_latency::total 10688802314 # number of overall MSHR miss cycles
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.001287 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.001287 # mshr miss rate for ReadReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.005392 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.005392 # mshr miss rate for WriteReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.187065 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.187065 # mshr miss rate for SoftPFReq accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.003192 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.demand_mshr_miss_rate::total 0.003192 # mshr miss rate for demand accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.003742 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.overall_mshr_miss_rate::total 0.003742 # mshr miss rate for overall accesses
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 18931.841153 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 18931.841153 # average ReadReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 78900.238251 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 78900.238251 # average WriteReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 70281.041528 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 70281.041528 # average SoftPFReq mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 65942.882985 # average overall mshr miss latency
|
|
system.cpu.dcache.demand_avg_mshr_miss_latency::total 65942.882985 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 66591.090584 # average overall mshr miss latency
|
|
system.cpu.dcache.overall_avg_mshr_miss_latency::total 66591.090584 # average overall mshr miss latency
|
|
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.icache.tags.replacements 42756 # number of replacements
|
|
system.cpu.icache.tags.tagsinuse 1854.448619 # Cycle average of tags in use
|
|
system.cpu.icache.tags.total_refs 25096729 # Total number of references to valid blocks.
|
|
system.cpu.icache.tags.sampled_refs 44798 # Sample count of references to valid blocks.
|
|
system.cpu.icache.tags.avg_refs 560.219854 # Average number of references to valid blocks.
|
|
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.icache.tags.occ_blocks::cpu.inst 1854.448619 # Average occupied blocks per requestor
|
|
system.cpu.icache.tags.occ_percent::cpu.inst 0.905492 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_percent::total 0.905492 # Average percentage of cache occupancy
|
|
system.cpu.icache.tags.occ_task_id_blocks::1024 2042 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::0 82 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::1 38 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::3 918 # Occupied blocks per task id
|
|
system.cpu.icache.tags.age_task_id_blocks_1024::4 1004 # Occupied blocks per task id
|
|
system.cpu.icache.tags.occ_task_id_percent::1024 0.997070 # Percentage of cache occupancy per task id
|
|
system.cpu.icache.tags.tag_accesses 50327854 # Number of tag accesses
|
|
system.cpu.icache.tags.data_accesses 50327854 # Number of data accesses
|
|
system.cpu.icache.ReadReq_hits::cpu.inst 25096729 # number of ReadReq hits
|
|
system.cpu.icache.ReadReq_hits::total 25096729 # number of ReadReq hits
|
|
system.cpu.icache.demand_hits::cpu.inst 25096729 # number of demand (read+write) hits
|
|
system.cpu.icache.demand_hits::total 25096729 # number of demand (read+write) hits
|
|
system.cpu.icache.overall_hits::cpu.inst 25096729 # number of overall hits
|
|
system.cpu.icache.overall_hits::total 25096729 # number of overall hits
|
|
system.cpu.icache.ReadReq_misses::cpu.inst 44799 # number of ReadReq misses
|
|
system.cpu.icache.ReadReq_misses::total 44799 # number of ReadReq misses
|
|
system.cpu.icache.demand_misses::cpu.inst 44799 # number of demand (read+write) misses
|
|
system.cpu.icache.demand_misses::total 44799 # number of demand (read+write) misses
|
|
system.cpu.icache.overall_misses::cpu.inst 44799 # number of overall misses
|
|
system.cpu.icache.overall_misses::total 44799 # number of overall misses
|
|
system.cpu.icache.ReadReq_miss_latency::cpu.inst 934736739 # number of ReadReq miss cycles
|
|
system.cpu.icache.ReadReq_miss_latency::total 934736739 # number of ReadReq miss cycles
|
|
system.cpu.icache.demand_miss_latency::cpu.inst 934736739 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.demand_miss_latency::total 934736739 # number of demand (read+write) miss cycles
|
|
system.cpu.icache.overall_miss_latency::cpu.inst 934736739 # number of overall miss cycles
|
|
system.cpu.icache.overall_miss_latency::total 934736739 # number of overall miss cycles
|
|
system.cpu.icache.ReadReq_accesses::cpu.inst 25141528 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.ReadReq_accesses::total 25141528 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.icache.demand_accesses::cpu.inst 25141528 # number of demand (read+write) accesses
|
|
system.cpu.icache.demand_accesses::total 25141528 # number of demand (read+write) accesses
|
|
system.cpu.icache.overall_accesses::cpu.inst 25141528 # number of overall (read+write) accesses
|
|
system.cpu.icache.overall_accesses::total 25141528 # number of overall (read+write) accesses
|
|
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001782 # miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_miss_rate::total 0.001782 # miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_miss_rate::cpu.inst 0.001782 # miss rate for demand accesses
|
|
system.cpu.icache.demand_miss_rate::total 0.001782 # miss rate for demand accesses
|
|
system.cpu.icache.overall_miss_rate::cpu.inst 0.001782 # miss rate for overall accesses
|
|
system.cpu.icache.overall_miss_rate::total 0.001782 # miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20865.125092 # average ReadReq miss latency
|
|
system.cpu.icache.ReadReq_avg_miss_latency::total 20865.125092 # average ReadReq miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::cpu.inst 20865.125092 # average overall miss latency
|
|
system.cpu.icache.demand_avg_miss_latency::total 20865.125092 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::cpu.inst 20865.125092 # average overall miss latency
|
|
system.cpu.icache.overall_avg_miss_latency::total 20865.125092 # average overall miss latency
|
|
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 44799 # number of ReadReq MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_misses::total 44799 # number of ReadReq MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::cpu.inst 44799 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.demand_mshr_misses::total 44799 # number of demand (read+write) MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::cpu.inst 44799 # number of overall MSHR misses
|
|
system.cpu.icache.overall_mshr_misses::total 44799 # number of overall MSHR misses
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 865619261 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_latency::total 865619261 # number of ReadReq MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 865619261 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.demand_mshr_miss_latency::total 865619261 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 865619261 # number of overall MSHR miss cycles
|
|
system.cpu.icache.overall_mshr_miss_latency::total 865619261 # number of overall MSHR miss cycles
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.001782 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.001782 # mshr miss rate for ReadReq accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.001782 # mshr miss rate for demand accesses
|
|
system.cpu.icache.demand_mshr_miss_rate::total 0.001782 # mshr miss rate for demand accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.001782 # mshr miss rate for overall accesses
|
|
system.cpu.icache.overall_mshr_miss_rate::total 0.001782 # mshr miss rate for overall accesses
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19322.289806 # average ReadReq mshr miss latency
|
|
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19322.289806 # average ReadReq mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19322.289806 # average overall mshr miss latency
|
|
system.cpu.icache.demand_avg_mshr_miss_latency::total 19322.289806 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19322.289806 # average overall mshr miss latency
|
|
system.cpu.icache.overall_avg_mshr_miss_latency::total 19322.289806 # average overall mshr miss latency
|
|
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.l2cache.tags.replacements 95726 # number of replacements
|
|
system.cpu.l2cache.tags.tagsinuse 29866.578850 # Cycle average of tags in use
|
|
system.cpu.l2cache.tags.total_refs 99768 # Total number of references to valid blocks.
|
|
system.cpu.l2cache.tags.sampled_refs 126844 # Sample count of references to valid blocks.
|
|
system.cpu.l2cache.tags.avg_refs 0.786541 # Average number of references to valid blocks.
|
|
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu.l2cache.tags.occ_blocks::writebacks 26746.709888 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1560.467773 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_blocks::cpu.data 1559.401189 # Average occupied blocks per requestor
|
|
system.cpu.l2cache.tags.occ_percent::writebacks 0.816245 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.047622 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::cpu.data 0.047589 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_percent::total 0.911456 # Average percentage of cache occupancy
|
|
system.cpu.l2cache.tags.occ_task_id_blocks::1024 31118 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 120 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1811 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 12771 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 15838 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 578 # Occupied blocks per task id
|
|
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.949646 # Percentage of cache occupancy per task id
|
|
system.cpu.l2cache.tags.tag_accesses 2903858 # Number of tag accesses
|
|
system.cpu.l2cache.tags.data_accesses 2903858 # Number of data accesses
|
|
system.cpu.l2cache.ReadReq_hits::cpu.inst 39720 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::cpu.data 31906 # number of ReadReq hits
|
|
system.cpu.l2cache.ReadReq_hits::total 71626 # number of ReadReq hits
|
|
system.cpu.l2cache.Writeback_hits::writebacks 128435 # number of Writeback hits
|
|
system.cpu.l2cache.Writeback_hits::total 128435 # number of Writeback hits
|
|
system.cpu.l2cache.ReadExReq_hits::cpu.data 4748 # number of ReadExReq hits
|
|
system.cpu.l2cache.ReadExReq_hits::total 4748 # number of ReadExReq hits
|
|
system.cpu.l2cache.demand_hits::cpu.inst 39720 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::cpu.data 36654 # number of demand (read+write) hits
|
|
system.cpu.l2cache.demand_hits::total 76374 # number of demand (read+write) hits
|
|
system.cpu.l2cache.overall_hits::cpu.inst 39720 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::cpu.data 36654 # number of overall hits
|
|
system.cpu.l2cache.overall_hits::total 76374 # number of overall hits
|
|
system.cpu.l2cache.ReadReq_misses::cpu.inst 5079 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::cpu.data 21578 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadReq_misses::total 26657 # number of ReadReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::cpu.data 102282 # number of ReadExReq misses
|
|
system.cpu.l2cache.ReadExReq_misses::total 102282 # number of ReadExReq misses
|
|
system.cpu.l2cache.demand_misses::cpu.inst 5079 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::cpu.data 123860 # number of demand (read+write) misses
|
|
system.cpu.l2cache.demand_misses::total 128939 # number of demand (read+write) misses
|
|
system.cpu.l2cache.overall_misses::cpu.inst 5079 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::cpu.data 123860 # number of overall misses
|
|
system.cpu.l2cache.overall_misses::total 128939 # number of overall misses
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 403732250 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 1855266750 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadReq_miss_latency::total 2258999000 # number of ReadReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8287771000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.ReadExReq_miss_latency::total 8287771000 # number of ReadExReq miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.inst 403732250 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::cpu.data 10143037750 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.demand_miss_latency::total 10546770000 # number of demand (read+write) miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.inst 403732250 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::cpu.data 10143037750 # number of overall miss cycles
|
|
system.cpu.l2cache.overall_miss_latency::total 10546770000 # number of overall miss cycles
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.inst 44799 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::cpu.data 53484 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadReq_accesses::total 98283 # number of ReadReq accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::writebacks 128435 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.Writeback_accesses::total 128435 # number of Writeback accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::cpu.data 107030 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.ReadExReq_accesses::total 107030 # number of ReadExReq accesses(hits+misses)
|
|
system.cpu.l2cache.demand_accesses::cpu.inst 44799 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::cpu.data 160514 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.demand_accesses::total 205313 # number of demand (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.inst 44799 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::cpu.data 160514 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.overall_accesses::total 205313 # number of overall (read+write) accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.113373 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.403448 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_miss_rate::total 0.271227 # miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.955639 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_miss_rate::total 0.955639 # miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.113373 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::cpu.data 0.771646 # miss rate for demand accesses
|
|
system.cpu.l2cache.demand_miss_rate::total 0.628012 # miss rate for demand accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.113373 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::cpu.data 0.771646 # miss rate for overall accesses
|
|
system.cpu.l2cache.overall_miss_rate::total 0.628012 # miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 79490.500098 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85979.550932 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadReq_avg_miss_latency::total 84743.181903 # average ReadReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81028.636515 # average ReadExReq miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81028.636515 # average ReadExReq miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 79490.500098 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81891.149281 # average overall miss latency
|
|
system.cpu.l2cache.demand_avg_miss_latency::total 81796.585983 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 79490.500098 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81891.149281 # average overall miss latency
|
|
system.cpu.l2cache.overall_avg_miss_latency::total 81796.585983 # average overall miss latency
|
|
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
|
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
|
system.cpu.l2cache.writebacks::writebacks 83953 # number of writebacks
|
|
system.cpu.l2cache.writebacks::total 83953 # number of writebacks
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 10 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 64 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.inst 10 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::cpu.data 64 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.demand_mshr_hits::total 74 # number of demand (read+write) MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.inst 10 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::cpu.data 64 # number of overall MSHR hits
|
|
system.cpu.l2cache.overall_mshr_hits::total 74 # number of overall MSHR hits
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 5069 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 21514 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_misses::total 26583 # number of ReadReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 102282 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.ReadExReq_mshr_misses::total 102282 # number of ReadExReq MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.inst 5069 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::cpu.data 123796 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.demand_mshr_misses::total 128865 # number of demand (read+write) MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.inst 5069 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::cpu.data 123796 # number of overall MSHR misses
|
|
system.cpu.l2cache.overall_mshr_misses::total 128865 # number of overall MSHR misses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 339459750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1581559750 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1921019500 # number of ReadReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 7009102000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 7009102000 # number of ReadExReq MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 339459750 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 8590661750 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.demand_mshr_miss_latency::total 8930121500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 339459750 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 8590661750 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.overall_mshr_miss_latency::total 8930121500 # number of overall MSHR miss cycles
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.113150 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.402251 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.270474 # mshr miss rate for ReadReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.955639 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.955639 # mshr miss rate for ReadExReq accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.113150 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.771247 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.demand_mshr_miss_rate::total 0.627651 # mshr miss rate for demand accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.113150 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.771247 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.overall_mshr_miss_rate::total 0.627651 # mshr miss rate for overall accesses
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66967.794437 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 73513.049642 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 72264.962570 # average ReadReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68527.228642 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68527.228642 # average ReadExReq mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66967.794437 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69393.694061 # average overall mshr miss latency
|
|
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69298.269507 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66967.794437 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69393.694061 # average overall mshr miss latency
|
|
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69298.269507 # average overall mshr miss latency
|
|
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu.toL2Bus.trans_dist::ReadReq 98283 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadResp 98282 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::Writeback 128435 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExReq 107030 # Transaction distribution
|
|
system.cpu.toL2Bus.trans_dist::ReadExResp 107030 # Transaction distribution
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 89597 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 449463 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_count::total 539060 # Packet count per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 2867072 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 18492736 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.pkt_size::total 21359808 # Cumulative packet size per connected master and slave (bytes)
|
|
system.cpu.toL2Bus.snoops 0 # Total snoops (count)
|
|
system.cpu.toL2Bus.snoop_fanout::samples 333748 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::mean 3 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 0.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::3 333748 100.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::4 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::min_value 3 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::max_value 3 # Request fanout histogram
|
|
system.cpu.toL2Bus.snoop_fanout::total 333748 # Request fanout histogram
|
|
system.cpu.toL2Bus.reqLayer0.occupancy 295309000 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.reqLayer0.utilization 0.5 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer0.occupancy 68157239 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
|
|
system.cpu.toL2Bus.respLayer1.occupancy 268247686 # Layer occupancy (ticks)
|
|
system.cpu.toL2Bus.respLayer1.utilization 0.5 # Layer utilization (%)
|
|
system.membus.trans_dist::ReadReq 26582 # Transaction distribution
|
|
system.membus.trans_dist::ReadResp 26582 # Transaction distribution
|
|
system.membus.trans_dist::Writeback 83953 # Transaction distribution
|
|
system.membus.trans_dist::ReadExReq 102282 # Transaction distribution
|
|
system.membus.trans_dist::ReadExResp 102282 # Transaction distribution
|
|
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 341681 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_count::total 341681 # Packet count per connected master and slave (bytes)
|
|
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 13620288 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.pkt_size::total 13620288 # Cumulative packet size per connected master and slave (bytes)
|
|
system.membus.snoops 0 # Total snoops (count)
|
|
system.membus.snoop_fanout::samples 212817 # Request fanout histogram
|
|
system.membus.snoop_fanout::mean 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::stdev 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::0 212817 100.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
|
system.membus.snoop_fanout::min_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::max_value 0 # Request fanout histogram
|
|
system.membus.snoop_fanout::total 212817 # Request fanout histogram
|
|
system.membus.reqLayer0.occupancy 578407500 # Layer occupancy (ticks)
|
|
system.membus.reqLayer0.utilization 1.0 # Layer utilization (%)
|
|
system.membus.respLayer1.occupancy 680129500 # Layer occupancy (ticks)
|
|
system.membus.respLayer1.utilization 1.2 # Layer utilization (%)
|
|
|
|
---------- End Simulation Statistics ----------
|