42535f5f53
formatting/indentation for case statements
src/arch/sparc/ua2005.cc:
formatting/indentation for case statements
--HG--
extra : convert_revision : aeb7d0274d8d22db3fa56aabbb8ab8f5371a32ff
233 lines
8.1 KiB
C++
233 lines
8.1 KiB
C++
/*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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*/
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#include "arch/sparc/miscregfile.hh"
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#include "base/bitfield.hh"
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#include "base/trace.hh"
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#include "cpu/base.hh"
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#include "cpu/thread_context.hh"
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using namespace SparcISA;
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void
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MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
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ThreadContext *tc)
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{
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int64_t time;
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switch (miscReg) {
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/* Full system only ASRs */
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case MISCREG_SOFTINT:
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// Check if we are going to interrupt because of something
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setReg(miscReg, val);
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tc->getCpuPtr()->checkInterrupts = true;
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if (val != 0x10000 && val != 0)
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warn("Writing to softint not really supported, writing: %#x\n", val);
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break;
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case MISCREG_SOFTINT_CLR:
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return setRegWithEffect(MISCREG_SOFTINT, ~val & softint, tc);
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case MISCREG_SOFTINT_SET:
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return setRegWithEffect(MISCREG_SOFTINT, val | softint, tc);
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case MISCREG_TICK_CMPR:
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if (tickCompare == NULL)
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tickCompare = new TickCompareEvent(this, tc);
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setReg(miscReg, val);
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if ((tick_cmpr & mask(63)) && tickCompare->scheduled())
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tickCompare->deschedule();
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time = (tick_cmpr & mask(63)) - (tick & mask(63));
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if (!(tick_cmpr & ~mask(63)) && time > 0)
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tickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
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panic("writing to TICK compare register %#X\n", val);
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break;
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case MISCREG_STICK_CMPR:
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if (sTickCompare == NULL)
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sTickCompare = new STickCompareEvent(this, tc);
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setReg(miscReg, val);
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if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled())
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sTickCompare->deschedule();
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time = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
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tc->getCpuPtr()->instCount();
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if (!(stick_cmpr & ~mask(63)) && time > 0)
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sTickCompare->schedule(time * tc->getCpuPtr()->cycles(1) + curTick);
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DPRINTF(Timer, "writing to sTICK compare register value %#X\n", val);
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break;
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case MISCREG_PSTATE:
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if (val & ie && !(pstate & ie)) {
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tc->getCpuPtr()->checkInterrupts = true;
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}
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setReg(miscReg, val);
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case MISCREG_PIL:
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if (val < pil) {
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tc->getCpuPtr()->checkInterrupts = true;
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}
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setReg(miscReg, val);
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break;
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case MISCREG_HVER:
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panic("Shouldn't be writing HVER\n");
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case MISCREG_HTBA:
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// clear lower 7 bits on writes.
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setReg(miscReg, val & ULL(~0x7FFF));
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break;
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case MISCREG_QUEUE_CPU_MONDO_HEAD:
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case MISCREG_QUEUE_CPU_MONDO_TAIL:
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case MISCREG_QUEUE_DEV_MONDO_HEAD:
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case MISCREG_QUEUE_DEV_MONDO_TAIL:
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case MISCREG_QUEUE_RES_ERROR_HEAD:
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case MISCREG_QUEUE_RES_ERROR_TAIL:
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case MISCREG_QUEUE_NRES_ERROR_HEAD:
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case MISCREG_QUEUE_NRES_ERROR_TAIL:
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setReg(miscReg, val);
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tc->getCpuPtr()->checkInterrupts = true;
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break;
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case MISCREG_HSTICK_CMPR:
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if (hSTickCompare == NULL)
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hSTickCompare = new HSTickCompareEvent(this, tc);
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setReg(miscReg, val);
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if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled())
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hSTickCompare->deschedule();
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time = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
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tc->getCpuPtr()->instCount();
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if (!(hstick_cmpr & ~mask(63)) && time > 0)
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hSTickCompare->schedule(curTick + time * tc->getCpuPtr()->cycles(1));
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DPRINTF(Timer, "writing to hsTICK compare register value %#X\n", val);
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break;
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case MISCREG_HPSTATE:
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// T1000 spec says impl. dependent val must always be 1
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setReg(miscReg, val | id);
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break;
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case MISCREG_HTSTATE:
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case MISCREG_STRAND_STS_REG:
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setReg(miscReg, val);
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break;
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default:
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panic("Invalid write to FS misc register %s\n", getMiscRegName(miscReg));
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}
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}
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MiscReg
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MiscRegFile::readFSRegWithEffect(int miscReg, ThreadContext * tc)
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{
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switch (miscReg) {
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/* Privileged registers. */
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case MISCREG_QUEUE_CPU_MONDO_HEAD:
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case MISCREG_QUEUE_CPU_MONDO_TAIL:
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case MISCREG_QUEUE_DEV_MONDO_HEAD:
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case MISCREG_QUEUE_DEV_MONDO_TAIL:
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case MISCREG_QUEUE_RES_ERROR_HEAD:
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case MISCREG_QUEUE_RES_ERROR_TAIL:
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case MISCREG_QUEUE_NRES_ERROR_HEAD:
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case MISCREG_QUEUE_NRES_ERROR_TAIL:
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case MISCREG_SOFTINT:
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case MISCREG_TICK_CMPR:
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case MISCREG_STICK_CMPR:
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case MISCREG_PIL:
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case MISCREG_HPSTATE:
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case MISCREG_HINTP:
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case MISCREG_HTSTATE:
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case MISCREG_STRAND_STS_REG:
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case MISCREG_HSTICK_CMPR:
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return readReg(miscReg) ;
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case MISCREG_HTBA:
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return readReg(miscReg) & ULL(~0x7FFF);
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case MISCREG_HVER:
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return NWindows | MaxTL << 8 | MaxGL << 16;
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default:
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panic("Invalid read to FS misc register\n");
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}
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}
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/*
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In Niagra STICK==TICK so this isn't needed
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case MISCREG_STICK:
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SparcSystem *sys;
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sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
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assert(sys != NULL);
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return curTick/Clock::Int::ns - sys->sysTick | (stick & ~(mask(63)));
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*/
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void
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MiscRegFile::processTickCompare(ThreadContext *tc)
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{
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panic("tick compare not implemented\n");
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}
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void
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MiscRegFile::processSTickCompare(ThreadContext *tc)
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{
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// since our microcode instructions take two cycles we need to check if
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// we're actually at the correct cycle or we need to wait a little while
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// more
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int ticks;
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ticks = ((int64_t)(stick_cmpr & mask(63)) - (int64_t)stick) -
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tc->getCpuPtr()->instCount();
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assert(ticks >= 0 && "stick compare missed interrupt cycle");
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if (ticks == 0) {
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DPRINTF(Timer, "STick compare cycle reached at %#x\n",
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(stick_cmpr & mask(63)));
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tc->getCpuPtr()->checkInterrupts = true;
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softint |= ULL(1) << 16;
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} else
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sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick);
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}
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void
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MiscRegFile::processHSTickCompare(ThreadContext *tc)
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{
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// since our microcode instructions take two cycles we need to check if
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// we're actually at the correct cycle or we need to wait a little while
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// more
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int ticks;
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ticks = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -
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tc->getCpuPtr()->instCount();
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assert(ticks >= 0 && "hstick compare missed interrupt cycle");
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if (ticks == 0) {
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DPRINTF(Timer, "HSTick compare cycle reached at %#x\n",
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(stick_cmpr & mask(63)));
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tc->getCpuPtr()->checkInterrupts = true;
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// Need to do something to cause interrupt to happen here !!! @todo
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} else
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sTickCompare->schedule(ticks * tc->getCpuPtr()->cycles(1) + curTick);
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}
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