c96160cef5
Right now this introduces a minor memory leak as old physPorts and virtPorts are not deleted when new ones are created. A flyspray task has been created for this issue. It can not be resolved until we determine how the bus will handle giving out ID's to functional ports that may be deleted. src/cpu/o3/cpu.cc: src/cpu/simple/atomic.cc: src/cpu/simple/timing.cc: Change the setup of the physPort and virtPort to instead happen every time the CPU has a context activated. This is a little high overhead, but keeps it working correctly when the CPU does not have a physical memory attached to it until it switches in (like the case of switch CPUs). src/cpu/o3/thread_context.hh: Change function from being called at init() to just being called whenever the memory ports need to be connected. src/cpu/o3/thread_context_impl.hh: Update this to not delete the port if it's the same as the virtPort. src/cpu/thread_context.hh: Change function from being called at init() to whenever the memory ports need to be connected. src/cpu/thread_state.cc: Instead of initializing the ports, simply connect them, deleting any old ports that might exist. This allows these functions to be called multiple times. src/cpu/thread_state.hh: Ports are no longer initialized, but rather connected at context activation time. --HG-- extra : convert_revision : e399ce5dfbd6ad658c953a7c9c7b69b89a70219e
258 lines
7.3 KiB
C++
258 lines
7.3 KiB
C++
/*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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*/
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#ifndef __CPU_THREAD_STATE_HH__
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#define __CPU_THREAD_STATE_HH__
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#include "arch/types.hh"
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#include "cpu/profile.hh"
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#include "cpu/thread_context.hh"
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#if !FULL_SYSTEM
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#include "mem/mem_object.hh"
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#include "sim/process.hh"
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#endif
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#if FULL_SYSTEM
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class EndQuiesceEvent;
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class FunctionProfile;
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class ProfileNode;
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namespace TheISA {
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namespace Kernel {
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class Statistics;
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};
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};
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#endif
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class BaseCPU;
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class Checkpoint;
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class Port;
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class TranslatingPort;
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/**
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* Struct for holding general thread state that is needed across CPU
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* models. This includes things such as pointers to the process,
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* memory, quiesce events, and certain stats. This can be expanded
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* to hold more thread-specific stats within it.
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*/
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struct ThreadState {
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typedef ThreadContext::Status Status;
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#if FULL_SYSTEM
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ThreadState(BaseCPU *cpu, int _cpuId, int _tid);
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#else
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ThreadState(BaseCPU *cpu, int _cpuId, int _tid, Process *_process,
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short _asid);
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#endif
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~ThreadState();
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void serialize(std::ostream &os);
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void unserialize(Checkpoint *cp, const std::string §ion);
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void setCpuId(int id) { cpuId = id; }
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int readCpuId() { return cpuId; }
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void setTid(int id) { tid = id; }
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int readTid() { return tid; }
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Tick readLastActivate() { return lastActivate; }
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Tick readLastSuspend() { return lastSuspend; }
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#if FULL_SYSTEM
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void connectMemPorts();
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void connectPhysPort();
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void connectVirtPort();
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void dumpFuncProfile();
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EndQuiesceEvent *getQuiesceEvent() { return quiesceEvent; }
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void profileClear();
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void profileSample();
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TheISA::Kernel::Statistics *getKernelStats() { return kernelStats; }
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FunctionalPort *getPhysPort() { return physPort; }
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void setPhysPort(FunctionalPort *port) { physPort = port; }
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VirtualPort *getVirtPort(ThreadContext *tc = NULL) { return virtPort; }
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void setVirtPort(VirtualPort *port) { virtPort = port; }
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#else
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Process *getProcessPtr() { return process; }
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TranslatingPort *getMemPort();
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void setMemPort(TranslatingPort *_port) { port = _port; }
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int getInstAsid() { return asid; }
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int getDataAsid() { return asid; }
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#endif
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/** Sets the current instruction being committed. */
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void setInst(TheISA::MachInst _inst) { inst = _inst; }
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/** Returns the current instruction being committed. */
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TheISA::MachInst getInst() { return inst; }
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/** Reads the number of instructions functionally executed and
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* committed.
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*/
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Counter readFuncExeInst() { return funcExeInst; }
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/** Sets the total number of instructions functionally executed
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* and committed.
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*/
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void setFuncExeInst(Counter new_val) { funcExeInst = new_val; }
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/** Returns the status of this thread. */
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Status status() const { return _status; }
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/** Sets the status of this thread. */
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void setStatus(Status new_status) { _status = new_status; }
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public:
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/** Connects port to the functional port of the memory object
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* below the CPU. */
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void connectToMemFunc(Port *port);
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/** Number of instructions committed. */
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Counter numInst;
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/** Stat for number instructions committed. */
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Stats::Scalar<> numInsts;
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/** Stat for number of memory references. */
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Stats::Scalar<> numMemRefs;
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/** Number of simulated loads, used for tracking events based on
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* the number of loads committed.
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*/
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Counter numLoad;
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/** The number of simulated loads committed prior to this run. */
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Counter startNumLoad;
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protected:
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ThreadContext::Status _status;
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// Pointer to the base CPU.
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BaseCPU *baseCpu;
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// ID of this context w.r.t. the System or Process object to which
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// it belongs. For full-system mode, this is the system CPU ID.
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int cpuId;
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// Index of hardware thread context on the CPU that this represents.
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int tid;
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public:
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/** Last time activate was called on this thread. */
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Tick lastActivate;
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/** Last time suspend was called on this thread. */
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Tick lastSuspend;
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#if FULL_SYSTEM
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public:
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FunctionProfile *profile;
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ProfileNode *profileNode;
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Addr profilePC;
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EndQuiesceEvent *quiesceEvent;
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TheISA::Kernel::Statistics *kernelStats;
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protected:
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/** A functional port outgoing only for functional accesses to physical
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* addresses.*/
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FunctionalPort *physPort;
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/** A functional port, outgoing only, for functional accesse to virtual
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* addresses. That doen't require execution context information */
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VirtualPort *virtPort;
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#else
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TranslatingPort *port;
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Process *process;
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// Address space ID. Note that this is used for TIMING cache
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// simulation only; all functional memory accesses should use
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// one of the FunctionalMemory pointers above.
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short asid;
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#endif
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/** Current instruction the thread is committing. Only set and
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* used for DTB faults currently.
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*/
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TheISA::MachInst inst;
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/** The current microcode pc for the currently executing macro
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* operation.
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*/
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MicroPC microPC;
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/** The next microcode pc for the currently executing macro
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* operation.
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*/
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MicroPC nextMicroPC;
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public:
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/**
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* Temporary storage to pass the source address from copy_load to
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* copy_store.
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* @todo Remove this temporary when we have a better way to do it.
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*/
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Addr copySrcAddr;
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/**
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* Temp storage for the physical source address of a copy.
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* @todo Remove this temporary when we have a better way to do it.
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*/
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Addr copySrcPhysAddr;
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/*
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* number of executed instructions, for matching with syscall trace
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* points in EIO files.
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*/
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Counter funcExeInst;
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//
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// Count failed store conditionals so we can warn of apparent
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// application deadlock situations.
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unsigned storeCondFailures;
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};
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#endif // __CPU_THREAD_STATE_HH__
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