Ron Dreslinski 4201ec84b2 Fix some unset values in the request in the timing CPU. ... Properly implement the MSHR allocate function. src/cpu/simple/timing.cc: Set the thread context in the CPU. Need to do this properly, currently I just set it to Cpu=0 Thread=0. This will just cause all the stats in the cache based on these to just yield totals and not a distribution. src/mem/cache/miss/mshr.cc: Properly implement the allocate function for the MSHR. --HG-- extra : convert_revision : bcece518e54ed1404db3196f996a77b4dd5c1c1e		2006-07-05 15:13:27 -04:00
..
atomic.cc	AtomicSimpleCPU with a cache now runs the hello world! test program.	2006-06-30 17:21:58 -04:00
atomic.hh	Various fixes for the CPU models to support the features that have been moved to python.	2006-06-29 19:45:24 -04:00
base.cc	add syscall emulation page table fault so we can allocate more stack pages	2006-06-26 16:49:05 -04:00
base.hh	Reorganization/renaming of CPUExecContext. Now it is called SimpleThread in order to clear up the confusion due to the many ExecContexts. It also derives from a common ThreadState object, which holds various state common to threads across CPU models.	2006-06-07 15:29:53 -04:00
timing.cc	Fix some unset values in the request in the timing CPU.	2006-07-05 15:13:27 -04:00
timing.hh	Various fixes for the CPU models to support the features that have been moved to python.	2006-06-29 19:45:24 -04:00