655e9ef3de
base/statistics.cc:
formatting
cpu/simple_cpu/simple_cpu.cc:
cpu/simple_cpu/simple_cpu.hh:
Make numInsts reset by adding a resetStats function
sim/sim_object.cc:
Register the reset callback in a slightly cleaner way to avoid
potential static member constructor ordering issues
--HG--
extra : convert_revision : 408073b4b0397fbf9dfd9c548a313f1c8c3fc031
157 lines
4 KiB
C++
157 lines
4 KiB
C++
/*
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* Copyright (c) 2003 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <assert.h>
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#include "base/callback.hh"
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#include "base/inifile.hh"
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#include "base/misc.hh"
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#include "base/trace.hh"
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#include "sim/configfile.hh"
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#include "sim/host.hh"
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#include "sim/sim_object.hh"
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#include "sim/sim_stats.hh"
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using namespace std;
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////////////////////////////////////////////////////////////////////////
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//
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// SimObject member definitions
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//
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////////////////////////////////////////////////////////////////////////
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//
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// static list of all SimObjects, used for initialization etc.
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//
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SimObject::SimObjectList SimObject::simObjectList;
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//
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// SimObject constructor: used to maintain static simObjectList
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//
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SimObject::SimObject(const string &_name)
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: objName(_name)
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{
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simObjectList.push_back(this);
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}
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//
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// no default statistics, so nothing to do in base implementation
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//
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void
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SimObject::regStats()
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{
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}
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void
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SimObject::regFormulas()
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{
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}
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void
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SimObject::resetStats()
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{
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}
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//
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// no default extra output
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//
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void
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SimObject::printExtraOutput(ostream &os)
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{
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}
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//
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// static function:
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// call regStats() on all SimObjects and then regFormulas() on all
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// SimObjects.
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//
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struct SimObjectResetCB : public Callback
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{
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virtual void process() { SimObject::resetAllStats(); }
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};
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namespace {
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static SimObjectResetCB StatResetCB;
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}
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void
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SimObject::regAllStats()
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{
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SimObjectList::iterator i;
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SimObjectList::iterator end = simObjectList.end();
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/**
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* @todo change cprintfs to DPRINTFs
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*/
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for (i = simObjectList.begin(); i != end; ++i) {
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#ifdef STAT_DEBUG
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cprintf("registering stats for %s\n", (*i)->name());
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#endif
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(*i)->regStats();
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}
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for (i = simObjectList.begin(); i != end; ++i) {
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#ifdef STAT_DEBUG
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cprintf("registering formulas for %s\n", (*i)->name());
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#endif
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(*i)->regFormulas();
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}
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Statistics::RegResetCallback(&StatResetCB);
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}
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//
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// static function: call resetStats() on all SimObjects.
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//
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void
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SimObject::resetAllStats()
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{
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SimObjectList::iterator i = simObjectList.begin();
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SimObjectList::iterator end = simObjectList.end();
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for (; i != end; ++i) {
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SimObject *obj = *i;
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obj->resetStats();
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}
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}
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//
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// static function: call printExtraOutput() on all SimObjects.
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//
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void
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SimObject::printAllExtraOutput(ostream &os)
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{
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SimObjectList::iterator i = simObjectList.begin();
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SimObjectList::iterator end = simObjectList.end();
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for (; i != end; ++i) {
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SimObject *obj = *i;
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obj->printExtraOutput(os);
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}
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}
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