30c588a483
Recent changes added setting of system-wide cache line size and these settings occur in the top-level configs (se.py and fs.py). This setting also needs to take place in ruby_fs.py. This change sets the cache line size as appropriate.
143 lines
5.2 KiB
Python
143 lines
5.2 KiB
Python
# Copyright (c) 2009-2011 Advanced Micro Devices, Inc.
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Brad Beckmann
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#
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# Full system configuraiton for ruby
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#
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import optparse
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import sys
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import m5
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from m5.defines import buildEnv
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from m5.objects import *
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from m5.util import addToPath, fatal
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addToPath('../common')
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addToPath('../ruby')
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addToPath('../topologies')
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import Ruby
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from FSConfig import *
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from SysPaths import *
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from Benchmarks import *
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import Options
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import Simulation
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parser = optparse.OptionParser()
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Options.addCommonOptions(parser)
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Options.addFSOptions(parser)
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# Add the ruby specific and protocol specific options
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Ruby.define_options(parser)
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(options, args) = parser.parse_args()
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options.ruby = True
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if args:
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print "Error: script doesn't take any positional arguments"
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sys.exit(1)
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if options.benchmark:
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try:
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bm = Benchmarks[options.benchmark]
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except KeyError:
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print "Error benchmark %s has not been defined." % options.benchmark
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print "Valid benchmarks are: %s" % DefinedBenchmarks
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sys.exit(1)
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else:
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bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)]
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# Check for timing mode because ruby does not support atomic accesses
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if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
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print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
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sys.exit(1)
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(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
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TestMemClass = Simulation.setMemClass(options)
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if buildEnv['TARGET_ISA'] == "alpha":
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system = makeLinuxAlphaRubySystem(test_mem_mode, bm[0])
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elif buildEnv['TARGET_ISA'] == "x86":
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system = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0], True)
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Simulation.setWorkCountOptions(system, options)
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else:
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fatal("incapable of building non-alpha or non-x86 full system!")
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system.cache_line_size = options.cacheline_size
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# Create a top-level voltage domain and clock domain
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system.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
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system.clk_domain = SrcClockDomain(clock = options.sys_clock,
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voltage_domain = system.voltage_domain)
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if options.kernel is not None:
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system.kernel = binary(options.kernel)
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if options.script is not None:
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system.readfile = options.script
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system.cpu = [CPUClass(cpu_id=i) for i in xrange(options.num_cpus)]
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# Create a source clock for the CPUs and set the clock period
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system.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
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voltage_domain = system.voltage_domain)
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Ruby.create_system(options, system, system.piobus, system._dma_ports)
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# Create a seperate clock domain for Ruby
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system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
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voltage_domain = system.voltage_domain)
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for (i, cpu) in enumerate(system.cpu):
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#
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# Tie the cpu ports to the correct ruby system ports
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#
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cpu.clk_domain = system.cpu_clk_domain
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cpu.createThreads()
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cpu.createInterruptController()
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cpu.icache_port = system.ruby._cpu_ruby_ports[i].slave
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cpu.dcache_port = system.ruby._cpu_ruby_ports[i].slave
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if buildEnv['TARGET_ISA'] == "x86":
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cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].slave
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cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].slave
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cpu.interrupts.pio = system.piobus.master
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cpu.interrupts.int_master = system.piobus.slave
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cpu.interrupts.int_slave = system.piobus.master
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system.ruby._cpu_ruby_ports[i].access_phys_mem = True
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# Create the appropriate memory controllers and connect them to the
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# PIO bus
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system.mem_ctrls = [TestMemClass(range = r) for r in system.mem_ranges]
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for i in xrange(len(system.mem_ctrls)):
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system.mem_ctrls[i].port = system.piobus.master
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root = Root(full_system = True, system = system)
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Simulation.run(options, root, system, FutureClass)
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