Ali Saidi 401165c778 ARM: Further break up condition code into NZ, C, V bits. ... Break up the condition code bits into NZ, C, V registers. These are individually written and this removes some incorrect dependencies between instructions.		2011-05-13 17:27:01 -05:00
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decoder	ARM: Add support for M5 ops in the ARM ISA	2010-11-08 13:58:24 -06:00
formats	ARM: Further break up condition code into NZ, C, V bits.	2011-05-13 17:27:01 -05:00
insts	ARM: Further break up condition code into NZ, C, V bits.	2011-05-13 17:27:01 -05:00
templates	ARM: Further break up condition code into NZ, C, V bits.	2011-05-13 17:27:01 -05:00
bitfields.isa	ARM: Rearrange the load/store double/exclusive, table branch thumb decoding.	2010-06-02 12:58:07 -05:00
copyright.txt	ARM: Remove IsControl from operands that don't imply control transfers.	2010-06-02 12:57:59 -05:00
includes.isa	trace: reimplement the DTRACE function so it doesn't use a vector	2011-04-15 10:44:32 -07:00
main.isa	ARM: Define the load instructions from outside the decoder.	2010-06-02 12:58:01 -05:00
operands.isa	ARM: Further break up condition code into NZ, C, V bits.	2011-05-13 17:27:01 -05:00