cpu/base_dyn_inst.hh: Code cleanup --HG-- extra : convert_revision : 501c03f8e4346ffbcb545ddeee30c1f8ded9baa7
194 lines
5.7 KiB
C++
194 lines
5.7 KiB
C++
/*
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* Copyright (c) 2006 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CPU_OZONE_THREAD_STATE_HH__
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#define __CPU_OZONE_THREAD_STATE_HH__
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#include "arch/faults.hh"
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#include "arch/isa_traits.hh"
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#include "cpu/exec_context.hh"
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#include "cpu/thread_state.hh"
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#include "sim/process.hh"
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class Event;
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//class Process;
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#if FULL_SYSTEM
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class EndQuiesceEvent;
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class FunctionProfile;
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class ProfileNode;
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#else
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class Process;
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class FunctionalMemory;
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#endif
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// Maybe this ozone thread state should only really have committed state?
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// I need to think about why I'm using this and what it's useful for. Clearly
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// has benefits for SMT; basically serves same use as CPUExecContext.
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// Makes the ExecContext proxy easier. Gives organization/central access point
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// to state of a thread that can be accessed normally (i.e. not in-flight
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// stuff within a OoO processor). Does this need an XC proxy within it?
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template <class Impl>
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struct OzoneThreadState : public ThreadState {
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typedef typename ExecContext::Status Status;
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typedef typename Impl::FullCPU FullCPU;
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typedef TheISA::MiscReg MiscReg;
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#if FULL_SYSTEM
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OzoneThreadState(FullCPU *_cpu, int _thread_num, FunctionalMemory *_mem)
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: ThreadState(-1, _thread_num, _mem),
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inSyscall(0), trapPending(0)
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{
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memset(®s, 0, sizeof(TheISA::RegFile));
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}
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#else
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OzoneThreadState(FullCPU *_cpu, int _thread_num, Process *_process, int _asid)
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: ThreadState(-1, _thread_num, _process->getMemory(), _process, _asid),
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cpu(_cpu), inSyscall(0), trapPending(0)
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{
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memset(®s, 0, sizeof(TheISA::RegFile));
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}
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OzoneThreadState(FullCPU *_cpu, int _thread_num, FunctionalMemory *_mem,
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int _asid)
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: ThreadState(-1, _thread_num, _mem, NULL, _asid),
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cpu(_cpu), inSyscall(0), trapPending(0)
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{
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memset(®s, 0, sizeof(TheISA::RegFile));
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}
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#endif
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Status _status;
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Status status() const { return _status; }
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void setStatus(Status new_status) { _status = new_status; }
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RenameTable<Impl> renameTable;
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Addr PC;
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Addr nextPC;
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// Current instruction
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TheISA::MachInst inst;
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TheISA::RegFile regs;
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typename Impl::FullCPU *cpu;
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bool inSyscall;
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bool trapPending;
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ExecContext *xcProxy;
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ExecContext *getXCProxy() { return xcProxy; }
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#if !FULL_SYSTEM
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Fault dummyTranslation(MemReqPtr &req)
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{
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#if 0
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assert((req->vaddr >> 48 & 0xffff) == 0);
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#endif
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// put the asid in the upper 16 bits of the paddr
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req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16);
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req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
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return NoFault;
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}
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Fault translateInstReq(MemReqPtr &req)
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{
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return dummyTranslation(req);
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}
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Fault translateDataReadReq(MemReqPtr &req)
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{
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return dummyTranslation(req);
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}
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Fault translateDataWriteReq(MemReqPtr &req)
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{
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return dummyTranslation(req);
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}
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#else
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Fault translateInstReq(MemReqPtr &req)
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{
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return cpu->itb->translate(req);
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}
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Fault translateDataReadReq(MemReqPtr &req)
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{
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return cpu->dtb->translate(req, false);
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}
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Fault translateDataWriteReq(MemReqPtr &req)
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{
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return cpu->dtb->translate(req, true);
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}
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#endif
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MiscReg readMiscReg(int misc_reg)
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{
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return regs.miscRegs.readReg(misc_reg);
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}
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MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
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{
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return regs.miscRegs.readRegWithEffect(misc_reg, fault, xcProxy);
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}
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Fault setMiscReg(int misc_reg, const MiscReg &val)
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{
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return regs.miscRegs.setReg(misc_reg, val);
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}
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Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
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{
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return regs.miscRegs.setRegWithEffect(misc_reg, val, xcProxy);
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}
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uint64_t readPC()
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{ return PC; }
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void setPC(uint64_t val)
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{ PC = val; }
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uint64_t readNextPC()
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{ return nextPC; }
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void setNextPC(uint64_t val)
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{ nextPC = val; }
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bool misspeculating() { return false; }
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void setInst(TheISA::MachInst _inst) { inst = _inst; }
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Counter readFuncExeInst() { return funcExeInst; }
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void setFuncExeInst(Counter new_val) { funcExeInst = new_val; }
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};
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#endif // __CPU_OZONE_THREAD_STATE_HH__
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