gem5/src/arch/arm/isa/formats/fp.isa

210 lines
7.9 KiB
C++

// -*- mode:c++ -*-
// Copyright (c) 2010 ARM Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder. You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Copyright (c) 2007-2008 The Florida State University
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
// Authors: Stephen Hines
////////////////////////////////////////////////////////////////////
//
// Floating Point operate instructions
//
def template FPAExecute {{
Fault %(class_name)s::execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(fp_enable_check)s;
%(op_decl)s;
%(op_rd)s;
if (%(predicate_test)s) {
%(code)s;
if (fault == NoFault) {
%(op_wb)s;
}
}
return fault;
}
}};
def template FloatDoubleDecode {{
{
ArmStaticInst *i = NULL;
switch (OPCODE_19 << 1 | OPCODE_7)
{
case 0:
i = (ArmStaticInst *)new %(class_name)sS(machInst);
break;
case 1:
i = (ArmStaticInst *)new %(class_name)sD(machInst);
break;
case 2:
case 3:
default:
panic("Cannot decode float/double nature of the instruction");
}
return i;
}
}};
// Primary format for float point operate instructions:
def format FloatOp(code, *flags) {{
orig_code = code
cblk = code
iop = InstObjParams(name, Name, 'PredOp',
{"code": cblk,
"predicate_test": predicateTest},
flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
exec_output = FPAExecute.subst(iop)
sng_cblk = code
sng_iop = InstObjParams(name, Name+'S', 'PredOp',
{"code": sng_cblk,
"predicate_test": predicateTest},
flags)
header_output += BasicDeclare.subst(sng_iop)
decoder_output += BasicConstructor.subst(sng_iop)
exec_output += FPAExecute.subst(sng_iop)
dbl_code = re.sub(r'\.sf', '.df', orig_code)
dbl_cblk = dbl_code
dbl_iop = InstObjParams(name, Name+'D', 'PredOp',
{"code": dbl_cblk,
"predicate_test": predicateTest},
flags)
header_output += BasicDeclare.subst(dbl_iop)
decoder_output += BasicConstructor.subst(dbl_iop)
exec_output += FPAExecute.subst(dbl_iop)
decode_block = FloatDoubleDecode.subst(iop)
}};
let {{
calcFPCcCode = '''
uint16_t _in, _iz, _ic, _iv;
_in = %(fReg1)s < %(fReg2)s;
_iz = %(fReg1)s == %(fReg2)s;
_ic = %(fReg1)s >= %(fReg2)s;
_iv = (isnan(%(fReg1)s) || isnan(%(fReg2)s)) & 1;
CondCodes = _in << 31 | _iz << 30 | _ic << 29 | _iv << 28 |
(CondCodes & 0x0FFFFFFF);
'''
}};
def format FloatCmp(fReg1, fReg2, *flags) {{
code = calcFPCcCode % vars()
iop = InstObjParams(name, Name, 'PredOp',
{"code": code,
"predicate_test": predicateTest},
flags)
header_output = BasicDeclare.subst(iop)
decoder_output = BasicConstructor.subst(iop)
decode_block = BasicDecode.subst(iop)
exec_output = FPAExecute.subst(iop)
}};
def format ExtensionRegLoadStore() {{
decode_block = '''
{
const uint32_t opcode = bits(machInst, 24, 20);
const uint32_t offset = bits(machInst, 7, 0);
const bool single = bits(machInst, 22);
const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
RegIndex vd;
if (single) {
vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
bits(machInst, 22));
} else {
vd = (RegIndex)(uint32_t)((bits(machInst, 15, 12) << 1) |
(bits(machInst, 22) << 5));
}
switch (bits(opcode, 4, 3)) {
case 0x0:
if (bits(opcode, 4, 1) == 0x2) {
return new WarnUnimplemented("core-to-extension-transfer",
machInst);
}
break;
case 0x1:
switch (bits(opcode, 1, 0)) {
case 0x0:
return new VLdmStm(machInst, rn, vd, single,
true, false, false, offset);
case 0x1:
return new VLdmStm(machInst, rn, vd, single,
true, false, true, offset);
case 0x2:
return new VLdmStm(machInst, rn, vd, single,
true, true, false, offset);
case 0x3:
// If rn == sp, then this is called vpop.
return new VLdmStm(machInst, rn, vd, single,
true, true, true, offset);
}
case 0x2:
if (bits(opcode, 1, 0) == 0x2) {
// If rn == sp, then this is called vpush.
return new VLdmStm(machInst, rn, vd, single,
false, true, false, offset);
} else if (bits(opcode, 1, 0) == 0x3) {
return new VLdmStm(machInst, rn, vd, single,
false, true, true, offset);
}
// Fall through on purpose
case 0x3:
if (bits(opcode, 1, 0) == 0x0) {
return new WarnUnimplemented("vstr", machInst);
} else if (bits(opcode, 1, 0) == 0x1) {
return new WarnUnimplemented("vldr", machInst);
}
}
return new Unknown(machInst);
}
'''
}};