612 lines
21 KiB
C++
612 lines
21 KiB
C++
/*
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* Copyright (c) 2009 Advanced Micro Devices, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "cpu/testers/rubytest/RubyTester.hh"
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#include "debug/Ruby.hh"
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#include "mem/protocol/AccessPermission.hh"
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#include "mem/ruby/slicc_interface/AbstractController.hh"
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#include "mem/ruby/system/RubyPort.hh"
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#include "mem/physical.hh"
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RubyPort::RubyPort(const Params *p)
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: MemObject(p)
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{
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m_version = p->version;
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assert(m_version != -1);
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physmem = p->physmem;
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m_controller = NULL;
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m_mandatory_q_ptr = NULL;
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m_request_cnt = 0;
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pio_port = NULL;
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physMemPort = NULL;
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m_usingRubyTester = p->using_ruby_tester;
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access_phys_mem = p->access_phys_mem;
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ruby_system = p->ruby_system;
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waitingOnSequencer = false;
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}
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void
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RubyPort::init()
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{
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assert(m_controller != NULL);
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m_mandatory_q_ptr = m_controller->getMandatoryQueue();
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}
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Port *
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RubyPort::getPort(const std::string &if_name, int idx)
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{
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if (if_name == "port") {
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M5Port* cpuPort = new M5Port(csprintf("%s-port%d", name(), idx),
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this, ruby_system, access_phys_mem);
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cpu_ports.push_back(cpuPort);
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return cpuPort;
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}
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if (if_name == "pio_port") {
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// ensure there is only one pio port
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assert(pio_port == NULL);
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pio_port = new PioPort(csprintf("%s-pio-port%d", name(), idx), this);
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return pio_port;
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}
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if (if_name == "physMemPort") {
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// RubyPort should only have one port to physical memory
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assert (physMemPort == NULL);
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physMemPort = new M5Port(csprintf("%s-physMemPort", name()), this,
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ruby_system, access_phys_mem);
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return physMemPort;
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}
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if (if_name == "functional") {
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// Calls for the functional port only want to access
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// functional memory. Therefore, directly pass these calls
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// ports to physmem.
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assert(physmem != NULL);
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return physmem->getPort(if_name, idx);
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}
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return NULL;
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}
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RubyPort::PioPort::PioPort(const std::string &_name,
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RubyPort *_port)
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: SimpleTimingPort(_name, _port)
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{
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DPRINTF(RubyPort, "creating port to ruby sequencer to cpu %s\n", _name);
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ruby_port = _port;
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}
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RubyPort::M5Port::M5Port(const std::string &_name, RubyPort *_port,
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RubySystem *_system, bool _access_phys_mem)
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: SimpleTimingPort(_name, _port)
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{
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DPRINTF(RubyPort, "creating port from ruby sequcner to cpu %s\n", _name);
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ruby_port = _port;
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ruby_system = _system;
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_onRetryList = false;
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access_phys_mem = _access_phys_mem;
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}
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Tick
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RubyPort::PioPort::recvAtomic(PacketPtr pkt)
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{
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panic("RubyPort::PioPort::recvAtomic() not implemented!\n");
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return 0;
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}
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Tick
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RubyPort::M5Port::recvAtomic(PacketPtr pkt)
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{
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panic("RubyPort::M5Port::recvAtomic() not implemented!\n");
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return 0;
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}
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bool
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RubyPort::PioPort::recvTiming(PacketPtr pkt)
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{
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// In FS mode, ruby memory will receive pio responses from devices
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// and it must forward these responses back to the particular CPU.
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DPRINTF(RubyPort, "Pio response for address %#x\n", pkt->getAddr());
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assert(pkt->isResponse());
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// First we must retrieve the request port from the sender State
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RubyPort::SenderState *senderState =
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safe_cast<RubyPort::SenderState *>(pkt->senderState);
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M5Port *port = senderState->port;
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assert(port != NULL);
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// pop the sender state from the packet
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pkt->senderState = senderState->saved;
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delete senderState;
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port->sendTiming(pkt);
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return true;
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}
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bool
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RubyPort::M5Port::recvTiming(PacketPtr pkt)
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{
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DPRINTF(RubyPort,
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"Timing access caught for address %#x\n", pkt->getAddr());
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//dsm: based on SimpleTimingPort::recvTiming(pkt);
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// The received packets should only be M5 requests, which should never
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// get nacked. There used to be code to hanldle nacks here, but
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// I'm pretty sure it didn't work correctly with the drain code,
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// so that would need to be fixed if we ever added it back.
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assert(pkt->isRequest());
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if (pkt->memInhibitAsserted()) {
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warn("memInhibitAsserted???");
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// snooper will supply based on copy of packet
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// still target's responsibility to delete packet
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delete pkt;
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return true;
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}
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// Save the port in the sender state object to be used later to
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// route the response
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pkt->senderState = new SenderState(this, pkt->senderState);
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// Check for pio requests and directly send them to the dedicated
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// pio port.
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if (!isPhysMemAddress(pkt->getAddr())) {
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assert(ruby_port->pio_port != NULL);
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DPRINTF(RubyPort,
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"Request for address 0x%#x is assumed to be a pio request\n",
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pkt->getAddr());
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return ruby_port->pio_port->sendTiming(pkt);
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}
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assert(Address(pkt->getAddr()).getOffset() + pkt->getSize() <=
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RubySystem::getBlockSizeBytes());
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// Submit the ruby request
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RequestStatus requestStatus = ruby_port->makeRequest(pkt);
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// If the request successfully issued then we should return true.
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// Otherwise, we need to delete the senderStatus we just created and return
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// false.
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if (requestStatus == RequestStatus_Issued) {
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DPRINTF(RubyPort, "Request %#x issued\n", pkt->getAddr());
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return true;
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}
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//
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// Unless one is using the ruby tester, record the stalled M5 port for
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// later retry when the sequencer becomes free.
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//
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if (!ruby_port->m_usingRubyTester) {
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ruby_port->addToRetryList(this);
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}
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DPRINTF(RubyPort,
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"Request for address %#x did not issue because %s\n",
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pkt->getAddr(), RequestStatus_to_string(requestStatus));
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SenderState* senderState = safe_cast<SenderState*>(pkt->senderState);
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pkt->senderState = senderState->saved;
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delete senderState;
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return false;
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}
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bool
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RubyPort::M5Port::doFunctionalRead(PacketPtr pkt)
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{
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Address address(pkt->getAddr());
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Address line_address(address);
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line_address.makeLineAddress();
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AccessPermission access_perm = AccessPermission_NotPresent;
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int num_controllers = ruby_system->m_abs_cntrl_vec.size();
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DPRINTF(RubyPort, "Functional Read request for %s\n",address);
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unsigned int num_ro = 0;
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unsigned int num_rw = 0;
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unsigned int num_busy = 0;
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unsigned int num_backing_store = 0;
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unsigned int num_invalid = 0;
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// In this loop we count the number of controllers that have the given
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// address in read only, read write and busy states.
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for (int i = 0; i < num_controllers; ++i) {
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access_perm = ruby_system->m_abs_cntrl_vec[i]->
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getAccessPermission(line_address);
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if (access_perm == AccessPermission_Read_Only)
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num_ro++;
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else if (access_perm == AccessPermission_Read_Write)
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num_rw++;
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else if (access_perm == AccessPermission_Busy)
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num_busy++;
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else if (access_perm == AccessPermission_Backing_Store)
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// See RubySlicc_Exports.sm for details, but Backing_Store is meant
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// to represent blocks in memory *for Broadcast/Snooping protocols*,
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// where memory has no idea whether it has an exclusive copy of data
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// or not.
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num_backing_store++;
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else if (access_perm == AccessPermission_Invalid ||
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access_perm == AccessPermission_NotPresent)
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num_invalid++;
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}
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assert(num_rw <= 1);
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uint8* data = pkt->getPtr<uint8_t>(true);
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unsigned int size_in_bytes = pkt->getSize();
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unsigned startByte = address.getAddress() - line_address.getAddress();
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// This if case is meant to capture what happens in a Broadcast/Snoop
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// protocol where the block does not exist in the cache hierarchy. You
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// only want to read from the Backing_Store memory if there is no copy in
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// the cache hierarchy, otherwise you want to try to read the RO or RW
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// copies existing in the cache hierarchy (covered by the else statement).
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// The reason is because the Backing_Store memory could easily be stale, if
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// there are copies floating around the cache hierarchy, so you want to read
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// it only if it's not in the cache hierarchy at all.
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if (num_invalid == (num_controllers - 1) &&
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num_backing_store == 1)
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{
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DPRINTF(RubyPort, "only copy in Backing_Store memory, read from it\n");
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for (int i = 0; i < num_controllers; ++i) {
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access_perm = ruby_system->m_abs_cntrl_vec[i]
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->getAccessPermission(line_address);
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if (access_perm == AccessPermission_Backing_Store) {
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DataBlock& block = ruby_system->m_abs_cntrl_vec[i]
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->getDataBlock(line_address);
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DPRINTF(RubyPort, "reading from %s block %s\n",
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ruby_system->m_abs_cntrl_vec[i]->name(), block);
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for (unsigned i = 0; i < size_in_bytes; ++i) {
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data[i] = block.getByte(i + startByte);
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}
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return true;
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}
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}
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} else {
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// In Broadcast/Snoop protocols, this covers if you know the block
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// exists somewhere in the caching hierarchy, then you want to read any
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// valid RO or RW block. In directory protocols, same thing, you want
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// to read any valid readable copy of the block.
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DPRINTF(RubyPort, "num_busy = %d, num_ro = %d, num_rw = %d\n",
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num_busy, num_ro, num_rw);
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// In this loop, we try to figure which controller has a read only or
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// a read write copy of the given address. Any valid copy would suffice
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// for a functional read.
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for(int i = 0;i < num_controllers;++i) {
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access_perm = ruby_system->m_abs_cntrl_vec[i]
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->getAccessPermission(line_address);
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if(access_perm == AccessPermission_Read_Only ||
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access_perm == AccessPermission_Read_Write)
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{
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DataBlock& block = ruby_system->m_abs_cntrl_vec[i]
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->getDataBlock(line_address);
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DPRINTF(RubyPort, "reading from %s block %s\n",
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ruby_system->m_abs_cntrl_vec[i]->name(), block);
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for (unsigned i = 0; i < size_in_bytes; ++i) {
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data[i] = block.getByte(i + startByte);
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}
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return true;
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}
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}
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}
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return false;
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}
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bool
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RubyPort::M5Port::doFunctionalWrite(PacketPtr pkt)
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{
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Address addr(pkt->getAddr());
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Address line_addr = line_address(addr);
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AccessPermission access_perm = AccessPermission_NotPresent;
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int num_controllers = ruby_system->m_abs_cntrl_vec.size();
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DPRINTF(RubyPort, "Functional Write request for %s\n",addr);
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unsigned int num_ro = 0;
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unsigned int num_rw = 0;
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unsigned int num_busy = 0;
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unsigned int num_backing_store = 0;
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unsigned int num_invalid = 0;
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// In this loop we count the number of controllers that have the given
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// address in read only, read write and busy states.
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for(int i = 0;i < num_controllers;++i) {
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access_perm = ruby_system->m_abs_cntrl_vec[i]->
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getAccessPermission(line_addr);
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if (access_perm == AccessPermission_Read_Only)
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num_ro++;
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else if (access_perm == AccessPermission_Read_Write)
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num_rw++;
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else if (access_perm == AccessPermission_Busy)
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num_busy++;
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else if (access_perm == AccessPermission_Backing_Store)
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// See RubySlicc_Exports.sm for details, but Backing_Store is meant
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// to represent blocks in memory *for Broadcast/Snooping protocols*,
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// where memory has no idea whether it has an exclusive copy of data
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// or not.
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num_backing_store++;
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else if (access_perm == AccessPermission_Invalid ||
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access_perm == AccessPermission_NotPresent)
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num_invalid++;
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}
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// If the number of read write copies is more than 1, then there is bug in
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// coherence protocol. Otherwise, if all copies are in stable states, i.e.
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// num_busy == 0, we update all the copies. If there is at least one copy
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// in busy state, then we check if there is read write copy. If yes, then
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// also we let the access go through. Or, if there is no copy in the cache
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// hierarchy at all, we still want to do the write to the memory
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// (Backing_Store) instead of failing.
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DPRINTF(RubyPort, "num_busy = %d, num_ro = %d, num_rw = %d\n",
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num_busy, num_ro, num_rw);
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assert(num_rw <= 1);
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uint8* data = pkt->getPtr<uint8_t>(true);
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unsigned int size_in_bytes = pkt->getSize();
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unsigned startByte = addr.getAddress() - line_addr.getAddress();
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if ((num_busy == 0 && num_ro > 0) || num_rw == 1 ||
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(num_invalid == (num_controllers - 1) && num_backing_store == 1))
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{
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for(int i = 0; i < num_controllers;++i) {
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access_perm = ruby_system->m_abs_cntrl_vec[i]->
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getAccessPermission(line_addr);
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if(access_perm == AccessPermission_Read_Only ||
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access_perm == AccessPermission_Read_Write||
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access_perm == AccessPermission_Maybe_Stale ||
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access_perm == AccessPermission_Backing_Store)
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{
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DataBlock& block = ruby_system->m_abs_cntrl_vec[i]
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->getDataBlock(line_addr);
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DPRINTF(RubyPort, "%s\n",block);
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for (unsigned i = 0; i < size_in_bytes; ++i) {
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block.setByte(i + startByte, data[i]);
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}
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DPRINTF(RubyPort, "%s\n",block);
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}
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}
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return true;
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}
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return false;
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}
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void
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RubyPort::M5Port::recvFunctional(PacketPtr pkt)
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{
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DPRINTF(RubyPort, "Functional access caught for address %#x\n",
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pkt->getAddr());
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// Check for pio requests and directly send them to the dedicated
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// pio port.
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if (!isPhysMemAddress(pkt->getAddr())) {
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assert(ruby_port->pio_port != NULL);
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DPRINTF(RubyPort, "Request for address 0x%#x is a pio request\n",
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pkt->getAddr());
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panic("RubyPort::PioPort::recvFunctional() not implemented!\n");
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}
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assert(pkt->getAddr() + pkt->getSize() <=
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line_address(Address(pkt->getAddr())).getAddress() +
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RubySystem::getBlockSizeBytes());
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bool accessSucceeded = false;
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bool needsResponse = pkt->needsResponse();
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// Do the functional access on ruby memory
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if (pkt->isRead()) {
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accessSucceeded = doFunctionalRead(pkt);
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} else if (pkt->isWrite()) {
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accessSucceeded = doFunctionalWrite(pkt);
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} else {
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panic("RubyPort: unsupported functional command %s\n",
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pkt->cmdString());
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}
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// Unless the requester explicitly said otherwise, generate an error if
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// the functional request failed
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if (!accessSucceeded && !pkt->suppressFuncError()) {
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fatal("Ruby functional %s failed for address %#x\n",
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pkt->isWrite() ? "write" : "read", pkt->getAddr());
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}
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if (access_phys_mem) {
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// The attached physmem contains the official version of data.
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// The following command performs the real functional access.
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// This line should be removed once Ruby supplies the official version
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// of data.
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ruby_port->physMemPort->sendFunctional(pkt);
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}
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// turn packet around to go back to requester if response expected
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if (needsResponse) {
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pkt->setFunctionalResponseStatus(accessSucceeded);
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DPRINTF(RubyPort, "Sending packet back over port\n");
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sendFunctional(pkt);
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}
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DPRINTF(RubyPort, "Functional access %s!\n",
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accessSucceeded ? "successful":"failed");
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}
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void
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RubyPort::ruby_hit_callback(PacketPtr pkt)
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{
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// Retrieve the request port from the sender State
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RubyPort::SenderState *senderState =
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safe_cast<RubyPort::SenderState *>(pkt->senderState);
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M5Port *port = senderState->port;
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assert(port != NULL);
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// pop the sender state from the packet
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pkt->senderState = senderState->saved;
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delete senderState;
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port->hitCallback(pkt);
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//
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// If we had to stall the M5Ports, wake them up because the sequencer
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// likely has free resources now.
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//
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if (waitingOnSequencer) {
|
|
//
|
|
// Record the current list of ports to retry on a temporary list before
|
|
// calling sendRetry on those ports. sendRetry will cause an
|
|
// immediate retry, which may result in the ports being put back on the
|
|
// list. Therefore we want to clear the retryList before calling
|
|
// sendRetry.
|
|
//
|
|
std::list<M5Port*> curRetryList(retryList);
|
|
|
|
retryList.clear();
|
|
waitingOnSequencer = false;
|
|
|
|
for (std::list<M5Port*>::iterator i = curRetryList.begin();
|
|
i != curRetryList.end(); ++i) {
|
|
DPRINTF(RubyPort,
|
|
"Sequencer may now be free. SendRetry to port %s\n",
|
|
(*i)->name());
|
|
(*i)->onRetryList(false);
|
|
(*i)->sendRetry();
|
|
}
|
|
}
|
|
}
|
|
|
|
void
|
|
RubyPort::M5Port::hitCallback(PacketPtr pkt)
|
|
{
|
|
bool needsResponse = pkt->needsResponse();
|
|
|
|
//
|
|
// Unless specified at configuraiton, all responses except failed SC
|
|
// and Flush operations access M5 physical memory.
|
|
//
|
|
bool accessPhysMem = access_phys_mem;
|
|
|
|
if (pkt->isLLSC()) {
|
|
if (pkt->isWrite()) {
|
|
if (pkt->req->getExtraData() != 0) {
|
|
//
|
|
// Successful SC packets convert to normal writes
|
|
//
|
|
pkt->convertScToWrite();
|
|
} else {
|
|
//
|
|
// Failed SC packets don't access physical memory and thus
|
|
// the RubyPort itself must convert it to a response.
|
|
//
|
|
accessPhysMem = false;
|
|
}
|
|
} else {
|
|
//
|
|
// All LL packets convert to normal loads so that M5 PhysMem does
|
|
// not lock the blocks.
|
|
//
|
|
pkt->convertLlToRead();
|
|
}
|
|
}
|
|
|
|
//
|
|
// Flush requests don't access physical memory
|
|
//
|
|
if (pkt->isFlush()) {
|
|
accessPhysMem = false;
|
|
}
|
|
|
|
DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse);
|
|
|
|
if (accessPhysMem) {
|
|
ruby_port->physMemPort->sendAtomic(pkt);
|
|
} else if (needsResponse) {
|
|
pkt->makeResponse();
|
|
}
|
|
|
|
// turn packet around to go back to requester if response expected
|
|
if (needsResponse) {
|
|
DPRINTF(RubyPort, "Sending packet back over port\n");
|
|
sendTiming(pkt);
|
|
} else {
|
|
delete pkt;
|
|
}
|
|
DPRINTF(RubyPort, "Hit callback done!\n");
|
|
}
|
|
|
|
bool
|
|
RubyPort::M5Port::sendTiming(PacketPtr pkt)
|
|
{
|
|
//minimum latency, must be > 0
|
|
schedSendTiming(pkt, curTick() + (1 * g_eventQueue_ptr->getClock()));
|
|
return true;
|
|
}
|
|
|
|
bool
|
|
RubyPort::PioPort::sendTiming(PacketPtr pkt)
|
|
{
|
|
//minimum latency, must be > 0
|
|
schedSendTiming(pkt, curTick() + (1 * g_eventQueue_ptr->getClock()));
|
|
return true;
|
|
}
|
|
|
|
bool
|
|
RubyPort::M5Port::isPhysMemAddress(Addr addr)
|
|
{
|
|
AddrRangeList physMemAddrList;
|
|
bool snoop = false;
|
|
ruby_port->physMemPort->getPeerAddressRanges(physMemAddrList, snoop);
|
|
for (AddrRangeIter iter = physMemAddrList.begin();
|
|
iter != physMemAddrList.end();
|
|
iter++) {
|
|
if (addr >= iter->start && addr <= iter->end) {
|
|
DPRINTF(RubyPort, "Request found in %#llx - %#llx range\n",
|
|
iter->start, iter->end);
|
|
return true;
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
unsigned
|
|
RubyPort::M5Port::deviceBlockSize() const
|
|
{
|
|
return (unsigned) RubySystem::getBlockSizeBytes();
|
|
}
|