463aa6d49d
arch/alpha/alpha_linux_process.cc: Added using directive for AlphaISA namespace arch/alpha/alpha_memory.hh: arch/alpha/isa/branch.isa: cpu/pc_event.hh: Added typedefs for Addr arch/alpha/alpha_tru64_process.cc: arch/alpha/arguments.cc: Added using directive for AlphaISA arch/alpha/ev5.hh: Added an include of arch/alpha/isa_traits.hh, and a using directive for the AlphaISA namespace. arch/alpha/faults.hh: Added a typedef for the Addr type, and changed the formatting of the faults slightly. arch/alpha/isa/main.isa: Untemplatized StaticInst, added a using for namespace AlphaISA to show up in decoder.cc and the exec.ccs, relocated makeNop to decoder.hh arch/alpha/isa/mem.isa: Untemplatized StaticInst and StaticInstPtr arch/alpha/isa/pal.isa: cpu/base_dyn_inst.cc: Untemplatized StaticInstPtr arch/alpha/isa_traits.hh: Changed variables to be externs instead of static since they are part of a namespace and not a class. arch/alpha/stacktrace.cc: Untemplatized StaticInstPtr, and added a using directive for AlphaISA. arch/alpha/stacktrace.hh: Added some typedefs for Addr and MachInst, and untemplatized StaticInstPtr arch/alpha/vtophys.cc: Added a using directive for AlphaISA arch/alpha/vtophys.hh: Added the AlphaISA namespace specifier where needed arch/isa_parser.py: Changed the placement of the definition of the decodeInst function to be outside the namespaceInst namespace. base/loader/object_file.hh: cpu/o3/bpred_unit.hh: Added a typedef for Addr base/loader/symtab.hh: Added a typedef for Addr, and added a TheISA to Addr in another typedef base/remote_gdb.cc: Added a using namespace TheISA, and untemplatized StaticInstPtr base/remote_gdb.hh: Added typedefs for Addr and MachInst cpu/base.cc: Added TheISA specifier to some variables exported from the isa. cpu/base.hh: Added a typedef for Addr, and TheISA to some variables from the ISA cpu/base_dyn_inst.hh: Untemplatized StaticInstPtr, and added TheISA specifier to some variables from the ISA. cpu/exec_context.hh: Added some typedefs for types from the isa, and added TheISA specifier to some variables from the isa cpu/exetrace.hh: Added typedefs for some types from the ISA, and untemplatized StaticInstPtr cpu/memtest/memtest.cc: cpu/o3/btb.cc: dev/baddev.cc: dev/ide_ctrl.cc: dev/ide_disk.cc: dev/isa_fake.cc: dev/ns_gige.cc: dev/pciconfigall.cc: dev/platform.cc: dev/sinic.cc: dev/uart8250.cc: kern/freebsd/freebsd_system.cc: kern/linux/linux_system.cc: kern/system_events.cc: kern/tru64/dump_mbuf.cc: kern/tru64/tru64_events.cc: sim/process.cc: sim/pseudo_inst.cc: sim/system.cc: Added using namespace TheISA cpu/memtest/memtest.hh: cpu/trace/opt_cpu.hh: cpu/trace/reader/itx_reader.hh: dev/ide_disk.hh: dev/pcidev.hh: dev/platform.hh: dev/tsunami.hh: sim/system.hh: sim/vptr.hh: Added typedef for Addr cpu/o3/2bit_local_pred.hh: Changed the include to use arch/isa_traits.hh instead of arch/alpha/isa_traits.hh. Added typedef for Addr cpu/o3/alpha_cpu.hh: Added typedefs for Addr and IntReg cpu/o3/alpha_cpu_impl.hh: Added this-> to setNextPC to fix a problem since it didn't depend on template parameters any more. Removed "typename" where it was no longer needed. cpu/o3/alpha_dyn_inst.hh: Cleaned up some typedefs, and untemplatized StaticInst cpu/o3/alpha_dyn_inst_impl.hh: untemplatized StaticInstPtr cpu/o3/alpha_impl.hh: Fixed up a typedef of MachInst cpu/o3/bpred_unit_impl.hh: Added a using TheISA::MachInst to a function cpu/o3/btb.hh: Changed an include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr cpu/o3/commit.hh: Removed a typedef of Impl::ISA as ISA, since TheISA takes care of this now. cpu/o3/cpu.cc: Cleaned up namespace issues cpu/o3/cpu.hh: Cleaned up namespace usage cpu/o3/decode.hh: Removed typedef of ISA, and changed it to TheISA cpu/o3/fetch.hh: Fized up typedefs, and changed ISA to TheISA cpu/o3/free_list.hh: Changed include of arch/alpha/isa_traits.hh to arch/isa_traits.hh cpu/o3/iew.hh: Removed typedef of ISA cpu/o3/iew_impl.hh: Added TheISA namespace specifier to MachInst cpu/o3/ras.hh: Changed include from arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef for Addr. cpu/o3/regfile.hh: Changed ISA to TheISA, and added some typedefs for Addr, IntReg, FloatReg, and MiscRegFile cpu/o3/rename.hh: Changed ISA to TheISA, and added a typedef for RegIndex cpu/o3/rename_map.hh: Added an include for arch/isa_traits.hh, and a typedef for RegIndex cpu/o3/rob.hh: Added a typedef for RegIndex cpu/o3/store_set.hh: cpu/o3/tournament_pred.hh: Changed an include of arch/alpha/isa_traits.hh to arch/isa_traits.hh, and added a typedef of Addr cpu/ozone/cpu.hh: Changed ISA into TheISA, and untemplatized StaticInst cpu/pc_event.cc: Added namespace specifier TheISA to Addr types cpu/profile.hh: kern/kernel_stats.hh: Added typedef for Addr, and untemplatized StaticInstPtr cpu/simple/cpu.cc: Changed using directive from LittleEndianGuest to AlphaISA, which will contain both namespaces. Added TheISA where needed, and untemplatized StaticInst cpu/simple/cpu.hh: Added a typedef for MachInst, and untemplatized StaticInst cpu/static_inst.cc: Untemplatized StaticInst cpu/static_inst.hh: Untemplatized StaticInst by using the TheISA namespace dev/alpha_console.cc: Added using namespace AlphaISA dev/simple_disk.hh: Added typedef for Addr and fixed up some formatting dev/sinicreg.hh: Added TheISA namespace specifier where needed dev/tsunami.cc: dev/tsunami_io.cc: dev/tsunami_pchip.cc: Added using namespace TheISA. It might be better for it to be AlphaISA dev/tsunami_cchip.cc: Added typedef for TheISA. It might be better for it to be AlphaISA kern/linux/aligned.hh: sim/pseudo_inst.hh: Added TheISA namespace specifier to Addr kern/linux/linux_threadinfo.hh: Added typedef for Addr, and TheISA namespace specifier to StackPointerReg kern/tru64/mbuf.hh: Added TheISA to Addr type in structs sim/process.hh: Added typedefs of Addr, RegFile, and MachInst sim/syscall_emul.cc: Added using namespace TheISA, and a cast of VMPageSize to the int type sim/syscall_emul.hh: Added typecast for Addr, and TheISA namespace specifier for where needed --HG-- extra : convert_revision : 91d4f6ca33a73b21c1f1771d74bfdea3b80eff45
265 lines
7.5 KiB
C++
265 lines
7.5 KiB
C++
/*
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* Copyright (c) 2002-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <string>
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#include "arch/alpha/vtophys.hh"
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#include "base/trace.hh"
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#include "cpu/exec_context.hh"
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#include "mem/functional/physical.hh"
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using namespace std;
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using namespace AlphaISA;
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AlphaISA::PageTableEntry
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kernel_pte_lookup(PhysicalMemory *pmem, Addr ptbr, AlphaISA::VAddr vaddr)
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{
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Addr level1_pte = ptbr + vaddr.level1();
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AlphaISA::PageTableEntry level1 = pmem->phys_read_qword(level1_pte);
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if (!level1.valid()) {
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DPRINTF(VtoPhys, "level 1 PTE not valid, va = %#\n", vaddr);
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return 0;
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}
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Addr level2_pte = level1.paddr() + vaddr.level2();
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AlphaISA::PageTableEntry level2 = pmem->phys_read_qword(level2_pte);
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if (!level2.valid()) {
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DPRINTF(VtoPhys, "level 2 PTE not valid, va = %#x\n", vaddr);
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return 0;
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}
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Addr level3_pte = level2.paddr() + vaddr.level3();
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AlphaISA::PageTableEntry level3 = pmem->phys_read_qword(level3_pte);
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if (!level3.valid()) {
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DPRINTF(VtoPhys, "level 3 PTE not valid, va = %#x\n", vaddr);
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return 0;
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}
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return level3;
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}
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Addr
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vtophys(PhysicalMemory *xc, Addr vaddr)
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{
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Addr paddr = 0;
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if (AlphaISA::IsUSeg(vaddr))
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DPRINTF(VtoPhys, "vtophys: invalid vaddr %#x", vaddr);
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else if (AlphaISA::IsK0Seg(vaddr))
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paddr = AlphaISA::K0Seg2Phys(vaddr);
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else
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panic("vtophys: ptbr is not set on virtual lookup");
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DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr);
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return paddr;
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}
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Addr
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vtophys(ExecContext *xc, Addr addr)
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{
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AlphaISA::VAddr vaddr = addr;
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Addr ptbr = xc->regs.ipr[AlphaISA::IPR_PALtemp20];
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Addr paddr = 0;
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//@todo Andrew couldn't remember why he commented some of this code
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//so I put it back in. Perhaps something to do with gdb debugging?
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if (AlphaISA::PcPAL(vaddr) && (vaddr < EV5::PalMax)) {
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paddr = vaddr & ~ULL(1);
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} else {
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if (AlphaISA::IsK0Seg(vaddr)) {
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paddr = AlphaISA::K0Seg2Phys(vaddr);
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} else if (!ptbr) {
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paddr = vaddr;
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} else {
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AlphaISA::PageTableEntry pte =
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kernel_pte_lookup(xc->physmem, ptbr, vaddr);
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if (pte.valid())
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paddr = pte.paddr() | vaddr.offset();
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}
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}
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DPRINTF(VtoPhys, "vtophys(%#x) -> %#x\n", vaddr, paddr);
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return paddr;
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}
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uint8_t *
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ptomem(ExecContext *xc, Addr paddr, size_t len)
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{
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return xc->physmem->dma_addr(paddr, len);
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}
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uint8_t *
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vtomem(ExecContext *xc, Addr vaddr, size_t len)
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{
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Addr paddr = vtophys(xc, vaddr);
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return xc->physmem->dma_addr(paddr, len);
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}
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void
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CopyOut(ExecContext *xc, void *dest, Addr src, size_t cplen)
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{
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Addr paddr;
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char *dmaaddr;
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char *dst = (char *)dest;
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int len;
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paddr = vtophys(xc, src);
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len = min((int)(AlphaISA::PageBytes - (paddr & AlphaISA::PageOffset)),
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(int)cplen);
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dmaaddr = (char *)xc->physmem->dma_addr(paddr, len);
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assert(dmaaddr);
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memcpy(dst, dmaaddr, len);
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if (len == cplen)
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return;
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cplen -= len;
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dst += len;
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src += len;
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while (cplen > AlphaISA::PageBytes) {
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paddr = vtophys(xc, src);
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dmaaddr = (char *)xc->physmem->dma_addr(paddr, AlphaISA::PageBytes);
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assert(dmaaddr);
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memcpy(dst, dmaaddr, AlphaISA::PageBytes);
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cplen -= AlphaISA::PageBytes;
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dst += AlphaISA::PageBytes;
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src += AlphaISA::PageBytes;
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}
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if (cplen > 0) {
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paddr = vtophys(xc, src);
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dmaaddr = (char *)xc->physmem->dma_addr(paddr, cplen);
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assert(dmaaddr);
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memcpy(dst, dmaaddr, cplen);
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}
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}
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void
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CopyIn(ExecContext *xc, Addr dest, void *source, size_t cplen)
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{
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Addr paddr;
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char *dmaaddr;
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char *src = (char *)source;
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int len;
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paddr = vtophys(xc, dest);
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len = min((int)(AlphaISA::PageBytes - (paddr & AlphaISA::PageOffset)),
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(int)cplen);
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dmaaddr = (char *)xc->physmem->dma_addr(paddr, len);
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assert(dmaaddr);
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memcpy(dmaaddr, src, len);
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if (len == cplen)
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return;
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cplen -= len;
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src += len;
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dest += len;
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while (cplen > AlphaISA::PageBytes) {
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paddr = vtophys(xc, dest);
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dmaaddr = (char *)xc->physmem->dma_addr(paddr, AlphaISA::PageBytes);
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assert(dmaaddr);
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memcpy(dmaaddr, src, AlphaISA::PageBytes);
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cplen -= AlphaISA::PageBytes;
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src += AlphaISA::PageBytes;
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dest += AlphaISA::PageBytes;
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}
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if (cplen > 0) {
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paddr = vtophys(xc, dest);
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dmaaddr = (char *)xc->physmem->dma_addr(paddr, cplen);
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assert(dmaaddr);
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memcpy(dmaaddr, src, cplen);
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}
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}
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void
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CopyString(ExecContext *xc, char *dst, Addr vaddr, size_t maxlen)
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{
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Addr paddr;
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char *dmaaddr;
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int len;
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paddr = vtophys(xc, vaddr);
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len = min((int)(AlphaISA::PageBytes - (paddr & AlphaISA::PageOffset)),
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(int)maxlen);
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dmaaddr = (char *)xc->physmem->dma_addr(paddr, len);
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assert(dmaaddr);
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char *term = (char *)memchr(dmaaddr, 0, len);
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if (term)
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len = term - dmaaddr + 1;
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memcpy(dst, dmaaddr, len);
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if (term || len == maxlen)
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return;
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maxlen -= len;
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dst += len;
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vaddr += len;
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while (maxlen > AlphaISA::PageBytes) {
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paddr = vtophys(xc, vaddr);
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dmaaddr = (char *)xc->physmem->dma_addr(paddr, AlphaISA::PageBytes);
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assert(dmaaddr);
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char *term = (char *)memchr(dmaaddr, 0, AlphaISA::PageBytes);
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len = term ? (term - dmaaddr + 1) : AlphaISA::PageBytes;
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memcpy(dst, dmaaddr, len);
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if (term)
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return;
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maxlen -= AlphaISA::PageBytes;
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dst += AlphaISA::PageBytes;
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vaddr += AlphaISA::PageBytes;
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}
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if (maxlen > 0) {
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paddr = vtophys(xc, vaddr);
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dmaaddr = (char *)xc->physmem->dma_addr(paddr, maxlen);
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assert(dmaaddr);
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char *term = (char *)memchr(dmaaddr, 0, maxlen);
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len = term ? (term - dmaaddr + 1) : maxlen;
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memcpy(dst, dmaaddr, len);
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maxlen -= len;
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}
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if (maxlen == 0)
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dst[maxlen] = '\0';
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}
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