fbe3688de3
Add a regression tester to McPAT. Joel Hestness wrote these tests and Yasuko Eckert modified them to reflect the new McPAT interface and other changes the previous patch made.
64 lines
2.7 KiB
XML
64 lines
2.7 KiB
XML
<?xml version="1.0" ?>
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<component id="root" name="root">
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<component id="system" name="system" type="System">
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<param name="core_tech_node" value="40"/>
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<param name="target_core_clockrate" value="1700"/>
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<param name="temperature" value="380"/>
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<param name="interconnect_projection_type" value="1"/>
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<param name="device_type" value="0"/>
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<param name="longer_channel_device" value="0"/>
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<param name="machine_bits" value="64"/>
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<param name="virtual_address_width" value="64"/>
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<param name="physical_address_width" value="36"/>
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<param name="virtual_memory_page_size" value="4096"/>
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<param name="wire_is_mat_type" value="2"/>
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<param name="wire_os_mat_type" value="2"/>
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<param name="delay_wt" value="100"/>
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<param name="area_wt" value="0"/>
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<param name="dynamic_power_wt" value="100"/>
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<param name="leakage_power_wt" value="0"/>
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<param name="cycle_time_wt" value="0"/>
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<param name="delay_dev" value="10000"/>
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<param name="area_dev" value="10000"/>
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<param name="dynamic_power_dev" value="10000"/>
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<param name="leakage_power_dev" value="10000"/>
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<param name="cycle_time_dev" value="10000"/>
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<param name="ed" value="2"/>
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<param name="burst_len" value="1"/>
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<param name="int_prefetch_w" value="1"/>
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<param name="page_sz_bits" value="0"/>
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<param name="rpters_in_htree" value="1"/>
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<param name="ver_htree_wires_over_array" value="0"/>
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<param name="nuca" value="0"/>
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<param name="nuca_bank_count" value="0"/>
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<param name="force_cache_config" value="0"/>
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<param name="wt" value="0"/>
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<param name="force_wiretype" value="0"/>
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<param name="print_detail" value="1"/>
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<param name="add_ecc_b_" value="1"/>
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<stat name="total_cycles" value="15"/>
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<component id="system.tol2bus" name="bus" type="BusInterconnect">
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<param name="clockrate" value="1700"/>
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<param name="link_throughput" value="1"/>
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<param name="link_latency" value="1"/>
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<param name="total_nodes" value="2"/>
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<param name="input_ports" value="2"/>
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<param name="output_ports" value="2"/>
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<param name="global_linked_ports" value="1"/>
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<param name="flit_bits" value="256"/>
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<param name="chip_coverage" value="1"/>
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<param name="pipelinable" value="1"/>
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<param name="link_routing_over_percentage" value="0.5"/>
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<param name="virtual_channel_per_port" value="1"/>
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<param name="M_traffic_pattern" value="1"/>
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<param name="link_len" value="1"/>
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<param name="link_base_width" value="1"/>
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<param name="link_base_height" value="1"/>
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<param name="link_start_wiring_level" value="3"/>
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<param name="wire_mat_type" value="2"/>
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<param name="wire_type" value="0"/>
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<stat name="total_accesses" value="5"/>
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<stat name="duty_cycle" value="1"/>
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</component>
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</component>
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</component>
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