Andreas Sandberg 3db3f83a5e arch: Make the ISA class inherit from SimObject ... The ISA class on stores the contents of ID registers on many architectures. In order to make reset values of such registers configurable, we make the class inherit from SimObject, which allows us to use the normal generated parameter headers. This patch introduces a Python helper method, BaseCPU.createThreads(), which creates a set of ISAs for each of the threads in an SMT system. Although it is currently only needed when creating multi-threaded CPUs, it should always be called before instantiating the system as this is an obvious place to configure ID registers identifying a thread/CPU.		2013-01-07 13:05:35 -05:00
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fs.py	arch: Make the ISA class inherit from SimObject	2013-01-07 13:05:35 -05:00
memtest.py	Configs: Fix memtest cache latency to match new parameters	2012-09-27 08:59:25 -04:00
ruby_direct_test.py	ruby: modify the directed tester to read/write streams	2012-12-11 10:05:55 -06:00
ruby_fs.py	arch: Make the ISA class inherit from SimObject	2013-01-07 13:05:35 -05:00
ruby_mem_test.py	ruby: improved support for functional accesses	2012-10-15 17:51:57 -05:00
ruby_network_test.py	ruby: changes how Topologies are created	2012-07-10 22:51:53 -07:00
ruby_random_test.py	ruby: remove the cpu assumptions for the random tester	2012-07-10 22:51:54 -07:00
se.py	arch: Make the ISA class inherit from SimObject	2013-01-07 13:05:35 -05:00