20e9a90edc
which I need to update the misc. regfile accesses
arch/mips/faults.cc:
arch/mips/faults.hh:
alpha to mips
arch/mips/isa/base.isa:
add includes
arch/mips/isa/bitfields.isa:
more bitfields
arch/mips/isa/decoder.isa:
lots o' lots o' lots o' changes!!!!
arch/mips/isa/formats.isa:
include cop0.isa
arch/mips/isa/formats/basic.isa:
fix faults
arch/mips/isa/formats/branch.isa:
arch/mips/isa/formats/fp.isa:
arch/mips/isa/formats/int.isa:
arch/mips/isa/formats/mem.isa:
arch/mips/isa/formats/noop.isa:
arch/mips/isa/formats/trap.isa:
arch/mips/isa/formats/unimp.isa:
arch/mips/isa/formats/unknown.isa:
arch/mips/isa/formats/util.isa:
arch/mips/isa/operands.isa:
arch/mips/isa_traits.cc:
arch/mips/linux_process.cc:
merge MIPS-specific comilable/buidable files code into multiarch
arch/mips/isa_traits.hh:
merge MIPS-specific comilable/buidable files code into multiarch... the miscRegs file accesses i have
need to be recoded and everything should build then ...
arch/mips/stacktrace.hh:
file copied over
--HG--
extra : convert_revision : 4a72e14fc5fb0a0d1f8b205dadbbf69636b7fb1f
67 lines
1.5 KiB
C++
67 lines
1.5 KiB
C++
// -*- mode:c++ -*-
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////////////////////////////////////////////////////////////////////
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//
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// Bitfield definitions.
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//
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def bitfield OPCODE <31:26>;
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def bitfield OPCODE_HI <31:29>;
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def bitfield OPCODE_LO <28:26>;
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def bitfield REGIMM <20:16>;
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def bitfield REGIMM_HI <20:19>;
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def bitfield REGIMM_LO <18:16>;
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def bitfield FUNCTION < 5: 0>;
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def bitfield FUNCTION_HI < 5: 3>;
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def bitfield FUNCTION_LO < 2: 0>;
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// Integer operate format
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def bitfield RT <20:16>;
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def bitfield RT_HI <20:19>;
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def bitfield RT_LO <18:16>;
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def bitfield RS <25:21>;
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def bitfield RS_MSB <25:25>;
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def bitfield RS_HI <25:24>;
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def bitfield RS_LO <23:21>;
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def bitfield RD <15:11>;
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def bitfield INTIMM <15: 0>; // integer immediate (literal)
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// Floating-point operate format
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def bitfield FMT <25:21>;
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def bitfield FR <25:21>;
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def bitfield FT <20:16>;
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def bitfield FS <15:11>;
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def bitfield FD <10:6>;
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def bitfield CC <20:18>;
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def bitfield ND <17:17>;
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def bitfield TF <16:16>;
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def bitfield MOVCI <16:16>;
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def bitfield MOVCF <16:16>;
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def bitfield SRL <21:21>;
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def bitfield SRLV < 6: 6>;
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def bitfield SA <10: 6>;
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// CP0 Register Select
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def bitfield SEL < 2: 0>;
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// Interrupts
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def bitfield SC < 5: 5>;
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// Branch format
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def bitfield OFFSET <15: 0>; // displacement
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// Jmp format
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def bitfield JMPTARG <25: 0>;
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def bitfield HINT <10: 6>;
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def bitfield SYSCALLCODE <25: 6>;
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def bitfield TRAPCODE <15:13>;
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// M5 instructions
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def bitfield M5FUNC <7:0>;
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