e7825aab59
The shadow registers are folded into the normal integer registers to ease renaming indexing.
Include the removed Opcdec class of instructions for faulting when a pal mode only instruction is decoded in non-pal mode.
arch/alpha/ev5.cc:
Changes to automatically map the shadow registers if the instruction is in PAL mode.
arch/alpha/isa/branch.isa:
arch/alpha/isa/decoder.isa:
arch/alpha/isa/fp.isa:
arch/alpha/isa/int.isa:
arch/alpha/isa/mem.isa:
arch/alpha/isa/pal.isa:
arch/alpha/isa/unimp.isa:
Changes for automatically using the shadow registers. Now instructions must decode based on an ExtMachInst, which is a MachInst with any decode context information concatenated onto the higher order bits.
arch/alpha/isa/main.isa:
Changes for automatically using the shadow registers. Now instructions must decode based on an ExtMachInst, which is a MachInst with any decode context information concatenated onto the higher order bits.
The decoder (for Alpha) uses the 32nd bit in order to determine if the machine is in PAL mode. If it is, then it refers to the reg_redir table to determine the true index of the register it is using.
Also include the opcdec instruction definition.
arch/alpha/isa_traits.hh:
Define ExtMachInst type that is used by the static inst in order to decode the instruction, given the context of being in pal mode or not.
Redefine the number of Int registers, splitting it into NumIntArchRegs (32) and NumIntRegs (32 + 8 shadow registers).
Change the dependence tags to reflect the integer registers include the 8 shadow registers.
Define function to make an ExtMachInst. Currently it is somewhat specific to Alpha; in the future it must be decided to make this more generic and possibly slower, or leave it specific to each architecture and ifdef it within the CPU.
arch/isa_parser.py:
Have static insts decode on the ExtMachInst.
base/remote_gdb.cc:
Support the automatic remapping of shadow registers. Remote GDB must now look at the PC being read in order to tell if it should use the normal register indices or the shadow register indices.
cpu/o3/regfile.hh:
Comment out the pal registers; they are now a part of the integer registers.
cpu/simple/cpu.cc:
Create an ExtMachInst to decode on, based on the normal MachInst and the PC of the instructoin.
cpu/static_inst.hh:
Change from MachInst to ExtMachInst to support shadow register renaming.
--HG--
extra : convert_revision : 1d23eabf735e297068e1917445a6348e9f8c88d5
272 lines
9.1 KiB
C++
272 lines
9.1 KiB
C++
// -*- mode:c++ -*-
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// Copyright (c) 2003-2005 The Regents of The University of Michigan
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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output header {{
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/**
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* Base class for emulated call_pal calls (used only in
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* non-full-system mode).
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*/
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class EmulatedCallPal : public AlphaStaticInst
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{
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protected:
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/// Constructor.
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EmulatedCallPal(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass)
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: AlphaStaticInst(mnem, _machInst, __opClass)
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{
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}
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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}};
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output decoder {{
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std::string
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EmulatedCallPal::generateDisassembly(Addr pc,
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const SymbolTable *symtab) const
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{
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#ifdef SS_COMPATIBLE_DISASSEMBLY
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return csprintf("%s %s", "call_pal", mnemonic);
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#else
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return csprintf("%-10s %s", "call_pal", mnemonic);
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#endif
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}
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}};
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def format EmulatedCallPal(code, *flags) {{
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iop = InstObjParams(name, Name, 'EmulatedCallPal', CodeBlock(code), flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = BasicDecode.subst(iop)
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exec_output = BasicExecute.subst(iop)
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}};
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output header {{
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/**
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* Base class for full-system-mode call_pal instructions.
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* Probably could turn this into a leaf class and get rid of the
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* parser template.
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*/
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class CallPalBase : public AlphaStaticInst
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{
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protected:
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int palFunc; ///< Function code part of instruction
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int palOffset; ///< Target PC, offset from IPR_PAL_BASE
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bool palValid; ///< is the function code valid?
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bool palPriv; ///< is this call privileged?
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/// Constructor.
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CallPalBase(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass);
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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}};
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output decoder {{
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inline
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CallPalBase::CallPalBase(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass)
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: AlphaStaticInst(mnem, _machInst, __opClass),
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palFunc(PALFUNC)
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{
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// From the 21164 HRM (paraphrased):
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// Bit 7 of the function code (mask 0x80) indicates
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// whether the call is privileged (bit 7 == 0) or
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// unprivileged (bit 7 == 1). The privileged call table
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// starts at 0x2000, the unprivielged call table starts at
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// 0x3000. Bits 5-0 (mask 0x3f) are used to calculate the
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// offset.
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const int palPrivMask = 0x80;
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const int palOffsetMask = 0x3f;
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// Pal call is invalid unless all other bits are 0
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palValid = ((machInst & ~(palPrivMask | palOffsetMask)) == 0);
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palPriv = ((machInst & palPrivMask) == 0);
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int shortPalFunc = (machInst & palOffsetMask);
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// Add 1 to base to set pal-mode bit
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palOffset = (palPriv ? 0x2001 : 0x3001) + (shortPalFunc << 6);
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}
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std::string
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CallPalBase::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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return csprintf("%-10s %#x", "call_pal", palFunc);
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}
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}};
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def format CallPal(code, *flags) {{
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iop = InstObjParams(name, Name, 'CallPalBase', CodeBlock(code), flags)
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = BasicDecode.subst(iop)
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exec_output = BasicExecute.subst(iop)
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}};
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////////////////////////////////////////////////////////////////////
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//
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// hw_ld, hw_st
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//
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output header {{
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/**
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* Base class for hw_ld and hw_st.
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*/
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class HwLoadStore : public Memory
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{
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protected:
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/// Displacement for EA calculation (signed).
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int16_t disp;
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/// Constructor
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HwLoadStore(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
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StaticInstPtr _eaCompPtr = nullStaticInstPtr,
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StaticInstPtr _memAccPtr = nullStaticInstPtr);
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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}};
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output decoder {{
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inline
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HwLoadStore::HwLoadStore(const char *mnem, ExtMachInst _machInst,
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OpClass __opClass,
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StaticInstPtr _eaCompPtr,
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StaticInstPtr _memAccPtr)
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: Memory(mnem, _machInst, __opClass, _eaCompPtr, _memAccPtr),
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disp(HW_LDST_DISP)
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{
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memAccessFlags = 0;
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if (HW_LDST_PHYS) memAccessFlags |= PHYSICAL;
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if (HW_LDST_ALT) memAccessFlags |= ALTMODE;
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if (HW_LDST_VPTE) memAccessFlags |= VPTE;
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if (HW_LDST_LOCK) memAccessFlags |= LOCKED;
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}
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std::string
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HwLoadStore::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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#ifdef SS_COMPATIBLE_DISASSEMBLY
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return csprintf("%-10s r%d,%d(r%d)", mnemonic, RA, disp, RB);
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#else
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// HW_LDST_LOCK and HW_LDST_COND are the same bit.
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const char *lock_str =
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(HW_LDST_LOCK) ? (flags[IsLoad] ? ",LOCK" : ",COND") : "";
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return csprintf("%-10s r%d,%d(r%d)%s%s%s%s%s",
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mnemonic, RA, disp, RB,
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HW_LDST_PHYS ? ",PHYS" : "",
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HW_LDST_ALT ? ",ALT" : "",
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HW_LDST_QUAD ? ",QUAD" : "",
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HW_LDST_VPTE ? ",VPTE" : "",
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lock_str);
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#endif
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}
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}};
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def format HwLoad(ea_code, memacc_code, class_ext, *flags) {{
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(header_output, decoder_output, decode_block, exec_output) = \
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LoadStoreBase(name, Name + class_ext, ea_code, memacc_code,
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mem_flags = [], inst_flags = flags,
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base_class = 'HwLoadStore', exec_template_base = 'Load')
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}};
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def format HwStore(ea_code, memacc_code, class_ext, *flags) {{
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(header_output, decoder_output, decode_block, exec_output) = \
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LoadStoreBase(name, Name + class_ext, ea_code, memacc_code,
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mem_flags = [], inst_flags = flags,
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base_class = 'HwLoadStore', exec_template_base = 'Store')
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}};
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def format HwStoreCond(ea_code, memacc_code, postacc_code, class_ext,
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*flags) {{
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(header_output, decoder_output, decode_block, exec_output) = \
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LoadStoreBase(name, Name + class_ext, ea_code, memacc_code,
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postacc_code, mem_flags = [], inst_flags = flags,
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base_class = 'HwLoadStore')
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}};
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output header {{
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/**
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* Base class for hw_mfpr and hw_mtpr.
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*/
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class HwMoveIPR : public AlphaStaticInst
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{
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protected:
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/// Index of internal processor register.
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int ipr_index;
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/// Constructor
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HwMoveIPR(const char *mnem, ExtMachInst _machInst, OpClass __opClass)
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: AlphaStaticInst(mnem, _machInst, __opClass),
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ipr_index(HW_IPR_IDX)
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{
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}
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std::string
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generateDisassembly(Addr pc, const SymbolTable *symtab) const;
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};
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}};
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output decoder {{
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std::string
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HwMoveIPR::generateDisassembly(Addr pc, const SymbolTable *symtab) const
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{
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if (_numSrcRegs > 0) {
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// must be mtpr
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return csprintf("%-10s r%d,IPR(%#x)",
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mnemonic, RA, ipr_index);
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}
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else {
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// must be mfpr
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return csprintf("%-10s IPR(%#x),r%d",
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mnemonic, ipr_index, RA);
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}
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}
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}};
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def format HwMoveIPR(code) {{
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iop = InstObjParams(name, Name, 'HwMoveIPR', CodeBlock(code),
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['IprAccessOp'])
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header_output = BasicDeclare.subst(iop)
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decoder_output = BasicConstructor.subst(iop)
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decode_block = BasicDecode.subst(iop)
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exec_output = BasicExecute.subst(iop)
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}};
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