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cache
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mem: Add checks and explanation for assertMemInhibit usage
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2014-12-02 06:07:46 -05:00 |
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protocol
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ruby: interface with classic memory controller
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2014-11-06 05:42:21 -06:00 |
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ruby
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mem: Add const getters for write packet data
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2014-12-02 06:07:36 -05:00 |
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slicc
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ruby: interface with classic memory controller
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2014-11-06 05:42:21 -06:00 |
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abstract_mem.cc
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mem: Add const getters for write packet data
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2014-12-02 06:07:36 -05:00 |
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abstract_mem.hh
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mem: Dynamically determine page bytes in memory components
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2014-10-16 05:49:43 -04:00 |
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AbstractMemory.py
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mem: Change AbstractMemory defaults to match the common case
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2013-08-19 03:52:33 -04:00 |
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addr_mapper.cc
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mem: Set the cache line size on a system level
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2013-07-18 08:31:16 -04:00 |
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addr_mapper.hh
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mem: Set the cache line size on a system level
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2013-07-18 08:31:16 -04:00 |
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AddrMapper.py
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sim: Include object header files in SWIG interfaces
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2012-11-02 11:32:01 -05:00 |
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bridge.cc
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mem: Rename Bus to XBar to better reflect its behaviour
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2014-09-20 17:18:32 -04:00 |
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bridge.hh
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mem: Rename Bus to XBar to better reflect its behaviour
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2014-09-20 17:18:32 -04:00 |
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Bridge.py
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mem: Tidy up the bridge with const and additional checks
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2013-06-27 05:49:49 -04:00 |
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coherent_xbar.cc
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mem: Rename Bus to XBar to better reflect its behaviour
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2014-09-20 17:18:32 -04:00 |
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coherent_xbar.hh
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mem: Rename Bus to XBar to better reflect its behaviour
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2014-09-20 17:18:32 -04:00 |
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comm_monitor.cc
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misc: Fix a bunch of minor issues identified by static analysis
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2014-09-27 09:08:29 -04:00 |
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comm_monitor.hh
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misc: Fix a bunch of minor issues identified by static analysis
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2014-09-27 09:08:29 -04:00 |
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CommMonitor.py
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mem: Auto-generate CommMonitor trace file names
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2014-05-09 18:58:46 -04:00 |
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dram_ctrl.cc
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mem: Add a GDDR5 DRAM config
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2014-12-02 06:07:32 -05:00 |
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dram_ctrl.hh
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mem: Add DRAM device size and check against config
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2014-10-20 18:03:52 -04:00 |
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DRAMCtrl.py
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mem: Add a GDDR5 DRAM config
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2014-12-02 06:07:32 -05:00 |
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drampower.cc
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mem: Add a GDDR5 DRAM config
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2014-12-02 06:07:32 -05:00 |
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drampower.hh
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mem: Add DRAMPower wrapping class
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2014-07-29 17:29:36 +01:00 |
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dramsim2.cc
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mem: Dynamically determine page bytes in memory components
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2014-10-16 05:49:43 -04:00 |
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dramsim2.hh
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mem: Fix DRAMSim2 cycle check when restoring from checkpoint
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2014-08-26 10:14:38 -04:00 |
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DRAMSim2.py
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mem: Add a wrapped DRAMSim2 memory controller
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2014-02-18 05:50:53 -05:00 |
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dramsim2_wrapper.cc
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mem: Add a wrapped DRAMSim2 memory controller
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2014-02-18 05:50:53 -05:00 |
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dramsim2_wrapper.hh
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mem: Add a wrapped DRAMSim2 memory controller
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2014-02-18 05:50:53 -05:00 |
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external_master.cc
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mem: Add ExternalMaster and ExternalSlave ports
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2014-10-16 05:49:56 -04:00 |
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external_master.hh
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mem: Add ExternalMaster and ExternalSlave ports
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2014-10-16 05:49:56 -04:00 |
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external_slave.cc
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mem: Add const getters for write packet data
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2014-12-02 06:07:36 -05:00 |
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external_slave.hh
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mem: Add ExternalMaster and ExternalSlave ports
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2014-10-16 05:49:56 -04:00 |
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ExternalMaster.py
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mem: Add ExternalMaster and ExternalSlave ports
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2014-10-16 05:49:56 -04:00 |
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ExternalSlave.py
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mem: Add ExternalMaster and ExternalSlave ports
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2014-10-16 05:49:56 -04:00 |
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fs_translating_port_proxy.cc
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mem: Use const pointers for port proxy write functions
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2014-12-02 06:07:38 -05:00 |
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fs_translating_port_proxy.hh
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mem: Use const pointers for port proxy write functions
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2014-12-02 06:07:38 -05:00 |
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mem_object.cc
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Port: Add protocol-agnostic ports in the port hierarchy
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2012-10-15 08:12:35 -04:00 |
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mem_object.hh
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Port: Add protocol-agnostic ports in the port hierarchy
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2012-10-15 08:12:35 -04:00 |
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MemObject.py
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sim: Include object header files in SWIG interfaces
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2012-11-02 11:32:01 -05:00 |
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mport.cc
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MEM: Separate snoops and normal memory requests/responses
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2012-04-14 05:45:07 -04:00 |
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mport.hh
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MEM: Separate requests and responses for timing accesses
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2012-05-01 13:40:42 -04:00 |
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multi_level_page_table.cc
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mem: adding a multi-level page table class
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2014-04-01 12:18:12 -05:00 |
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multi_level_page_table.hh
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mem: Page Table map api modification
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2014-11-23 18:01:09 -08:00 |
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multi_level_page_table_impl.hh
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mem: Page Table map api modification
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2014-11-23 18:01:09 -08:00 |
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noncoherent_xbar.cc
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mem: Rename Bus to XBar to better reflect its behaviour
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2014-09-20 17:18:32 -04:00 |
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noncoherent_xbar.hh
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mem: Rename Bus to XBar to better reflect its behaviour
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2014-09-20 17:18:32 -04:00 |
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packet.cc
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mem: Remove redundant Packet::allocate calls
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2014-12-02 06:07:41 -05:00 |
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packet.hh
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mem: Add checks and explanation for assertMemInhibit usage
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2014-12-02 06:07:46 -05:00 |
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packet_access.hh
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mem: Add const getters for write packet data
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2014-12-02 06:07:36 -05:00 |
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packet_queue.cc
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mem: Allow packet queue to move next send event forward
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2014-10-09 17:51:52 -04:00 |
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packet_queue.hh
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mem: Packet queue clean up
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2014-09-03 07:42:28 -04:00 |
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page_table.cc
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mem: Page Table map api modification
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2014-11-23 18:01:09 -08:00 |
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page_table.hh
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mem: Page Table map api modification
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2014-11-23 18:01:09 -08:00 |
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physical.cc
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mem: Modernise PhysicalMemory with C++11 features
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2014-10-16 05:50:01 -04:00 |
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physical.hh
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mem: Modernise PhysicalMemory with C++11 features
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2014-10-16 05:50:01 -04:00 |
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port.cc
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mem: Set the cache line size on a system level
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2013-07-18 08:31:16 -04:00 |
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port.hh
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misc: Move AddrRangeList from port.hh to addr_range.hh
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2014-10-16 05:49:59 -04:00 |
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port_proxy.cc
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mem: Use const pointers for port proxy write functions
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2014-12-02 06:07:38 -05:00 |
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port_proxy.hh
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mem: Use const pointers for port proxy write functions
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2014-12-02 06:07:38 -05:00 |
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qport.hh
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ruby: Simplify RubyPort flow control and routing
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2014-02-23 19:16:16 -06:00 |
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request.hh
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mem: Add accessor function for vaddr
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2014-09-09 04:36:33 -04:00 |
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SConscript
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mem: Add ExternalMaster and ExternalSlave ports
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2014-10-16 05:49:56 -04:00 |
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se_translating_port_proxy.cc
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mem: Use const pointers for port proxy write functions
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2014-12-02 06:07:38 -05:00 |
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se_translating_port_proxy.hh
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mem: Use const pointers for port proxy write functions
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2014-12-02 06:07:38 -05:00 |
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simple_mem.cc
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arm, mem: Fix drain bug and provide drain prints for more components.
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2014-10-29 23:18:26 -05:00 |
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simple_mem.hh
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mem: Add an internal packet queue in SimpleMemory
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2013-08-19 03:52:25 -04:00 |
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SimpleMemory.py
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mem: Add an internal packet queue in SimpleMemory
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2013-08-19 03:52:25 -04:00 |
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snoop_filter.cc
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mem: Add access statistics for the snoop filter
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2014-04-25 12:36:16 +01:00 |
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snoop_filter.hh
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mem: Add access statistics for the snoop filter
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2014-04-25 12:36:16 +01:00 |
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tport.cc
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mem: Replace check with panic where inhibited should not happen
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2013-04-22 13:20:33 -04:00 |
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tport.hh
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Port: Hide the queue implementation in SimpleTimingPort
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2012-07-09 12:35:42 -04:00 |
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xbar.cc
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mem: Output precise range when XBar has conflicts
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2014-09-27 09:08:32 -04:00 |
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xbar.hh
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mem: Rename Bus to XBar to better reflect its behaviour
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2014-09-20 17:18:32 -04:00 |
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XBar.py
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mem: Rename Bus to XBar to better reflect its behaviour
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2014-09-20 17:18:32 -04:00 |
