3ece6ab029
wierd ini files. The ini files are still used as an intermediate step,
but a sophisticated python library exists to help build them more
easily.
SConscript:
add the new embedded file stuff
remove all of the old object description junk
base/inifile.cc:
base/inifile.hh:
get rid of findDefault and findAppend since they were the source
of much evil.
base/trace.cc:
For now, if we don't have the dprintf_stream set up, dump
to standard out. We probably want a command line option
for this.
dev/alpha_console.cc:
PioDevice now takes a platform parameter.
All PioDevices must have a pio_latency parameter. We stick
a dummy parameter in here for now until we get rid of the
builder stuff.
dev/alpha_console.hh:
don't need Platform anymore
dev/baddev.cc:
PioDevice now takes a platform parameter.
All PioDevices must have a pio_latency parameter. We stick
a dummy parameter in here for now until we get rid of the
builder stuff. Same for the platform parameter, though we just
pass the PioDevice a null parameter since it isn't used by
this device and it's quicker.
dev/baddev.hh:
fix #include guards
dev/etherlink.cc:
rename parameters.
dev/ethertap.cc:
rename parameters
dev/ide_ctrl.cc:
All devices need an address even if it will get overwritten later.
dev/ide_disk.cc:
use an enum for the drive ID stuff.
rename disk_delay -> delay
Actually, I think that we should implement "cable select" and
have the controller tell the drive what it is.
dev/io_device.cc:
dev/io_device.hh:
All IO devices take a Platform *
dev/ns_gige.cc:
all devices need an io_bus. rename header_bus to io_bus
We don't need stuff for the interrupt controller since
it's all in the platform now.
dev/ns_gige.hh:
We don't need stuff for the interrupt controller now since
it's all in the platform.
dev/pciconfigall.cc:
Pass a dummy NULL to the PioDevice for the platform since
we don't need one.
dev/pcidev.cc:
Move a bunch of common functionality into the PciDev
dev/platform.hh:
remove unneeded code
dev/tsunami.cc:
remove unused param
dev/tsunami_cchip.cc:
pass platform pointer
dev/tsunami_io.cc:
dev/tsunami_pchip.cc:
dev/uart.cc:
pass platform variable
dev/uart.hh:
don't need to keep a platform pointer. it's in the base class
kern/linux/linux_system.cc:
kern/tru64/tru64_system.cc:
rename some parameters
sim/builder.cc:
clean up builder code. use more parameters from the
config node. all sections with a type= are now created,
the old mechanisms no longer work
sim/builder.hh:
remove some extra variables since they are found in the ConfigNode
sim/main.cc:
add a quick hack command line argument -X to dump out the
embedded files. (probably should be fixed up a little.)
accept .mpy files
printing to the streams has to happen after the hierarchy
is built since we're moving away from param contexts
sim/param.cc:
add parsing support for ranges
sim/process.cc:
isValid isn't very useful anymore. interpret the names
stdout, stderr, cout, cerr for the file descriptors
sim/pyconfig/SConscript:
Add Action handlers for creating an embedded python file
and for creating an embedded C file.
use these action handlers to embed all objects found in the objects
tree into the binary along with the importer and the m5config stuff
sim/pyconfig/m5config.py:
Major changes to the original configuration file generator. These
changes largely involve implementing copy-on-write like semantics
for all of the SimObjects. Real documentation must be written.
sim/universe.cc:
Universe becomes a SimObject since we don't really have the notion of
param contexts in the python code.
--HG--
rename : sim/pyconfig/m5configbase.py => sim/pyconfig/m5config.py
extra : convert_revision : c353453e5beb91c37f15755998fc0d8858c6829a
386 lines
13 KiB
C++
386 lines
13 KiB
C++
/*
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* Copyright (c) 2004 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* @file
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* Tsunami PChip (pci)
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*/
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#include <deque>
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#include <string>
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#include <vector>
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#include "base/trace.hh"
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#include "dev/tsunami_pchip.hh"
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#include "dev/tsunamireg.h"
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#include "dev/tsunami.hh"
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#include "mem/bus/bus.hh"
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#include "mem/bus/pio_interface.hh"
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#include "mem/bus/pio_interface_impl.hh"
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#include "mem/functional_mem/memory_control.hh"
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#include "mem/functional_mem/physical_memory.hh"
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#include "sim/builder.hh"
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#include "sim/system.hh"
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using namespace std;
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TsunamiPChip::TsunamiPChip(const string &name, Tsunami *t, Addr a,
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MemoryController *mmu, HierParams *hier,
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Bus *bus, Tick pio_latency)
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: PioDevice(name, t), addr(a), tsunami(t)
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{
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mmu->add_child(this, RangeSize(addr, size));
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for (int i = 0; i < 4; i++) {
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wsba[i] = 0;
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wsm[i] = 0;
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tba[i] = 0;
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}
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if (bus) {
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pioInterface = newPioInterface(name, hier, bus, this,
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&TsunamiPChip::cacheAccess);
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pioInterface->addAddrRange(RangeSize(addr, size));
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pioLatency = pio_latency * bus->clockRatio;
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}
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// initialize pchip control register
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pctl = (ULL(0x1) << 20) | (ULL(0x1) << 32) | (ULL(0x2) << 36);
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//Set back pointer in tsunami
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tsunami->pchip = this;
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}
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Fault
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TsunamiPChip::read(MemReqPtr &req, uint8_t *data)
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{
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DPRINTF(Tsunami, "read va=%#x size=%d\n",
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req->vaddr, req->size);
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Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)) >> 6;
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switch (req->size) {
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case sizeof(uint64_t):
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switch(daddr) {
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case TSDEV_PC_WSBA0:
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*(uint64_t*)data = wsba[0];
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return No_Fault;
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case TSDEV_PC_WSBA1:
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*(uint64_t*)data = wsba[1];
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return No_Fault;
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case TSDEV_PC_WSBA2:
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*(uint64_t*)data = wsba[2];
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return No_Fault;
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case TSDEV_PC_WSBA3:
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*(uint64_t*)data = wsba[3];
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return No_Fault;
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case TSDEV_PC_WSM0:
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*(uint64_t*)data = wsm[0];
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return No_Fault;
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case TSDEV_PC_WSM1:
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*(uint64_t*)data = wsm[1];
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return No_Fault;
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case TSDEV_PC_WSM2:
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*(uint64_t*)data = wsm[2];
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return No_Fault;
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case TSDEV_PC_WSM3:
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*(uint64_t*)data = wsm[3];
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return No_Fault;
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case TSDEV_PC_TBA0:
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*(uint64_t*)data = tba[0];
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return No_Fault;
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case TSDEV_PC_TBA1:
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*(uint64_t*)data = tba[1];
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return No_Fault;
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case TSDEV_PC_TBA2:
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*(uint64_t*)data = tba[2];
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return No_Fault;
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case TSDEV_PC_TBA3:
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*(uint64_t*)data = tba[3];
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return No_Fault;
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case TSDEV_PC_PCTL:
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*(uint64_t*)data = pctl;
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return No_Fault;
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case TSDEV_PC_PLAT:
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panic("PC_PLAT not implemented\n");
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case TSDEV_PC_RES:
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panic("PC_RES not implemented\n");
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case TSDEV_PC_PERROR:
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*(uint64_t*)data = 0x00;
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return No_Fault;
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case TSDEV_PC_PERRMASK:
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*(uint64_t*)data = 0x00;
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return No_Fault;
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case TSDEV_PC_PERRSET:
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panic("PC_PERRSET not implemented\n");
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case TSDEV_PC_TLBIV:
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panic("PC_TLBIV not implemented\n");
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case TSDEV_PC_TLBIA:
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*(uint64_t*)data = 0x00; // shouldn't be readable, but linux
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return No_Fault;
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case TSDEV_PC_PMONCTL:
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panic("PC_PMONCTL not implemented\n");
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case TSDEV_PC_PMONCNT:
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panic("PC_PMONCTN not implemented\n");
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default:
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panic("Default in PChip Read reached reading 0x%x\n", daddr);
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} // uint64_t
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break;
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case sizeof(uint32_t):
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case sizeof(uint16_t):
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case sizeof(uint8_t):
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default:
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panic("invalid access size(?) for tsunami register!\n\n");
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}
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DPRINTFN("Tsunami PChip ERROR: read daddr=%#x size=%d\n", daddr, req->size);
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return No_Fault;
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}
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Fault
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TsunamiPChip::write(MemReqPtr &req, const uint8_t *data)
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{
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DPRINTF(Tsunami, "write - va=%#x size=%d \n",
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req->vaddr, req->size);
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Addr daddr = (req->paddr - (addr & EV5::PAddrImplMask)) >> 6;
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switch (req->size) {
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case sizeof(uint64_t):
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switch(daddr) {
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case TSDEV_PC_WSBA0:
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wsba[0] = *(uint64_t*)data;
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return No_Fault;
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case TSDEV_PC_WSBA1:
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wsba[1] = *(uint64_t*)data;
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return No_Fault;
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case TSDEV_PC_WSBA2:
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wsba[2] = *(uint64_t*)data;
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return No_Fault;
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case TSDEV_PC_WSBA3:
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wsba[3] = *(uint64_t*)data;
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return No_Fault;
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case TSDEV_PC_WSM0:
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wsm[0] = *(uint64_t*)data;
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return No_Fault;
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case TSDEV_PC_WSM1:
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wsm[1] = *(uint64_t*)data;
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return No_Fault;
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case TSDEV_PC_WSM2:
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wsm[2] = *(uint64_t*)data;
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return No_Fault;
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case TSDEV_PC_WSM3:
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wsm[3] = *(uint64_t*)data;
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return No_Fault;
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case TSDEV_PC_TBA0:
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tba[0] = *(uint64_t*)data;
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return No_Fault;
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case TSDEV_PC_TBA1:
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tba[1] = *(uint64_t*)data;
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return No_Fault;
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case TSDEV_PC_TBA2:
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tba[2] = *(uint64_t*)data;
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return No_Fault;
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case TSDEV_PC_TBA3:
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tba[3] = *(uint64_t*)data;
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return No_Fault;
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case TSDEV_PC_PCTL:
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pctl = *(uint64_t*)data;
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return No_Fault;
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case TSDEV_PC_PLAT:
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panic("PC_PLAT not implemented\n");
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case TSDEV_PC_RES:
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panic("PC_RES not implemented\n");
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case TSDEV_PC_PERROR:
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return No_Fault;
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case TSDEV_PC_PERRMASK:
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panic("PC_PERRMASK not implemented\n");
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case TSDEV_PC_PERRSET:
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panic("PC_PERRSET not implemented\n");
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case TSDEV_PC_TLBIV:
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panic("PC_TLBIV not implemented\n");
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case TSDEV_PC_TLBIA:
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return No_Fault; // value ignored, supposted to invalidate SG TLB
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case TSDEV_PC_PMONCTL:
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panic("PC_PMONCTL not implemented\n");
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case TSDEV_PC_PMONCNT:
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panic("PC_PMONCTN not implemented\n");
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default:
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panic("Default in PChip Read reached reading 0x%x\n", daddr);
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} // uint64_t
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break;
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case sizeof(uint32_t):
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case sizeof(uint16_t):
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case sizeof(uint8_t):
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default:
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panic("invalid access size(?) for tsunami register!\n\n");
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}
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DPRINTFN("Tsunami ERROR: write daddr=%#x size=%d\n", daddr, req->size);
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return No_Fault;
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}
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#define DMA_ADDR_MASK ULL(0x3ffffffff)
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Addr
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TsunamiPChip::translatePciToDma(Addr busAddr)
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{
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// compare the address to the window base registers
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uint64_t tbaMask = 0;
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uint64_t baMask = 0;
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uint64_t windowMask = 0;
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uint64_t windowBase = 0;
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uint64_t pteEntry = 0;
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Addr pteAddr;
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Addr dmaAddr;
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#if 0
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DPRINTF(IdeDisk, "Translation for bus address: %#x\n", busAddr);
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for (int i = 0; i < 4; i++) {
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DPRINTF(IdeDisk, "(%d) base:%#x mask:%#x\n",
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i, wsba[i], wsm[i]);
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windowBase = wsba[i];
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windowMask = ~wsm[i] & (ULL(0xfff) << 20);
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if ((busAddr & windowMask) == (windowBase & windowMask)) {
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DPRINTF(IdeDisk, "Would have matched %d (wb:%#x wm:%#x --> ba&wm:%#x wb&wm:%#x)\n",
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i, windowBase, windowMask, (busAddr & windowMask),
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(windowBase & windowMask));
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}
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}
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#endif
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for (int i = 0; i < 4; i++) {
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windowBase = wsba[i];
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windowMask = ~wsm[i] & (ULL(0xfff) << 20);
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if ((busAddr & windowMask) == (windowBase & windowMask)) {
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if (wsba[i] & 0x1) { // see if enabled
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if (wsba[i] & 0x2) { // see if SG bit is set
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/** @todo
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This currently is faked by just doing a direct
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read from memory, however, to be realistic, this
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needs to actually do a bus transaction. The process
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is explained in the tsunami documentation on page
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10-12 and basically munges the address to look up a
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PTE from a table in memory and then uses that mapping
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to create an address for the SG page
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*/
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tbaMask = ~(((wsm[i] & (ULL(0xfff) << 20)) >> 10) | ULL(0x3ff));
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baMask = (wsm[i] & (ULL(0xfff) << 20)) | (ULL(0x7f) << 13);
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pteAddr = (tba[i] & tbaMask) | ((busAddr & baMask) >> 10);
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memcpy((void *)&pteEntry,
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tsunami->system->
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physmem->dma_addr(pteAddr, sizeof(uint64_t)),
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sizeof(uint64_t));
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dmaAddr = ((pteEntry & ~ULL(0x1)) << 12) | (busAddr & ULL(0x1fff));
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} else {
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baMask = (wsm[i] & (ULL(0xfff) << 20)) | ULL(0xfffff);
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tbaMask = ~baMask;
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dmaAddr = (tba[i] & tbaMask) | (busAddr & baMask);
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}
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return (dmaAddr & DMA_ADDR_MASK);
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}
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}
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}
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// if no match was found, then return the original address
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return busAddr;
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}
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void
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TsunamiPChip::serialize(std::ostream &os)
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{
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SERIALIZE_SCALAR(pctl);
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SERIALIZE_ARRAY(wsba, 4);
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SERIALIZE_ARRAY(wsm, 4);
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SERIALIZE_ARRAY(tba, 4);
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}
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void
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TsunamiPChip::unserialize(Checkpoint *cp, const std::string §ion)
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{
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UNSERIALIZE_SCALAR(pctl);
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UNSERIALIZE_ARRAY(wsba, 4);
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UNSERIALIZE_ARRAY(wsm, 4);
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UNSERIALIZE_ARRAY(tba, 4);
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}
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Tick
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TsunamiPChip::cacheAccess(MemReqPtr &req)
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{
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return curTick + pioLatency;
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}
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
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SimObjectParam<Tsunami *> tsunami;
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SimObjectParam<MemoryController *> mmu;
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Param<Addr> addr;
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SimObjectParam<Bus*> io_bus;
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Param<Tick> pio_latency;
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SimObjectParam<HierParams *> hier;
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END_DECLARE_SIM_OBJECT_PARAMS(TsunamiPChip)
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BEGIN_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
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INIT_PARAM(tsunami, "Tsunami"),
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INIT_PARAM(mmu, "Memory Controller"),
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INIT_PARAM(addr, "Device Address"),
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INIT_PARAM_DFLT(io_bus, "The IO Bus to attach to", NULL),
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INIT_PARAM_DFLT(pio_latency, "Programmed IO latency in bus cycles", 1),
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INIT_PARAM_DFLT(hier, "Hierarchy global variables", &defaultHierParams)
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END_INIT_SIM_OBJECT_PARAMS(TsunamiPChip)
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CREATE_SIM_OBJECT(TsunamiPChip)
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{
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return new TsunamiPChip(getInstanceName(), tsunami, addr, mmu, hier,
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io_bus, pio_latency);
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}
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REGISTER_SIM_OBJECT("TsunamiPChip", TsunamiPChip)
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