173 lines
6.5 KiB
C++
173 lines
6.5 KiB
C++
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/*
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* Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* $Id: Sequencer.h 1.70 2006/09/27 14:56:41-05:00 bobba@s1-01.cs.wisc.edu $
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*
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* Description:
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*
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*/
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#ifndef SEQUENCER_H
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#define SEQUENCER_H
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#include "Global.hh"
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#include "RubyConfig.hh"
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#include "Consumer.hh"
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#include "CacheRequestType.hh"
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#include "AccessModeType.hh"
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#include "GenericMachineType.hh"
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#include "PrefetchBit.hh"
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#include "Map.hh"
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#include "packet.hh"
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class DataBlock;
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class AbstractChip;
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class CacheMsg;
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class Address;
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class MachineID;
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class Sequencer : public Consumer {
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public:
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// Constructors
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Sequencer(AbstractChip* chip_ptr, int version);
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// Destructor
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~Sequencer();
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// Public Methods
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void wakeup(); // Used only for deadlock detection
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static void printConfig(ostream& out);
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// returns total number of outstanding request (includes prefetches)
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int getNumberOutstanding();
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// return only total number of outstanding demand requests
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int getNumberOutstandingDemand();
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// return only total number of outstanding prefetch requests
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int getNumberOutstandingPrefetch();
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// remove load/store request from queue
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void removeLoadRequest(const Address & addr, int thread);
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void removeStoreRequest(const Address & addr, int thread);
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void printProgress(ostream& out) const;
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// returns a pointer to the request in the request tables
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CacheMsg & getReadRequest( const Address & addr, int thread );
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CacheMsg & getWriteRequest( const Address & addr, int thread );
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// called by Ruby when transaction completes
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void writeConflictCallback(const Address& address);
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void readConflictCallback(const Address& address);
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void writeConflictCallback(const Address& address, GenericMachineType respondingMach, int thread);
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void readConflictCallback(const Address& address, GenericMachineType respondingMach, int thread);
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void writeCallback(const Address& address, DataBlock& data);
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void readCallback(const Address& address, DataBlock& data);
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void writeCallback(const Address& address);
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void readCallback(const Address& address);
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void writeCallback(const Address& address, DataBlock& data, GenericMachineType respondingMach, PrefetchBit pf, int thread);
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void readCallback(const Address& address, DataBlock& data, GenericMachineType respondingMach, PrefetchBit pf, int thread);
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void writeCallback(const Address& address, DataBlock& data, GenericMachineType respondingMach, int thread);
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void readCallback(const Address& address, DataBlock& data, GenericMachineType respondingMach, int thread);
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// returns the thread ID of the request
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int getRequestThreadID(const Address & addr);
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// returns the physical address of the request
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Address getRequestPhysicalAddress(const Address & lineaddr);
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// returns whether a request is a prefetch request
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bool isPrefetchRequest(const Address & lineaddr);
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//notifies driver of debug print
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void printDebug();
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// called by Tester or Simics
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void makeRequest(const Packet* pkt, void* data);
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void makeRequest(const CacheMsg& request); // depricate this function
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bool doRequest(const CacheMsg& request);
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void issueRequest(const CacheMsg& request);
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bool isReady(const Packet* pkt) const;
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bool isReady(const CacheMsg& request) const; // depricate this function
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bool empty() const;
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void resetRequestTime(const Address& addr, int thread);
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Address getLogicalAddressOfRequest(Address address, int thread);
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AccessModeType getAccessModeOfRequest(Address address, int thread);
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//uint64 getSequenceNumberOfRequest(Address addr, int thread);
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void print(ostream& out) const;
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void checkCoherence(const Address& address);
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bool getRubyMemoryValue(const Address& addr, char* value, unsigned int size_in_bytes);
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bool setRubyMemoryValue(const Address& addr, char *value, unsigned int size_in_bytes);
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void removeRequest(const CacheMsg& request);
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private:
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// Private Methods
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bool tryCacheAccess(const Address& addr, CacheRequestType type, const Address& pc, AccessModeType access_mode, int size, DataBlock*& data_ptr);
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void conflictCallback(const CacheMsg& request, GenericMachineType respondingMach, int thread);
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void hitCallback(const CacheMsg& request, DataBlock& data, GenericMachineType respondingMach, int thread);
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bool insertRequest(const CacheMsg& request);
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// Private copy constructor and assignment operator
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Sequencer(const Sequencer& obj);
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Sequencer& operator=(const Sequencer& obj);
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// Data Members (m_ prefix)
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AbstractChip* m_chip_ptr;
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// indicates what processor on the chip this sequencer is associated with
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int m_version;
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// One request table per SMT thread
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Map<Address, CacheMsg>** m_writeRequestTable_ptr;
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Map<Address, CacheMsg>** m_readRequestTable_ptr;
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// Global outstanding request count, across all request tables
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int m_outstanding_count;
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bool m_deadlock_check_scheduled;
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};
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// Output operator declaration
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ostream& operator<<(ostream& out, const Sequencer& obj);
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// ******************* Definitions *******************
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// Output operator definition
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extern inline
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ostream& operator<<(ostream& out, const Sequencer& obj)
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{
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obj.print(out);
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out << flush;
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return out;
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}
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#endif //SEQUENCER_H
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