sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity
gem5/tests/quick/fs/10.linux-boot/ref/arm/linux/realview-simple-timing/stats.txt
Andreas Hansson 74553c7d3f stats: Update the stats to reflect bus and memory changes 
This patch updates the stats to reflect the addition of the bus stats,
and changes to the bus layers. In addition it updates the stats to
match the addition of the static pipeline latency of the memory
conotroller and the addition of a stat tracking the bytes per
activate.
2013-05-30 12:54:18 -04:00

1290 lines
153 KiB
Text
Raw Blame History

---------- Begin Simulation Statistics ----------
sim_seconds 2.615622 # Number of seconds simulated
sim_ticks 2615622384000 # Number of ticks simulated
final_tick 2615622384000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 264818 # Simulator instruction rate (inst/s)
host_op_rate 336993 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 11506330329 # Simulator tick rate (ticks/s)
host_mem_usage 396436 # Number of bytes of host memory used
host_seconds 227.32 # Real time elapsed on the host
sim_insts 60198587 # Number of instructions simulated
sim_ops 76605405 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 122683392 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 320 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.inst 704800 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 9093200 # Number of bytes read from this memory
system.physmem.bytes_read::total 132481840 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 704800 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 704800 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3709760 # Number of bytes written to this memory
system.physmem.bytes_written::cpu.data 3016072 # Number of bytes written to this memory
system.physmem.bytes_written::total 6725832 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 15335424 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 5 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 2 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.inst 17215 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 142115 # Number of read requests responded to by this memory
system.physmem.num_reads::total 15494761 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 57965 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu.data 754018 # Number of write requests responded to by this memory
system.physmem.num_writes::total 811983 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 46904092 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 122 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 49 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.inst 269458 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3476496 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 50650216 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 269458 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 269458 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1418309 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu.data 1153099 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2571408 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1418309 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 46904092 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 122 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 49 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 269458 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 4629595 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 53221624 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 15494761 # Total number of read requests seen
system.physmem.writeReqs 811983 # Total number of write requests seen
system.physmem.cpureqs 215166 # Reqs generatd by CPU via cache - shady
system.physmem.bytesRead 991664704 # Total number of bytes read from memory
system.physmem.bytesWritten 51966912 # Total number of bytes written to memory
system.physmem.bytesConsumedRd 132481840 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 6725832 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 301 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 4516 # Reqs where no action is needed
system.physmem.perBankRdReqs::0 968108 # Track reads on a per bank basis
system.physmem.perBankRdReqs::1 967904 # Track reads on a per bank basis
system.physmem.perBankRdReqs::2 967765 # Track reads on a per bank basis
system.physmem.perBankRdReqs::3 967946 # Track reads on a per bank basis
system.physmem.perBankRdReqs::4 974722 # Track reads on a per bank basis
system.physmem.perBankRdReqs::5 968494 # Track reads on a per bank basis
system.physmem.perBankRdReqs::6 967971 # Track reads on a per bank basis
system.physmem.perBankRdReqs::7 967832 # Track reads on a per bank basis
system.physmem.perBankRdReqs::8 968523 # Track reads on a per bank basis
system.physmem.perBankRdReqs::9 968301 # Track reads on a per bank basis
system.physmem.perBankRdReqs::10 967958 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 967809 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 967930 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 967629 # Track reads on a per bank basis
system.physmem.perBankRdReqs::14 967885 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 967683 # Track reads on a per bank basis
system.physmem.perBankWrReqs::0 49152 # Track writes on a per bank basis
system.physmem.perBankWrReqs::1 49010 # Track writes on a per bank basis
system.physmem.perBankWrReqs::2 50853 # Track writes on a per bank basis
system.physmem.perBankWrReqs::3 50913 # Track writes on a per bank basis
system.physmem.perBankWrReqs::4 51127 # Track writes on a per bank basis
system.physmem.perBankWrReqs::5 51430 # Track writes on a per bank basis
system.physmem.perBankWrReqs::6 51157 # Track writes on a per bank basis
system.physmem.perBankWrReqs::7 51246 # Track writes on a per bank basis
system.physmem.perBankWrReqs::8 51368 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 51158 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 50878 # Track writes on a per bank basis
system.physmem.perBankWrReqs::11 50797 # Track writes on a per bank basis
system.physmem.perBankWrReqs::12 50871 # Track writes on a per bank basis
system.physmem.perBankWrReqs::13 50522 # Track writes on a per bank basis
system.physmem.perBankWrReqs::14 50825 # Track writes on a per bank basis
system.physmem.perBankWrReqs::15 50676 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
system.physmem.totGap 2615618000000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 6652 # Categorize read packet sizes
system.physmem.readPktSize::3 15335424 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 152685 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 754018 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 57965 # Categorize write packet sizes
system.physmem.rdQLenPdf::0 1126555 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 973164 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 1018253 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 3775658 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2831038 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2826406 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 2774250 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 21901 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 19136 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 31670 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 43534 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 30921 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 5697 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 5598 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 5455 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 5184 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 40 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 35284 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 35302 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 35303 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 35304 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 35304 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 35304 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 35304 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 35304 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 35304 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 35304 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 35304 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 35304 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 35304 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 35304 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 35303 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 35303 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 35303 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 35303 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 35303 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 35303 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 35303 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 35303 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 35303 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 20 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 2 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 38567 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 27059.676926 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 2495.376643 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 33105.439598 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-127 5489 14.23% 14.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-191 3331 8.64% 22.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-255 2176 5.64% 28.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-319 1697 4.40% 32.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-383 1162 3.01% 35.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-447 1046 2.71% 38.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-511 828 2.15% 40.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-575 748 1.94% 42.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-639 582 1.51% 44.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-703 509 1.32% 45.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-767 411 1.07% 46.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-831 479 1.24% 47.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-895 285 0.74% 48.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-959 248 0.64% 49.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-1023 187 0.48% 49.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1087 239 0.62% 50.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1151 141 0.37% 50.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1215 137 0.36% 51.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1279 106 0.27% 51.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1343 105 0.27% 51.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1407 92 0.24% 51.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1471 151 0.39% 52.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1535 970 2.52% 54.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1599 203 0.53% 55.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1663 135 0.35% 55.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1727 110 0.29% 55.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1791 91 0.24% 56.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1855 77 0.20% 56.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1919 66 0.17% 56.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1983 47 0.12% 56.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-2047 51 0.13% 56.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2111 64 0.17% 56.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2175 37 0.10% 57.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2239 25 0.06% 57.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2303 18 0.05% 57.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2367 25 0.06% 57.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2431 26 0.07% 57.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2495 13 0.03% 57.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2559 25 0.06% 57.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2623 11 0.03% 57.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2687 14 0.04% 57.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2751 8 0.02% 57.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2815 18 0.05% 57.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2879 9 0.02% 57.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2943 8 0.02% 57.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-3007 14 0.04% 57.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3071 7 0.02% 57.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3135 17 0.04% 57.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3199 7 0.02% 57.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3263 8 0.02% 57.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3327 12 0.03% 57.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3391 12 0.03% 57.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3455 3 0.01% 57.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3519 9 0.02% 57.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3583 3 0.01% 57.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3647 6 0.02% 57.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3711 12 0.03% 57.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3775 9 0.02% 57.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3839 7 0.02% 57.89% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3903 9 0.02% 57.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3967 4 0.01% 57.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-4031 6 0.02% 57.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4095 9 0.02% 57.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4159 44 0.11% 58.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4223 3 0.01% 58.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4287 2 0.01% 58.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4351 3 0.01% 58.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4415 5 0.01% 58.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4479 6 0.02% 58.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4543 2 0.01% 58.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4607 5 0.01% 58.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4671 2 0.01% 58.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4735 1 0.00% 58.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4799 1 0.00% 58.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4863 3 0.01% 58.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4927 7 0.02% 58.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-5055 6 0.02% 58.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5119 1 0.00% 58.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5183 12 0.03% 58.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5247 1 0.00% 58.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5311 5 0.01% 58.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5312-5375 3 0.01% 58.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5439 5 0.01% 58.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5503 7 0.02% 58.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5567 2 0.01% 58.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568-5631 2 0.01% 58.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5695 2 0.01% 58.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5696-5759 6 0.02% 58.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5824-5887 3 0.01% 58.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5951 2 0.01% 58.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5952-6015 3 0.01% 58.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6079 2 0.01% 58.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6143 2 0.01% 58.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6207 180 0.47% 58.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6271 1 0.00% 58.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6335 1 0.00% 58.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6336-6399 3 0.01% 58.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6463 5 0.01% 58.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6527 2 0.01% 58.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6591 3 0.01% 58.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6655 1 0.00% 58.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6719 2 0.01% 58.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6783 1 0.00% 58.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6847 15 0.04% 58.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6911 3 0.01% 58.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6975 1 0.00% 58.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6976-7039 2 0.01% 58.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7103 2 0.01% 58.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7231 4 0.01% 58.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7232-7295 3 0.01% 58.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7360-7423 1 0.00% 58.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7487 2 0.01% 58.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7488-7551 3 0.01% 58.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552-7615 3 0.01% 58.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7616-7679 3 0.01% 58.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7743 11 0.03% 59.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7744-7807 3 0.01% 59.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7808-7871 4 0.01% 59.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7872-7935 4 0.01% 59.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7999 3 0.01% 59.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8000-8063 1 0.00% 59.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8064-8127 6 0.02% 59.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8128-8191 4 0.01% 59.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8255 327 0.85% 59.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8448-8511 5 0.01% 59.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8832-8895 1 0.00% 59.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8960-9023 1 0.00% 59.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9216-9279 3 0.01% 59.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9472-9535 2 0.01% 59.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9728-9791 1 0.00% 59.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10240-10303 18 0.05% 59.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10496-10559 1 0.00% 59.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10752-10815 1 0.00% 60.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11200-11263 1 0.00% 60.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11264-11327 2 0.01% 60.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11520-11583 2 0.01% 60.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11584-11647 1 0.00% 60.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11776-11839 1 0.00% 60.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12032-12095 1 0.00% 60.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12288-12351 3 0.01% 60.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12544-12607 1 0.00% 60.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13056-13119 1 0.00% 60.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13568-13631 1 0.00% 60.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14080-14143 1 0.00% 60.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14336-14399 2 0.01% 60.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14592-14655 2 0.01% 60.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15360-15423 3 0.01% 60.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15680-15743 1 0.00% 60.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15872-15935 1 0.00% 60.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16128-16191 2 0.01% 60.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16384-16447 1 0.00% 60.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17408-17471 2 0.01% 60.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17664-17727 1 0.00% 60.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17920-17983 1 0.00% 60.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18176-18239 1 0.00% 60.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18432-18495 2 0.01% 60.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19008-19071 1 0.00% 60.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19200-19263 1 0.00% 60.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19456-19519 3 0.01% 60.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19712-19775 3 0.01% 60.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19968-20031 1 0.00% 60.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20224-20287 1 0.00% 60.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20480-20543 2 0.01% 60.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20736-20799 1 0.00% 60.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21248-21311 1 0.00% 60.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21504-21567 1 0.00% 60.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21760-21823 2 0.01% 60.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22528-22591 4 0.01% 60.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22784-22847 1 0.00% 60.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23040-23103 3 0.01% 60.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23296-23359 1 0.00% 60.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23552-23615 5 0.01% 60.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23808-23871 1 0.00% 60.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24064-24127 2 0.01% 60.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24576-24639 1 0.00% 60.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24832-24895 1 0.00% 60.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24960-25023 1 0.00% 60.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25600-25663 3 0.01% 60.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25856-25919 2 0.01% 60.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26368-26431 1 0.00% 60.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26624-26687 4 0.01% 60.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26880-26943 1 0.00% 60.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27136-27199 1 0.00% 60.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27904-27967 1 0.00% 60.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28096-28159 1 0.00% 60.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28672-28735 1 0.00% 60.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28928-28991 1 0.00% 60.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29376-29439 1 0.00% 60.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29696-29759 6 0.02% 60.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29952-30015 2 0.01% 60.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30464-30527 3 0.01% 60.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30720-30783 3 0.01% 60.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31168-31231 1 0.00% 60.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31232-31295 2 0.01% 60.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31744-31807 5 0.01% 60.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32000-32063 1 0.00% 60.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32768-32831 2 0.01% 60.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33280-33343 4 0.01% 60.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33536-33599 56 0.15% 60.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33600-33663 1 0.00% 60.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34048-34111 1 0.00% 60.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34816-34879 1 0.00% 60.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35840-35903 1 0.00% 60.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37376-37439 1 0.00% 60.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38912-38975 1 0.00% 60.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39936-39999 2 0.01% 60.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42240-42303 1 0.00% 60.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42496-42559 2 0.01% 60.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43008-43071 1 0.00% 60.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43520-43583 1 0.00% 60.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45056-45119 1 0.00% 60.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45568-45631 1 0.00% 60.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46080-46143 1 0.00% 60.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47360-47423 1 0.00% 60.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48128-48191 1 0.00% 60.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49152-49215 2 0.01% 60.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49664-49727 2 0.01% 60.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::50176-50239 1 0.00% 60.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::51200-51263 1 0.00% 60.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::52480-52543 1 0.00% 60.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::52992-53055 1 0.00% 60.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::56320-56383 3 0.01% 60.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::57088-57151 1 0.00% 60.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::59392-59455 1 0.00% 60.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::60416-60479 2 0.01% 60.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::61440-61503 1 0.00% 60.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::63488-63551 2 0.01% 60.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::63808-63871 1 0.00% 60.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::64512-64575 1 0.00% 60.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65024-65087 19 0.05% 60.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65088-65151 6 0.02% 60.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65152-65215 2 0.01% 60.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65280-65343 6 0.02% 60.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65344-65407 6 0.02% 60.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65408-65471 14 0.04% 60.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65472-65535 6 0.02% 60.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::65536-65599 14789 38.35% 99.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::71360-71423 1 0.00% 99.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::73984-74047 1 0.00% 99.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::83008-83071 1 0.00% 99.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::85504-85567 1 0.00% 99.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::93120-93183 1 0.00% 99.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::97152-97215 1 0.00% 99.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::97408-97471 1 0.00% 99.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::100672-100735 1 0.00% 99.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::103680-103743 1 0.00% 99.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::104768-104831 1 0.00% 99.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::106432-106495 1 0.00% 99.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::109760-109823 1 0.00% 99.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::110848-110911 1 0.00% 99.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::110912-110975 1 0.00% 99.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::114240-114303 1 0.00% 99.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::115328-115391 1 0.00% 99.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::116992-117055 1 0.00% 99.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::120320-120383 1 0.00% 99.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::121408-121471 1 0.00% 99.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::121472-121535 1 0.00% 99.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::124416-124479 1 0.00% 99.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::127552-127615 1 0.00% 99.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128640-128703 1 0.00% 99.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::130176-130239 1 0.00% 99.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::130368-130431 1 0.00% 99.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::130432-130495 1 0.00% 99.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::130496-130559 1 0.00% 99.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::130624-130687 1 0.00% 99.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::130688-130751 1 0.00% 99.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::130880-130943 1 0.00% 99.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::131072-131135 328 0.85% 99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::131200-131263 1 0.00% 99.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::132096-132159 3 0.01% 99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::136576-136639 1 0.00% 99.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::161408-161471 1 0.00% 99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::190336-190399 1 0.00% 99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::196032-196095 1 0.00% 99.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::196608-196671 2 0.01% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::420352-420415 1 0.00% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 38567 # Bytes accessed per row activation
system.physmem.totQLat 306544443250 # Total cycles spent in queuing delays
system.physmem.totMemAccLat 400266823250 # Sum of mem lat for all requests
system.physmem.totBusLat 77472300000 # Total cycles spent in databus access
system.physmem.totBankLat 16250080000 # Total cycles spent in bank access
system.physmem.avgQLat 19784.13 # Average queueing delay per request
system.physmem.avgBankLat 1048.77 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
system.physmem.avgMemAccLat 25832.90 # Average memory access latency
system.physmem.avgRdBW 379.13 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 19.87 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 50.65 # Average consumed read bandwidth in MB/s
system.physmem.avgConsumedWrBW 2.57 # Average consumed write bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 3.12 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.15 # Average read queue length over time
system.physmem.avgWrQLen 10.80 # Average write queue length over time
system.physmem.readRowHits 15469403 # Number of row buffer hits during reads
system.physmem.writeRowHits 798459 # Number of row buffer hits during writes
system.physmem.readRowHitRate 99.84 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 98.33 # Row buffer hit rate for writes
system.physmem.avgGap 160401.00 # Average gap between requests
system.realview.nvmem.bytes_read::cpu.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu.inst 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu.inst 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu.inst 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu.inst 8 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput 54138467 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 16546589 # Transaction distribution
system.membus.trans_dist::ReadResp 16546589 # Transaction distribution
system.membus.trans_dist::WriteReq 763368 # Transaction distribution
system.membus.trans_dist::WriteResp 763368 # Transaction distribution
system.membus.trans_dist::Writeback 57965 # Transaction distribution
system.membus.trans_dist::UpgradeReq 4516 # Transaction distribution
system.membus.trans_dist::UpgradeResp 4516 # Transaction distribution
system.membus.trans_dist::ReadExReq 132246 # Transaction distribution
system.membus.trans_dist::ReadExResp 132246 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.bridge.slave 2382986 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 1893707 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.cpu.l2cache.mem_side::total 4280555 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 30670848 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 30670848 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.bridge.slave 2382986 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.realview.nvmem.port 10 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.physmem.port 32564555 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.realview.gic.pio 3850 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::system.realview.a9scu.pio 2 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 34951403 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.bridge.slave 2390389 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 16524280 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::total 18922393 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 122683392 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 122683392 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.bridge.slave 2390389 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.realview.nvmem.port 20 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.physmem.port 139207672 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.realview.gic.pio 7700 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::system.realview.a9scu.pio 4 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 141605785 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 141605785 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 1206150500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer1.occupancy 5000 # Layer occupancy (ticks)
system.membus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 17904777500 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.7 # Layer utilization (%)
system.membus.reqLayer3.occupancy 3613000 # Layer occupancy (ticks)
system.membus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer5.occupancy 1000 # Layer occupancy (ticks)
system.membus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 4945376509 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.2 # Layer utilization (%)
system.membus.respLayer2.occupancy 34635651750 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 1.3 # Layer utilization (%)
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.iobus.throughput 47817981 # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq 16518751 # Transaction distribution
system.iobus.trans_dist::ReadResp 16518751 # Transaction distribution
system.iobus.trans_dist::WriteReq 8166 # Transaction distribution
system.iobus.trans_dist::WriteResp 8166 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 7944 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 534 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 2382986 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total 30670848 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.uart.pio 29936 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.realview_io.pio 7944 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.timer0.pio 534 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.timer1.pio 1042 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.clcd.pio 36 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.kmi0.pio 124 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.kmi1.pio 746 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.cf_ctrl.pio 2342380 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.sp810_fake.pio 20 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::system.iocache.cpu_side 30670848 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 33053834 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 1068 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total 2390389 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total 122683392 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.uart.pio 39180 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.realview_io.pio 15888 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.timer0.pio 1068 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.timer1.pio 2084 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.clcd.pio 72 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.kmi0.pio 86 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.kmi1.pio 397 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.cf_ctrl.pio 2331126 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.sp810_fake.pio 40 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::system.iocache.cpu_side 122683392 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total 125073781 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 125073781 # Total data (bytes)
system.iobus.reqLayer0.occupancy 21043000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 3977000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 534000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 527000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 27000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer5.occupancy 74000 # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 445000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 1172909000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 11000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 15335424000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
system.iobus.respLayer0.occupancy 2374820000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.1 # Layer utilization (%)
system.iobus.respLayer1.occupancy 30670848000 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 1.2 # Layer utilization (%)
system.cpu.dtb.inst_hits 0 # ITB inst hits
system.cpu.dtb.inst_misses 0 # ITB inst misses
system.cpu.dtb.read_hits 14996055 # DTB read hits
system.cpu.dtb.read_misses 7342 # DTB read misses
system.cpu.dtb.write_hits 11230429 # DTB write hits
system.cpu.dtb.write_misses 2216 # DTB write misses
system.cpu.dtb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries 3506 # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults 192 # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses 15003397 # DTB read accesses
system.cpu.dtb.write_accesses 11232645 # DTB write accesses
system.cpu.dtb.inst_accesses 0 # ITB inst accesses
system.cpu.dtb.hits 26226484 # DTB hits
system.cpu.dtb.misses 9558 # DTB misses
system.cpu.dtb.accesses 26236042 # DTB accesses
system.cpu.itb.inst_hits 61492425 # ITB inst hits
system.cpu.itb.inst_misses 4471 # ITB inst misses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.flush_tlb 2 # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid 1439 # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid 63 # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries 2343 # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.inst_accesses 61496896 # ITB inst accesses
system.cpu.itb.hits 61492425 # DTB hits
system.cpu.itb.misses 4471 # DTB misses
system.cpu.itb.accesses 61496896 # DTB accesses
system.cpu.numCycles 5231244768 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.committedInsts 60198587 # Number of instructions committed
system.cpu.committedOps 76605405 # Number of ops (including micro ops) committed
system.cpu.num_int_alu_accesses 68872209 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 10269 # Number of float alu accesses
system.cpu.num_func_calls 2140451 # number of times a function call or return occured
system.cpu.num_conditional_control_insts 7948368 # number of instructions that are conditional controls
system.cpu.num_int_insts 68872209 # number of integer instructions
system.cpu.num_fp_insts 10269 # number of float instructions
system.cpu.num_int_register_reads 394776354 # number of times the integer registers were read
system.cpu.num_int_register_writes 74181797 # number of times the integer registers were written
system.cpu.num_fp_register_reads 7493 # number of times the floating registers were read
system.cpu.num_fp_register_writes 2780 # number of times the floating registers were written
system.cpu.num_mem_refs 27393915 # number of memory refs
system.cpu.num_load_insts 15660071 # Number of load instructions
system.cpu.num_store_insts 11733844 # Number of store instructions
system.cpu.num_idle_cycles 4582065338.612248 # Number of idle cycles
system.cpu.num_busy_cycles 649179429.387752 # Number of busy cycles
system.cpu.not_idle_fraction 0.124097 # Percentage of non-idle cycles
system.cpu.idle_fraction 0.875903 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 83018 # number of quiesce instructions executed
system.cpu.icache.replacements 856250 # number of replacements
system.cpu.icache.tagsinuse 510.885364 # Cycle average of tags in use
system.cpu.icache.total_refs 60635663 # Total number of references to valid blocks.
system.cpu.icache.sampled_refs 856762 # Sample count of references to valid blocks.
system.cpu.icache.avg_refs 70.773054 # Average number of references to valid blocks.
system.cpu.icache.warmup_cycle 19768699000 # Cycle when the warmup percentage was hit.
system.cpu.icache.occ_blocks::cpu.inst 510.885364 # Average occupied blocks per requestor
system.cpu.icache.occ_percent::cpu.inst 0.997823 # Average percentage of cache occupancy
system.cpu.icache.occ_percent::total 0.997823 # Average percentage of cache occupancy
system.cpu.icache.ReadReq_hits::cpu.inst 60635663 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 60635663 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 60635663 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 60635663 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 60635663 # number of overall hits
system.cpu.icache.overall_hits::total 60635663 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 856762 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 856762 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 856762 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 856762 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 856762 # number of overall misses
system.cpu.icache.overall_misses::total 856762 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 11759087500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 11759087500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 11759087500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 11759087500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 11759087500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 11759087500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 61492425 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 61492425 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 61492425 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 61492425 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 61492425 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 61492425 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.013933 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.013933 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.013933 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.013933 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.013933 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.013933 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13725.033907 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 13725.033907 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 13725.033907 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 13725.033907 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 13725.033907 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 13725.033907 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 856762 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 856762 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 856762 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 856762 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 856762 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 856762 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 10045563500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 10045563500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 10045563500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 10045563500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 10045563500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 10045563500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::cpu.inst 429084500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_uncacheable_latency::total 429084500 # number of ReadReq MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::cpu.inst 429084500 # number of overall MSHR uncacheable cycles
system.cpu.icache.overall_mshr_uncacheable_latency::total 429084500 # number of overall MSHR uncacheable cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.013933 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.013933 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.013933 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.013933 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 11725.033907 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 11725.033907 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 11725.033907 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 11725.033907 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 11725.033907 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 11725.033907 # average overall mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.icache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.icache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.l2cache.replacements 62577 # number of replacements
system.cpu.l2cache.tagsinuse 50733.086800 # Cycle average of tags in use
system.cpu.l2cache.total_refs 1684914 # Total number of references to valid blocks.
system.cpu.l2cache.sampled_refs 128011 # Sample count of references to valid blocks.
system.cpu.l2cache.avg_refs 13.162259 # Average number of references to valid blocks.
system.cpu.l2cache.warmup_cycle 2564823166000 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.occ_blocks::writebacks 37695.331461 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.dtb.walker 3.884612 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.itb.walker 0.000689 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.inst 6997.589035 # Average occupied blocks per requestor
system.cpu.l2cache.occ_blocks::cpu.data 6036.281004 # Average occupied blocks per requestor
system.cpu.l2cache.occ_percent::writebacks 0.575185 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.dtb.walker 0.000059 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.itb.walker 0.000000 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.inst 0.106775 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::cpu.data 0.092106 # Average percentage of cache occupancy
system.cpu.l2cache.occ_percent::total 0.774125 # Average percentage of cache occupancy
system.cpu.l2cache.ReadReq_hits::cpu.dtb.walker 8724 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.itb.walker 3533 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.inst 844523 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 369967 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1226747 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 595512 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 595512 # number of Writeback hits
system.cpu.l2cache.UpgradeReq_hits::cpu.data 26 # number of UpgradeReq hits
system.cpu.l2cache.UpgradeReq_hits::total 26 # number of UpgradeReq hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 113491 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 113491 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.dtb.walker 8724 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.itb.walker 3533 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.inst 844523 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 483458 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1340238 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.dtb.walker 8724 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.itb.walker 3533 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.inst 844523 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 483458 # number of overall hits
system.cpu.l2cache.overall_hits::total 1340238 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.dtb.walker 5 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.itb.walker 2 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.inst 10599 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 9833 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 20439 # number of ReadReq misses
system.cpu.l2cache.UpgradeReq_misses::cpu.data 2885 # number of UpgradeReq misses
system.cpu.l2cache.UpgradeReq_misses::total 2885 # number of UpgradeReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 133877 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 133877 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.dtb.walker 5 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.itb.walker 2 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.inst 10599 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 143710 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 154316 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.dtb.walker 5 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.itb.walker 2 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.inst 10599 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 143710 # number of overall misses
system.cpu.l2cache.overall_misses::total 154316 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.dtb.walker 468000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.itb.walker 122000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 741931500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 698335500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 1440857000 # number of ReadReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::cpu.data 460000 # number of UpgradeReq miss cycles
system.cpu.l2cache.UpgradeReq_miss_latency::total 460000 # number of UpgradeReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 8582435500 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 8582435500 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.dtb.walker 468000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.itb.walker 122000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 741931500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 9280771000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 10023292500 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.dtb.walker 468000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.itb.walker 122000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 741931500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 9280771000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 10023292500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.dtb.walker 8729 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.itb.walker 3535 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.inst 855122 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 379800 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 1247186 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 595512 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 595512 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2911 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.UpgradeReq_accesses::total 2911 # number of UpgradeReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 247368 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 247368 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.dtb.walker 8729 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.itb.walker 3535 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.inst 855122 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 627168 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 1494554 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.dtb.walker 8729 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.itb.walker 3535 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 855122 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 627168 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 1494554 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.dtb.walker 0.000573 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.itb.walker 0.000566 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.012395 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.025890 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.016388 # miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.991068 # miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_miss_rate::total 0.991068 # miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.541206 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.541206 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.dtb.walker 0.000573 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.itb.walker 0.000566 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.012395 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.229141 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.103252 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.dtb.walker 0.000573 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.itb.walker 0.000566 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.012395 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.229141 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.103252 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.dtb.walker 93600 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.itb.walker 61000 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70000.141523 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 71019.576935 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 70495.474338 # average ReadReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::cpu.data 159.445407 # average UpgradeReq miss latency
system.cpu.l2cache.UpgradeReq_avg_miss_latency::total 159.445407 # average UpgradeReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 64106.870486 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 64106.870486 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.dtb.walker 93600 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.itb.walker 61000 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70000.141523 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 64579.855264 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 64953.034682 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.dtb.walker 93600 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.itb.walker 61000 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70000.141523 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 64579.855264 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 64953.034682 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 57965 # number of writebacks
system.cpu.l2cache.writebacks::total 57965 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.dtb.walker 5 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.itb.walker 2 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 10599 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 9833 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 20439 # number of ReadReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 2885 # number of UpgradeReq MSHR misses
system.cpu.l2cache.UpgradeReq_mshr_misses::total 2885 # number of UpgradeReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 133877 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 133877 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.dtb.walker 5 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.itb.walker 2 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 10599 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 143710 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 154316 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.dtb.walker 5 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.itb.walker 2 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 10599 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 143710 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 154316 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.dtb.walker 404750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.itb.walker 97500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 611089500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 576558000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 1188149750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 28854885 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 28854885 # number of UpgradeReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6940085381 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6940085381 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.dtb.walker 404750 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.itb.walker 97500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 611089500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 7516643381 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 8128235131 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.dtb.walker 404750 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.itb.walker 97500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 611089500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 7516643381 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 8128235131 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.inst 339371500 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::cpu.data 166657063250 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_uncacheable_latency::total 166996434750 # number of ReadReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::cpu.data 16701843725 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.WriteReq_mshr_uncacheable_latency::total 16701843725 # number of WriteReq MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.inst 339371500 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::cpu.data 183358906975 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.overall_mshr_uncacheable_latency::total 183698278475 # number of overall MSHR uncacheable cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.dtb.walker 0.000573 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.012395 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.025890 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.016388 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.991068 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.991068 # mshr miss rate for UpgradeReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.541206 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.541206 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000573 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.012395 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.229141 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.103252 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000573 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000566 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.012395 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.229141 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.103252 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 80950 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 48750 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57655.392018 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 58635.004576 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58131.501052 # average ReadReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001.693241 # average UpgradeReq mshr miss latency
system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001.693241 # average UpgradeReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 51839.265751 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 51839.265751 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 80950 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 48750 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57655.392018 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 52304.247311 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 52672.666029 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 80950 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 48750 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57655.392018 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 52304.247311 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 52672.666029 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.inst inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.inst inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.replacements 626656 # number of replacements
system.cpu.dcache.tagsinuse 511.879114 # Cycle average of tags in use
system.cpu.dcache.total_refs 23655617 # Total number of references to valid blocks.
system.cpu.dcache.sampled_refs 627168 # Sample count of references to valid blocks.
system.cpu.dcache.avg_refs 37.718150 # Average number of references to valid blocks.
system.cpu.dcache.warmup_cycle 650249000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.occ_blocks::cpu.data 511.879114 # Average occupied blocks per requestor
system.cpu.dcache.occ_percent::cpu.data 0.999764 # Average percentage of cache occupancy
system.cpu.dcache.occ_percent::total 0.999764 # Average percentage of cache occupancy
system.cpu.dcache.ReadReq_hits::cpu.data 13195840 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 13195840 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 9972724 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 9972724 # number of WriteReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data 236345 # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total 236345 # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data 247797 # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total 247797 # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data 23168564 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 23168564 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 23168564 # number of overall hits
system.cpu.dcache.overall_hits::total 23168564 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 368347 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 368347 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 250279 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 250279 # number of WriteReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data 11453 # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total 11453 # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data 618626 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 618626 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 618626 # number of overall misses
system.cpu.dcache.overall_misses::total 618626 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5378545500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 5378545500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 10531910500 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 10531910500 # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 158860000 # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total 158860000 # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 15910456000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 15910456000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 15910456000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 15910456000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 13564187 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 13564187 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 10223003 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 10223003 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data 247798 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total 247798 # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data 247797 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total 247797 # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 23787190 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 23787190 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 23787190 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 23787190 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.027156 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.027156 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.024482 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.024482 # miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.046219 # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total 0.046219 # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.026007 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.026007 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.026007 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.026007 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 14601.844185 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 14601.844185 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42080.679961 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 42080.679961 # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 13870.601589 # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 13870.601589 # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 25719.022479 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 25719.022479 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 25719.022479 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 25719.022479 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 595512 # number of writebacks
system.cpu.dcache.writebacks::total 595512 # number of writebacks
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 368347 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 368347 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 250279 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 250279 # number of WriteReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 11453 # number of LoadLockedReq MSHR misses
system.cpu.dcache.LoadLockedReq_mshr_misses::total 11453 # number of LoadLockedReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 618626 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 618626 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 618626 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 618626 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4641851500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 4641851500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 10031352500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 10031352500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 135954000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 135954000 # number of LoadLockedReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 14673204000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 14673204000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 14673204000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 14673204000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::cpu.data 182050723500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_uncacheable_latency::total 182050723500 # number of ReadReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::cpu.data 26234076500 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.WriteReq_mshr_uncacheable_latency::total 26234076500 # number of WriteReq MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::cpu.data 208284800000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.overall_mshr_uncacheable_latency::total 208284800000 # number of overall MSHR uncacheable cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.027156 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.027156 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.024482 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.024482 # mshr miss rate for WriteReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.046219 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.046219 # mshr miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.026007 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.026007 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.026007 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.026007 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12601.844185 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12601.844185 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40080.679961 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40080.679961 # average WriteReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 11870.601589 # average LoadLockedReq mshr miss latency
system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11870.601589 # average LoadLockedReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 23719.022479 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 23719.022479 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 23719.022479 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 23719.022479 # average overall mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::cpu.data inf # average overall mshr uncacheable latency
system.cpu.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput 53002965 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 2454953 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 2454953 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteReq 763368 # Transaction distribution
system.cpu.toL2Bus.trans_dist::WriteResp 763368 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 595512 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeReq 2911 # Transaction distribution
system.cpu.toL2Bus.trans_dist::UpgradeResp 2911 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 247368 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 247368 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 1725126 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 5750616 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.itb.walker.dma 12461 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dtb.walker.dma 27468 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count 7515671 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 54754292 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 83665829 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.itb.walker.dma 14140 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dtb.walker.dma 34916 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size 138469177 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 138469177 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 166564 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 3009252000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1291764000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 2507996500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
system.cpu.toL2Bus.respLayer2.occupancy 8926000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer3.occupancy 18739000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 0 # Sample count of references to valid blocks.
system.iocache.avg_refs nan # Average number of references to valid blocks.
system.iocache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1470128900250 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1470128900250 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1470128900250 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1470128900250 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
Reference in a new issue View git blame Copy permalink