a6074016e2
This patch removes the NACKing in the bridge, as the split request/response busses now ensure that protocol deadlocks do not occur, i.e. the message-dependency chain is broken by always allowing responses to make progress without being stalled by requests. The NACKs had limited support in the system with most components ignoring their use (with a suitable call to panic), and as the NACKs are no longer needed to avoid protocol deadlocks, the cleanest way is to simply remove them. The bridge is the starting point as this is the only place where the NACKs are created. A follow-up patch will remove the code that deals with NACKs in the endpoints, e.g. the X86 table walker and DMA port. Ultimately the type of packet can be complete removed (until someone sees a need for modelling more complex protocols, which can now be done in parts of the system since the port and interface is split). As a consequence of the NACK removal, the bridge now has to send a retry to a master if the request or response queue was full on the first attempt. This change also makes the bridge ports very similar to QueuedPorts, and a later patch will change the bridge to use these. A first step in this direction is taken by aligning the name of the member functions, as done by this patch. A bit of tidying up has also been done as part of the simplifications. Surprisingly, this patch has no impact on any of the regressions. Hence, there was never any NACKs issued. In a follow-up patch I would suggest changing the size of the bridge buffers set in FSConfig.py to also test the situation where the bridge fills up.
185 lines
6.7 KiB
Python
185 lines
6.7 KiB
Python
# Copyright (c) 2010-2012 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Ali Saidi
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import optparse
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import sys
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import m5
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from m5.defines import buildEnv
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from m5.objects import *
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from m5.util import addToPath, fatal
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addToPath('../common')
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from FSConfig import *
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from SysPaths import *
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from Benchmarks import *
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import Simulation
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import CacheConfig
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from Caches import *
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import Options
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parser = optparse.OptionParser()
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Options.addCommonOptions(parser)
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Options.addFSOptions(parser)
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(options, args) = parser.parse_args()
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if args:
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print "Error: script doesn't take any positional arguments"
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sys.exit(1)
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# driver system CPU is always simple... note this is an assignment of
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# a class, not an instance.
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DriveCPUClass = AtomicSimpleCPU
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drive_mem_mode = 'atomic'
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# system under test can be any CPU
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(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
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TestCPUClass.clock = options.clock
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DriveCPUClass.clock = options.clock
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if options.benchmark:
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try:
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bm = Benchmarks[options.benchmark]
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except KeyError:
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print "Error benchmark %s has not been defined." % options.benchmark
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print "Valid benchmarks are: %s" % DefinedBenchmarks
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sys.exit(1)
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else:
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if options.dual:
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bm = [SysConfig(disk=options.disk_image, mem=options.mem_size), SysConfig(disk=options.disk_image, mem=options.mem_size)]
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else:
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bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)]
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np = options.num_cpus
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if buildEnv['TARGET_ISA'] == "alpha":
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test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
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elif buildEnv['TARGET_ISA'] == "mips":
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test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
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elif buildEnv['TARGET_ISA'] == "sparc":
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test_sys = makeSparcSystem(test_mem_mode, bm[0])
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elif buildEnv['TARGET_ISA'] == "x86":
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test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0])
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elif buildEnv['TARGET_ISA'] == "arm":
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test_sys = makeArmSystem(test_mem_mode,
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options.machine_type, bm[0],
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bare_metal=options.bare_metal)
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else:
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fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
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if options.kernel is not None:
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test_sys.kernel = binary(options.kernel)
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if options.script is not None:
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test_sys.readfile = options.script
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test_sys.init_param = options.init_param
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test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
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if bm[0]:
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mem_size = bm[0].mem()
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else:
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mem_size = SysConfig().mem()
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if options.caches or options.l2cache:
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test_sys.iocache = IOCache(addr_ranges=[test_sys.physmem.range])
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test_sys.iocache.cpu_side = test_sys.iobus.master
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test_sys.iocache.mem_side = test_sys.membus.slave
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else:
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test_sys.iobridge = Bridge(delay='50ns', ranges = [test_sys.physmem.range])
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test_sys.iobridge.slave = test_sys.iobus.master
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test_sys.iobridge.master = test_sys.membus.slave
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# Sanity check
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if options.fastmem and (options.caches or options.l2cache):
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fatal("You cannot use fastmem in combination with caches!")
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for i in xrange(np):
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if options.fastmem:
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test_sys.cpu[i].fastmem = True
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if options.checker:
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test_sys.cpu[i].addCheckerCpu()
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CacheConfig.config_cache(options, test_sys)
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if len(bm) == 2:
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if buildEnv['TARGET_ISA'] == 'alpha':
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drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
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elif buildEnv['TARGET_ISA'] == 'mips':
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drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1])
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elif buildEnv['TARGET_ISA'] == 'sparc':
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drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
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elif buildEnv['TARGET_ISA'] == 'x86':
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drive_sys = makeX86System(drive_mem_mode, np, bm[1])
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elif buildEnv['TARGET_ISA'] == 'arm':
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drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1])
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drive_sys.cpu = DriveCPUClass(cpu_id=0)
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drive_sys.cpu.createInterruptController()
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drive_sys.cpu.connectAllPorts(drive_sys.membus)
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if options.fastmem:
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drive_sys.cpu.fastmem = True
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if options.kernel is not None:
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drive_sys.kernel = binary(options.kernel)
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drive_sys.iobridge = Bridge(delay='50ns',
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ranges = [drive_sys.physmem.range])
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drive_sys.iobridge.slave = drive_sys.iobus.master
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drive_sys.iobridge.master = drive_sys.membus.slave
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drive_sys.init_param = options.init_param
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root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
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elif len(bm) == 1:
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root = Root(full_system=True, system=test_sys)
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else:
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print "Error I don't know how to create more than 2 systems."
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sys.exit(1)
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if options.timesync:
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root.time_sync_enable = True
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if options.frame_capture:
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VncServer.frame_capture = True
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Simulation.setWorkCountOptions(test_sys, options)
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Simulation.run(options, root, test_sys, FutureClass)
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