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3ccaee976a
gem5
/
src
/
arch
/
sparc
/
isa
History
Gabe Black
3ccaee976a
Make the SPARC branch instructions use ExtMachInsts in their constructors. This isn't necessary since they don't use the extended fields, but it's more consistent and more correct.
...
--HG-- extra : convert_revision : afd4f408122ad5e497012eb9744d6bce66a1de37
2007-03-16 10:55:50 +00:00
..
formats
Make the SPARC branch instructions use ExtMachInsts in their constructors. This isn't necessary since they don't use the extended fields, but it's more consistent and more correct.
2007-03-16 10:55:50 +00:00
base.isa
*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg
2007-03-07 15:04:31 -05:00
bitfields.isa
add pseduo instruction support for sparc
2007-02-21 21:06:17 -05:00
decoder.isa
Fix mulscc.
2007-03-12 17:07:10 -04:00
includes.isa
add pseduo instruction support for sparc
2007-02-21 21:06:17 -05:00
main.isa
Broke Load/Store instructions into microcode, and partially refactored memory operations in the SPARC ISA description.
2006-10-23 07:55:52 -04:00
operands.isa
make ldtw(a) -- Twin 32 bit load work correctly -- by doing it the same way as the twin 64 bit loads
2007-03-02 22:34:51 -05:00