9b1e2db811
cpu/base_cpu.cc:
cpu/base_cpu.hh:
Convert the CPU stuff to use a params struct
cpu/memtest/memtest.cc:
The memory tester is really not a cpu, so don't derive from
BaseCPU since it just makes things a pain in the butt. Keep
track of max loads in the memtest class now that the base class
doesn't do it for us.
Don't have any default parameters.
cpu/memtest/memtest.hh:
The memory tester is really not a cpu, so don't derive from
BaseCPU since it just makes things a pain in the butt. Keep
track of max loads in the memtest class now that the base class
doesn't do it for us.
cpu/simple_cpu/simple_cpu.cc:
Convert to use a params struct.
remove default parameters
cpu/simple_cpu/simple_cpu.hh:
convert to use a params struct
cpu/trace/opt_cpu.cc:
cpu/trace/opt_cpu.hh:
cpu/trace/trace_cpu.cc:
cpu/trace/trace_cpu.hh:
this isn't really a cpu. don't derive from BaseCPU
objects/MemTest.mpy:
we only need one max_loads parameter
sim/main.cc:
Don't check for the number of CPUs since we may be doing something
else going on. If we don't have anything to simulate, the
simulator will exit anyway.
--HG--
extra : convert_revision : 2195a34a9ec90b5414324054ceb3bab643540dd5
138 lines
3.7 KiB
C++
138 lines
3.7 KiB
C++
/*
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* Copyright (c) 2004 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/**
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* @file
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* Declaration of a memory trace CPU object. Uses a memory trace to drive the
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* provided memory hierarchy.
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*/
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#ifndef __CPU_TRACE_TRACE_CPU_HH__
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#define __CPU_TRACE_TRACE_CPU_HH__
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#include <string>
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#include "mem/mem_req.hh" // for MemReqPtr
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#include "sim/eventq.hh" // for Event
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#include "sim/sim_object.hh"
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// Forward declaration.
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class MemInterface;
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class MemTraceReader;
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/**
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* A cpu object for running memory traces through a memory hierarchy.
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*/
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class TraceCPU : public SimObject
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{
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private:
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/** Interface for instruction trace requests, if any. */
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MemInterface *icacheInterface;
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/** Interface for data trace requests, if any. */
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MemInterface *dcacheInterface;
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/** Data reference trace. */
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MemTraceReader *dataTrace;
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/** Number of outstanding requests. */
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int outstandingRequests;
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/** Cycle of the next request, 0 if not available. */
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Tick nextCycle;
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/** Next request. */
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MemReqPtr nextReq;
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/**
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* Event to call the TraceCPU::tick
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*/
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class TickEvent : public Event
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{
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private:
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/** The associated CPU */
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TraceCPU *cpu;
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public:
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/**
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* Construct this event;
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*/
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TickEvent(TraceCPU *c);
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/**
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* Call the tick function.
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*/
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void process();
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/**
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* Return a string description of this event.
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*/
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const char *description();
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};
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TickEvent tickEvent;
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public:
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/**
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* Construct a TraceCPU object.
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*/
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TraceCPU(const std::string &name,
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MemInterface *icache_interface,
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MemInterface *dcache_interface,
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MemTraceReader *data_trace);
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/**
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* Perform all the accesses for one cycle.
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*/
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void tick();
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/**
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* Handle a completed memory request.
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*/
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void completeRequest(MemReqPtr &req);
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};
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class TraceCompleteEvent : public Event
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{
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MemReqPtr req;
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TraceCPU *tester;
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public:
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TraceCompleteEvent(MemReqPtr &_req, TraceCPU *_tester)
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: Event(&mainEventQueue), req(_req), tester(_tester)
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{
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setFlags(AutoDelete);
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}
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void process();
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virtual const char *description();
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};
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#endif // __CPU_TRACE_TRACE_CPU_HH__
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