3c7071a6be
Added function to skip determine_cpu_caches(). We may have to update this in the
future: see note below.
arch/alpha/alpha_memory.cc:
dev/ide_ctrl.cc:
dev/tsunamireg.h:
Added ULL for 64bit ints
kern/linux/linux_system.cc:
Added a function to skip determine_cpu_caches, right now it is only used for
printing in proc, however in the future we may either want to implement the SC_CTL
IPR register or manually set alpha_l1i_cacheshape, alpha_l1d_cacheshape,
alpha_l2_cacheshape, alpha_l3_cacheshape to ((size << 10) | (linesize>>1)<<4 | way)
kern/linux/linux_system.hh:
added event to skip determine_cpu_caches()
--HG--
extra : convert_revision : 1065f2091bbe6832b730af490f5b4672c2afedce
111 lines
3.3 KiB
C
111 lines
3.3 KiB
C
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#ifndef __TSUNAMIREG_H__
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#define __TSUNAMIREG_H__
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#define ALPHA_K0SEG_BASE 0xfffffc0000000000ULL
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// CChip Registers
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#define TSDEV_CC_CSR 0x00
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#define TSDEV_CC_MTR 0x01
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#define TSDEV_CC_MISC 0x02
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#define TSDEV_CC_AAR0 0x04
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#define TSDEV_CC_AAR1 0x05
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#define TSDEV_CC_AAR2 0x06
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#define TSDEV_CC_AAR3 0x07
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#define TSDEV_CC_DIM0 0x08
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#define TSDEV_CC_DIM1 0x09
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#define TSDEV_CC_DIR0 0x0A
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#define TSDEV_CC_DIR1 0x0B
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#define TSDEV_CC_DRIR 0x0C
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#define TSDEV_CC_PRBEN 0x0D
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#define TSDEV_CC_IIC0 0x0E
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#define TSDEV_CC_IIC1 0x0F
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#define TSDEV_CC_MPR0 0x10
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#define TSDEV_CC_MPR1 0x11
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#define TSDEV_CC_MPR2 0x12
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#define TSDEV_CC_MPR3 0x13
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#define TSDEV_CC_DIM2 0x18
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#define TSDEV_CC_DIM3 0x19
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#define TSDEV_CC_DIR2 0x1A
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#define TSDEV_CC_DIR3 0x1B
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#define TSDEV_CC_IIC2 0x1C
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#define TSDEV_CC_IIC3 0x1D
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// PChip Registers
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#define TSDEV_PC_WSBA0 0x00
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#define TSDEV_PC_WSBA1 0x01
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#define TSDEV_PC_WSBA2 0x02
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#define TSDEV_PC_WSBA3 0x03
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#define TSDEV_PC_WSM0 0x04
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#define TSDEV_PC_WSM1 0x05
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#define TSDEV_PC_WSM2 0x06
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#define TSDEV_PC_WSM3 0x07
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#define TSDEV_PC_TBA0 0x08
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#define TSDEV_PC_TBA1 0x09
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#define TSDEV_PC_TBA2 0x0A
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#define TSDEV_PC_TBA3 0x0B
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#define TSDEV_PC_PCTL 0x0C
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#define TSDEV_PC_PLAT 0x0D
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#define TSDEV_PC_RES 0x0E
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#define TSDEV_PC_PERROR 0x0F
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#define TSDEV_PC_PERRMASK 0x10
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#define TSDEV_PC_PERRSET 0x11
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#define TSDEV_PC_TLBIV 0x12
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#define TSDEV_PC_TLBIA 0x13
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#define TSDEV_PC_PMONCTL 0x14
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#define TSDEV_PC_PMONCNT 0x15
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#define TSDEV_PC_SPST 0x20
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// DChip Registers
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#define TSDEV_DC_DSC 0x20
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#define TSDEV_DC_STR 0x21
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#define TSDEV_DC_DREV 0x22
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#define TSDEV_DC_DSC2 0x23
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// I/O Ports
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#define TSDEV_PIC1_MASK 0x21
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#define TSDEV_PIC2_MASK 0xA1
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#define TSDEV_DMA1_RESET 0x0D
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#define TSDEV_DMA2_RESET 0xDA
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#define TSDEV_DMA1_MODE 0x0B
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#define TSDEV_DMA2_MODE 0xD6
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#define TSDEV_DMA1_MASK 0x0A
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#define TSDEV_DMA2_MASK 0xD4
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#define TSDEV_TMR_CTL 0x61
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#define TSDEV_TMR2_CTL 0x43
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#define TSDEV_TMR2_DATA 0x42
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#define TSDEV_TMR0_DATA 0x40
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#define TSDEV_RTC_ADDR 0x70
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#define TSDEV_RTC_DATA 0x71
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// RTC defines
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#define RTC_SECOND 0 // second of minute [0..59]
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#define RTC_SECOND_ALARM 1 // seconds to alarm
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#define RTC_MINUTE 2 // minute of hour [0..59]
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#define RTC_MINUTE_ALARM 3 // minutes to alarm
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#define RTC_HOUR 4 // hour of day [0..23]
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#define RTC_HOUR_ALARM 5 // hours to alarm
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#define RTC_DAY_OF_WEEK 6 // day of week [1..7]
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#define RTC_DAY_OF_MONTH 7 // day of month [1..31]
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#define RTC_MONTH 8 // month of year [1..12]
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#define RTC_YEAR 9 // year [00..99]
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#define RTC_CONTROL_REGISTERA 10 // control register A
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#define RTC_CONTROL_REGISTERB 11 // control register B
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#define RTC_CONTROL_REGISTERC 12 // control register C
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#define RTC_CONTROL_REGISTERD 13 // control register D
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#define RTC_REGNUMBER_RTC_CR1 0x6A // control register 1
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#define PCHIP_PCI0_MEMORY 0x10000000000ULL
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#define PCHIP_PCI0_IO 0x101FC000000ULL
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#define TSUNAMI_PCI0_MEMORY ALPHA_K0SEG_BASE + PCHIP_PCI0_MEMORY
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#define TSUNAMI_PCI0_IO ALPHA_K0SEG_BASE + PCHIP_PCI0_IO
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#endif // __TSUNAMIREG_H__
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