e3fb3d1ad0
physical addressing. This has the uncacheable bit as bit 40 as opposed to bit 39. Additionally, we now support (at least superficially) a 44-bit physical address. To deal with superpage access in this scheme, any super page access with either bit 39 or 40 set is sign extended. --HG-- extra : convert_revision : 05ddbcb9a6a92481109a63b261743881953620ab
104 lines
2.7 KiB
C++
104 lines
2.7 KiB
C++
/* $Id$ */
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#ifndef __EV5_H__
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#define __EV5_H__
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#ifndef SYSTEM_EV5
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#error This code is only valid for EV5 systems
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#endif
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#include "targetarch/isa_traits.hh"
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////////////////////////////////////////////////////////////////////////
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//
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//
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//
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////////////////////////////////////////////////////////////////////////
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//
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//
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//
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#define MODE2MASK(X) (1 << (X))
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// Alpha IPR register accessors
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#define PC_PAL(X) ((X) & 0x1)
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#define MCSR_SP(X) (((X) >> 1) & 0x3)
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#define ICSR_SDE(X) (((X) >> 30) & 0x1)
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#define ICSR_SPE(X) (((X) >> 28) & 0x3)
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#define ICSR_FPE(X) (((X) >> 26) & 0x1)
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#define ALT_MODE_AM(X) (((X) >> 3) & 0x3)
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#define DTB_CM_CM(X) (((X) >> 3) & 0x3)
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#define DTB_ASN_ASN(X) (((X) >> 57) & 0x7f)
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#define DTB_PTE_PPN(X) (((X) >> 32) & 0x07ffffff)
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#define DTB_PTE_XRE(X) (((X) >> 8) & 0xf)
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#define DTB_PTE_XWE(X) (((X) >> 12) & 0xf)
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#define DTB_PTE_FONR(X) (((X) >> 1) & 0x1)
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#define DTB_PTE_FONW(X) (((X) >> 2) & 0x1)
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#define DTB_PTE_GH(X) (((X) >> 5) & 0x3)
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#define DTB_PTE_ASMA(X) (((X) >> 4) & 0x1)
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#define ICM_CM(X) (((X) >> 3) & 0x3)
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#define ITB_ASN_ASN(X) (((X) >> 4) & 0x7f)
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#define ITB_PTE_PPN(X) (((X) >> 32) & 0x07ffffff)
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#define ITB_PTE_XRE(X) (((X) >> 8) & 0xf)
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#define ITB_PTE_FONR(X) (((X) >> 1) & 0x1)
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#define ITB_PTE_FONW(X) (((X) >> 2) & 0x1)
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#define ITB_PTE_GH(X) (((X) >> 5) & 0x3)
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#define ITB_PTE_ASMA(X) (((X) >> 4) & 0x1)
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#define VA_UNIMPL_MASK ULL(0xfffff80000000000)
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#define VA_IMPL_MASK ULL(0x000007ffffffffff)
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#define VA_IMPL(X) ((X) & VA_IMPL_MASK)
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#define VA_VPN(X) (VA_IMPL(X) >> 13)
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#define VA_SPACE(X) (((X) >> 41) & 0x3)
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#define VA_POFS(X) ((X) & 0x1fff)
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#define PA_IMPL_MASK ULL(0xfffffffffff) // for Tsunami
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#define PA_UNCACHED_BIT_39 ULL(0x8000000000)
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#define PA_UNCACHED_BIT_40 ULL(0x10000000000)
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#define PA_IPR_SPACE(X) ((X) >= ULL(0xFFFFFF00000))
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#define PA_PFN2PA(X) ((X) << 13)
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#define MM_STAT_BAD_VA_MASK 0x0020
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#define MM_STAT_DTB_MISS_MASK 0x0010
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#define MM_STAT_FONW_MASK 0x0008
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#define MM_STAT_FONR_MASK 0x0004
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#define MM_STAT_ACV_MASK 0x0002
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#define MM_STAT_WR_MASK 0x0001
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////////////////////////////////////////////////////////////////////////
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//
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//
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//
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// VPTE size for HW_LD/HW_ST
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#define HW_VPTE ((inst >> 11) & 0x1)
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// QWORD size for HW_LD/HW_ST
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#define HW_QWORD ((inst >> 12) & 0x1)
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// ALT mode for HW_LD/HW_ST
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#define HW_ALT (((inst >> 14) & 0x1) ? ALTMODE : 0)
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// LOCK/COND mode for HW_LD/HW_ST
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#define HW_LOCK (((inst >> 10) & 0x1) ? LOCKED : 0)
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#define HW_COND (((inst >> 10) & 0x1) ? LOCKED : 0)
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// PHY size for HW_LD/HW_ST
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#define HW_PHY (((inst >> 15) & 0x1) ? PHYSICAL : 0)
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// OFFSET for HW_LD/HW_ST
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#define HW_OFS (inst & 0x3ff)
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#define PAL_BASE 0x4000
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#endif //__EV5_H__
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