2510 lines
286 KiB
Text
2510 lines
286 KiB
Text
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---------- Begin Simulation Statistics ----------
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sim_seconds 0.000106 # Number of seconds simulated
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sim_ticks 105945500 # Number of ticks simulated
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final_tick 105945500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
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sim_freq 1000000000000 # Frequency of simulated ticks
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host_inst_rate 48441 # Simulator instruction rate (inst/s)
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host_op_rate 48441 # Simulator op (including micro ops) rate (op/s)
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host_tick_rate 4953275 # Simulator tick rate (ticks/s)
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host_mem_usage 291288 # Number of bytes of host memory used
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host_seconds 21.39 # Real time elapsed on the host
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sim_insts 1036095 # Number of instructions simulated
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sim_ops 1036095 # Number of ops (including micro ops) simulated
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system.physmem.bytes_read::cpu0.inst 22848 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu0.data 10752 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.inst 4992 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu1.data 1280 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.inst 512 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu2.data 832 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu3.inst 192 # Number of bytes read from this memory
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system.physmem.bytes_read::cpu3.data 832 # Number of bytes read from this memory
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system.physmem.bytes_read::total 42240 # Number of bytes read from this memory
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system.physmem.bytes_inst_read::cpu0.inst 22848 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu1.inst 4992 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu2.inst 512 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::cpu3.inst 192 # Number of instructions bytes read from this memory
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system.physmem.bytes_inst_read::total 28544 # Number of instructions bytes read from this memory
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system.physmem.num_reads::cpu0.inst 357 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu0.data 168 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.inst 78 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu1.data 20 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.inst 8 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu2.data 13 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu3.inst 3 # Number of read requests responded to by this memory
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system.physmem.num_reads::cpu3.data 13 # Number of read requests responded to by this memory
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system.physmem.num_reads::total 660 # Number of read requests responded to by this memory
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system.physmem.bw_read::cpu0.inst 215658051 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu0.data 101486141 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.inst 47118566 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu1.data 12081684 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.inst 4832673 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu2.data 7853094 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu3.inst 1812253 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::cpu3.data 7853094 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_read::total 398695556 # Total read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu0.inst 215658051 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu1.inst 47118566 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu2.inst 4832673 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::cpu3.inst 1812253 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_inst_read::total 269421542 # Instruction read bandwidth from this memory (bytes/s)
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system.physmem.bw_total::cpu0.inst 215658051 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu0.data 101486141 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.inst 47118566 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu1.data 12081684 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.inst 4832673 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu2.data 7853094 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu3.inst 1812253 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::cpu3.data 7853094 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.bw_total::total 398695556 # Total bandwidth to/from this memory (bytes/s)
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system.physmem.readReqs 661 # Total number of read requests seen
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system.physmem.writeReqs 0 # Total number of write requests seen
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system.physmem.cpureqs 735 # Reqs generatd by CPU via cache - shady
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system.physmem.bytesRead 42240 # Total number of bytes read from memory
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system.physmem.bytesWritten 0 # Total number of bytes written to memory
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system.physmem.bytesConsumedRd 42240 # bytesRead derated as per pkt->getSize()
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system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
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system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
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system.physmem.neitherReadNorWrite 74 # Reqs where no action is needed
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system.physmem.perBankRdReqs::0 65 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::1 39 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::2 74 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::3 69 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 58 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::5 38 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::6 16 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::7 21 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::8 30 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::9 14 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 30 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::11 13 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::12 37 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::13 60 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::14 74 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::15 23 # Track reads on a per bank basis
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system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
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system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
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system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
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system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry
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system.physmem.totGap 105917500 # Total gap between requests
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system.physmem.readPktSize::0 0 # Categorize read packet sizes
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system.physmem.readPktSize::1 0 # Categorize read packet sizes
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system.physmem.readPktSize::2 0 # Categorize read packet sizes
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system.physmem.readPktSize::3 0 # Categorize read packet sizes
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system.physmem.readPktSize::4 0 # Categorize read packet sizes
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system.physmem.readPktSize::5 0 # Categorize read packet sizes
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system.physmem.readPktSize::6 661 # Categorize read packet sizes
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system.physmem.writePktSize::0 0 # Categorize write packet sizes
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system.physmem.writePktSize::1 0 # Categorize write packet sizes
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system.physmem.writePktSize::2 0 # Categorize write packet sizes
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system.physmem.writePktSize::3 0 # Categorize write packet sizes
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system.physmem.writePktSize::4 0 # Categorize write packet sizes
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system.physmem.writePktSize::5 0 # Categorize write packet sizes
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system.physmem.writePktSize::6 0 # Categorize write packet sizes
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system.physmem.rdQLenPdf::0 378 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::1 204 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::2 59 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
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system.physmem.totQLat 4080500 # Total cycles spent in queuing delays
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system.physmem.totMemAccLat 20695500 # Sum of mem lat for all requests
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system.physmem.totBusLat 3305000 # Total cycles spent in databus access
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system.physmem.totBankLat 13310000 # Total cycles spent in bank access
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system.physmem.avgQLat 6173.22 # Average queueing delay per request
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system.physmem.avgBankLat 20136.16 # Average bank access latency per request
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system.physmem.avgBusLat 5000.00 # Average bus latency per request
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system.physmem.avgMemAccLat 31309.38 # Average memory access latency
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system.physmem.avgRdBW 398.70 # Average achieved read bandwidth in MB/s
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system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s
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system.physmem.avgConsumedRdBW 398.70 # Average consumed read bandwidth in MB/s
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system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
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system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
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system.physmem.busUtil 3.11 # Data bus utilization in percentage
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system.physmem.avgRdQLen 0.19 # Average read queue length over time
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system.physmem.avgWrQLen 0.00 # Average write queue length over time
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system.physmem.readRowHits 465 # Number of row buffer hits during reads
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system.physmem.writeRowHits 0 # Number of row buffer hits during writes
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system.physmem.readRowHitRate 70.35 # Row buffer hit rate for reads
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system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
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system.physmem.avgGap 160238.28 # Average gap between requests
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system.cpu0.branchPred.lookups 82343 # Number of BP lookups
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system.cpu0.branchPred.condPredicted 80122 # Number of conditional branches predicted
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system.cpu0.branchPred.condIncorrect 1236 # Number of conditional branches incorrect
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system.cpu0.branchPred.BTBLookups 79627 # Number of BTB lookups
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system.cpu0.branchPred.BTBHits 77569 # Number of BTB hits
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system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
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system.cpu0.branchPred.BTBHitPct 97.415450 # BTB Hit Percentage
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system.cpu0.branchPred.usedRAS 525 # Number of times the RAS was used to get a target.
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system.cpu0.branchPred.RASInCorrect 132 # Number of incorrect RAS predictions.
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system.cpu0.workload.num_syscalls 89 # Number of system calls
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system.cpu0.numCycles 211892 # number of cpu cycles simulated
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system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
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system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu0.fetch.icacheStallCycles 17012 # Number of cycles fetch is stalled on an Icache miss
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system.cpu0.fetch.Insts 488761 # Number of instructions fetch has processed
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system.cpu0.fetch.Branches 82343 # Number of branches that fetch encountered
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system.cpu0.fetch.predictedBranches 78094 # Number of branches that fetch has predicted taken
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system.cpu0.fetch.Cycles 160351 # Number of cycles fetch has run and was not squashing or blocked
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system.cpu0.fetch.SquashCycles 3870 # Number of cycles fetch has spent squashing
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system.cpu0.fetch.BlockedCycles 13040 # Number of cycles fetch has spent blocked
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system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
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system.cpu0.fetch.PendingTrapStallCycles 1377 # Number of stall cycles due to pending traps
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system.cpu0.fetch.CacheLines 5901 # Number of cache lines fetched
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system.cpu0.fetch.IcacheSquashes 484 # Number of outstanding Icache misses that were squashed
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system.cpu0.fetch.rateDist::samples 194270 # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::mean 2.515885 # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::stdev 2.216000 # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::0 33919 17.46% 17.46% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::1 79392 40.87% 58.33% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::2 605 0.31% 58.64% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::3 996 0.51% 59.15% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::4 467 0.24% 59.39% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::5 75436 38.83% 98.22% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::6 571 0.29% 98.52% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::7 375 0.19% 98.71% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::8 2509 1.29% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.rateDist::total 194270 # Number of instructions fetched each cycle (Total)
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system.cpu0.fetch.branchRate 0.388608 # Number of branch fetches per cycle
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system.cpu0.fetch.rate 2.306652 # Number of inst fetches per cycle
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system.cpu0.decode.IdleCycles 17669 # Number of cycles decode is idle
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system.cpu0.decode.BlockedCycles 14482 # Number of cycles decode is blocked
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system.cpu0.decode.RunCycles 159353 # Number of cycles decode is running
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system.cpu0.decode.UnblockCycles 281 # Number of cycles decode is unblocking
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system.cpu0.decode.SquashCycles 2485 # Number of cycles decode is squashing
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system.cpu0.decode.DecodedInsts 485695 # Number of instructions handled by decode
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system.cpu0.rename.SquashCycles 2485 # Number of cycles rename is squashing
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system.cpu0.rename.IdleCycles 18316 # Number of cycles rename is idle
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system.cpu0.rename.BlockCycles 722 # Number of cycles rename is blocking
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system.cpu0.rename.serializeStallCycles 13165 # count of cycles rename stalled for serializing inst
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system.cpu0.rename.RunCycles 159020 # Number of cycles rename is running
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system.cpu0.rename.UnblockCycles 562 # Number of cycles rename is unblocking
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system.cpu0.rename.RenamedInsts 482913 # Number of instructions processed by rename
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system.cpu0.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full
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system.cpu0.rename.LSQFullEvents 156 # Number of times rename has blocked due to LSQ full
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system.cpu0.rename.RenamedOperands 330456 # Number of destination operands rename has renamed
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system.cpu0.rename.RenameLookups 963041 # Number of register rename lookups that rename has made
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system.cpu0.rename.int_rename_lookups 963041 # Number of integer rename lookups
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system.cpu0.rename.CommittedMaps 316991 # Number of HB maps that are committed
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system.cpu0.rename.UndoneMaps 13465 # Number of HB maps that are undone due to squashing
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system.cpu0.rename.serializingInsts 886 # count of serializing insts renamed
|
|
system.cpu0.rename.tempSerializingInsts 906 # count of temporary serializing insts renamed
|
|
system.cpu0.rename.skidInsts 3563 # count of insts added to the skid buffer
|
|
system.cpu0.memDep0.insertedLoads 154365 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu0.memDep0.insertedStores 77987 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu0.memDep0.conflictingLoads 75234 # Number of conflicting loads.
|
|
system.cpu0.memDep0.conflictingStores 75049 # Number of conflicting stores.
|
|
system.cpu0.iq.iqInstsAdded 403722 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu0.iq.iqNonSpecInstsAdded 919 # Number of non-speculative instructions added to the IQ
|
|
system.cpu0.iq.iqInstsIssued 400870 # Number of instructions issued
|
|
system.cpu0.iq.iqSquashedInstsIssued 124 # Number of squashed instructions issued
|
|
system.cpu0.iq.iqSquashedInstsExamined 11014 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu0.iq.iqSquashedOperandsExamined 10026 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu0.iq.iqSquashedNonSpecRemoved 360 # Number of squashed non-spec instructions that were removed
|
|
system.cpu0.iq.issued_per_cycle::samples 194270 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::mean 2.063468 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::stdev 1.094328 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::0 33101 17.04% 17.04% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::1 4910 2.53% 19.57% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::2 77039 39.66% 59.22% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::3 76515 39.39% 98.61% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::4 1655 0.85% 99.46% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::5 696 0.36% 99.82% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::6 259 0.13% 99.95% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::7 77 0.04% 99.99% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::8 18 0.01% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu0.iq.issued_per_cycle::total 194270 # Number of insts issued each cycle
|
|
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntAlu 50 22.22% 22.22% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntMult 0 0.00% 22.22% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IntDiv 0 0.00% 22.22% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatAdd 0 0.00% 22.22% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatCmp 0 0.00% 22.22% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatCvt 0 0.00% 22.22% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatMult 0 0.00% 22.22% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatDiv 0 0.00% 22.22% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 22.22% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAdd 0 0.00% 22.22% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 22.22% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdAlu 0 0.00% 22.22% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdCmp 0 0.00% 22.22% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdCvt 0 0.00% 22.22% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMisc 0 0.00% 22.22% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMult 0 0.00% 22.22% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 22.22% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdShift 0 0.00% 22.22% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 22.22% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 22.22% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 22.22% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 22.22% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 22.22% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 22.22% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 22.22% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 22.22% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 22.22% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 22.22% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 22.22% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::MemRead 62 27.56% 49.78% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::MemWrite 113 50.22% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntAlu 169604 42.31% 42.31% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.31% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.31% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.31% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.31% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.31% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.31% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.31% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.31% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.31% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.31% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.31% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.31% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.31% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.31% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.31% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.31% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.31% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.31% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.31% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.31% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.31% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.31% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.31% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.31% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.31% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.31% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.31% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.31% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::MemRead 153865 38.38% 80.69% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::MemWrite 77401 19.31% 100.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu0.iq.FU_type_0::total 400870 # Type of FU issued
|
|
system.cpu0.iq.rate 1.891860 # Inst issue rate
|
|
system.cpu0.iq.fu_busy_cnt 225 # FU busy when requested
|
|
system.cpu0.iq.fu_busy_rate 0.000561 # FU busy rate (busy events/executed inst)
|
|
system.cpu0.iq.int_inst_queue_reads 996359 # Number of integer instruction queue reads
|
|
system.cpu0.iq.int_inst_queue_writes 415710 # Number of integer instruction queue writes
|
|
system.cpu0.iq.int_inst_queue_wakeup_accesses 399019 # Number of integer instruction queue wakeup accesses
|
|
system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
|
|
system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
|
|
system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
|
|
system.cpu0.iq.int_alu_accesses 401095 # Number of integer alu accesses
|
|
system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses
|
|
system.cpu0.iew.lsq.thread0.forwLoads 74761 # Number of loads that had data forwarded from stores
|
|
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu0.iew.lsq.thread0.squashedLoads 2280 # Number of loads squashed
|
|
system.cpu0.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu0.iew.lsq.thread0.memOrderViolation 55 # Number of memory ordering violations
|
|
system.cpu0.iew.lsq.thread0.squashedStores 1438 # Number of stores squashed
|
|
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
system.cpu0.iew.lsq.thread0.cacheBlocked 7 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu0.iew.iewSquashCycles 2485 # Number of cycles IEW is squashing
|
|
system.cpu0.iew.iewBlockCycles 453 # Number of cycles IEW is blocking
|
|
system.cpu0.iew.iewUnblockCycles 37 # Number of cycles IEW is unblocking
|
|
system.cpu0.iew.iewDispatchedInsts 480419 # Number of instructions dispatched to IQ
|
|
system.cpu0.iew.iewDispSquashedInsts 309 # Number of squashed instructions skipped by dispatch
|
|
system.cpu0.iew.iewDispLoadInsts 154365 # Number of dispatched load instructions
|
|
system.cpu0.iew.iewDispStoreInsts 77987 # Number of dispatched store instructions
|
|
system.cpu0.iew.iewDispNonSpecInsts 807 # Number of dispatched non-speculative instructions
|
|
system.cpu0.iew.iewIQFullEvents 40 # Number of times the IQ has become full, causing a stall
|
|
system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu0.iew.memOrderViolationEvents 55 # Number of memory order violations
|
|
system.cpu0.iew.predictedTakenIncorrect 346 # Number of branches that were predicted taken incorrectly
|
|
system.cpu0.iew.predictedNotTakenIncorrect 1112 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu0.iew.branchMispredicts 1458 # Number of branch mispredicts detected at execute
|
|
system.cpu0.iew.iewExecutedInsts 399786 # Number of executed instructions
|
|
system.cpu0.iew.iewExecLoadInsts 153534 # Number of load instructions executed
|
|
system.cpu0.iew.iewExecSquashedInsts 1084 # Number of squashed instructions skipped in execute
|
|
system.cpu0.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu0.iew.exec_nop 75778 # number of nop insts executed
|
|
system.cpu0.iew.exec_refs 230828 # number of memory reference insts executed
|
|
system.cpu0.iew.exec_branches 79388 # Number of branches executed
|
|
system.cpu0.iew.exec_stores 77294 # Number of stores executed
|
|
system.cpu0.iew.exec_rate 1.886744 # Inst execution rate
|
|
system.cpu0.iew.wb_sent 399367 # cumulative count of insts sent to commit
|
|
system.cpu0.iew.wb_count 399019 # cumulative count of insts written-back
|
|
system.cpu0.iew.wb_producers 236486 # num instructions producing a value
|
|
system.cpu0.iew.wb_consumers 239045 # num instructions consuming a value
|
|
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu0.iew.wb_rate 1.883124 # insts written-back per cycle
|
|
system.cpu0.iew.wb_fanout 0.989295 # average fanout of values written-back
|
|
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu0.commit.commitSquashedInsts 12546 # The number of squashed insts skipped by commit
|
|
system.cpu0.commit.commitNonSpecStalls 559 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu0.commit.branchMispredicts 1236 # The number of times a branch was mispredicted
|
|
system.cpu0.commit.committed_per_cycle::samples 191785 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::mean 2.439388 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::stdev 2.136415 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::0 33586 17.51% 17.51% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::1 79020 41.20% 58.71% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::2 2366 1.23% 59.95% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::3 689 0.36% 60.31% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::4 531 0.28% 60.58% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::5 74531 38.86% 99.45% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::6 504 0.26% 99.71% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::7 248 0.13% 99.84% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::8 310 0.16% 100.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu0.commit.committed_per_cycle::total 191785 # Number of insts commited each cycle
|
|
system.cpu0.commit.committedInsts 467838 # Number of instructions committed
|
|
system.cpu0.commit.committedOps 467838 # Number of ops (including micro ops) committed
|
|
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu0.commit.refs 228634 # Number of memory references committed
|
|
system.cpu0.commit.loads 152085 # Number of loads committed
|
|
system.cpu0.commit.membars 84 # Number of memory barriers committed
|
|
system.cpu0.commit.branches 78436 # Number of branches committed
|
|
system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions.
|
|
system.cpu0.commit.int_insts 315322 # Number of committed integer instructions.
|
|
system.cpu0.commit.function_calls 223 # Number of function calls committed.
|
|
system.cpu0.commit.bw_lim_events 310 # number cycles where commit BW limit reached
|
|
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu0.rob.rob_reads 670698 # The number of ROB reads
|
|
system.cpu0.rob.rob_writes 963274 # The number of ROB writes
|
|
system.cpu0.timesIdled 319 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu0.idleCycles 17622 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu0.committedInsts 392586 # Number of Instructions Simulated
|
|
system.cpu0.committedOps 392586 # Number of Ops (including micro ops) Simulated
|
|
system.cpu0.committedInsts_total 392586 # Number of Instructions Simulated
|
|
system.cpu0.cpi 0.539734 # CPI: Cycles Per Instruction
|
|
system.cpu0.cpi_total 0.539734 # CPI: Total CPI of All Threads
|
|
system.cpu0.ipc 1.852765 # IPC: Instructions Per Cycle
|
|
system.cpu0.ipc_total 1.852765 # IPC: Total IPC of All Threads
|
|
system.cpu0.int_regfile_reads 715161 # number of integer regfile reads
|
|
system.cpu0.int_regfile_writes 322387 # number of integer regfile writes
|
|
system.cpu0.fp_regfile_reads 192 # number of floating regfile reads
|
|
system.cpu0.misc_regfile_reads 232651 # number of misc regfile reads
|
|
system.cpu0.misc_regfile_writes 564 # number of misc regfile writes
|
|
system.cpu0.icache.replacements 298 # number of replacements
|
|
system.cpu0.icache.tagsinuse 245.594499 # Cycle average of tags in use
|
|
system.cpu0.icache.total_refs 5155 # Total number of references to valid blocks.
|
|
system.cpu0.icache.sampled_refs 589 # Sample count of references to valid blocks.
|
|
system.cpu0.icache.avg_refs 8.752122 # Average number of references to valid blocks.
|
|
system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.icache.occ_blocks::cpu0.inst 245.594499 # Average occupied blocks per requestor
|
|
system.cpu0.icache.occ_percent::cpu0.inst 0.479677 # Average percentage of cache occupancy
|
|
system.cpu0.icache.occ_percent::total 0.479677 # Average percentage of cache occupancy
|
|
system.cpu0.icache.ReadReq_hits::cpu0.inst 5155 # number of ReadReq hits
|
|
system.cpu0.icache.ReadReq_hits::total 5155 # number of ReadReq hits
|
|
system.cpu0.icache.demand_hits::cpu0.inst 5155 # number of demand (read+write) hits
|
|
system.cpu0.icache.demand_hits::total 5155 # number of demand (read+write) hits
|
|
system.cpu0.icache.overall_hits::cpu0.inst 5155 # number of overall hits
|
|
system.cpu0.icache.overall_hits::total 5155 # number of overall hits
|
|
system.cpu0.icache.ReadReq_misses::cpu0.inst 746 # number of ReadReq misses
|
|
system.cpu0.icache.ReadReq_misses::total 746 # number of ReadReq misses
|
|
system.cpu0.icache.demand_misses::cpu0.inst 746 # number of demand (read+write) misses
|
|
system.cpu0.icache.demand_misses::total 746 # number of demand (read+write) misses
|
|
system.cpu0.icache.overall_misses::cpu0.inst 746 # number of overall misses
|
|
system.cpu0.icache.overall_misses::total 746 # number of overall misses
|
|
system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 26567000 # number of ReadReq miss cycles
|
|
system.cpu0.icache.ReadReq_miss_latency::total 26567000 # number of ReadReq miss cycles
|
|
system.cpu0.icache.demand_miss_latency::cpu0.inst 26567000 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.demand_miss_latency::total 26567000 # number of demand (read+write) miss cycles
|
|
system.cpu0.icache.overall_miss_latency::cpu0.inst 26567000 # number of overall miss cycles
|
|
system.cpu0.icache.overall_miss_latency::total 26567000 # number of overall miss cycles
|
|
system.cpu0.icache.ReadReq_accesses::cpu0.inst 5901 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.ReadReq_accesses::total 5901 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.icache.demand_accesses::cpu0.inst 5901 # number of demand (read+write) accesses
|
|
system.cpu0.icache.demand_accesses::total 5901 # number of demand (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::cpu0.inst 5901 # number of overall (read+write) accesses
|
|
system.cpu0.icache.overall_accesses::total 5901 # number of overall (read+write) accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.126419 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_miss_rate::total 0.126419 # miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.126419 # miss rate for demand accesses
|
|
system.cpu0.icache.demand_miss_rate::total 0.126419 # miss rate for demand accesses
|
|
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.126419 # miss rate for overall accesses
|
|
system.cpu0.icache.overall_miss_rate::total 0.126419 # miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 35612.600536 # average ReadReq miss latency
|
|
system.cpu0.icache.ReadReq_avg_miss_latency::total 35612.600536 # average ReadReq miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 35612.600536 # average overall miss latency
|
|
system.cpu0.icache.demand_avg_miss_latency::total 35612.600536 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 35612.600536 # average overall miss latency
|
|
system.cpu0.icache.overall_avg_miss_latency::total 35612.600536 # average overall miss latency
|
|
system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 156 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_hits::total 156 # number of ReadReq MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::cpu0.inst 156 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.demand_mshr_hits::total 156 # number of demand (read+write) MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::cpu0.inst 156 # number of overall MSHR hits
|
|
system.cpu0.icache.overall_mshr_hits::total 156 # number of overall MSHR hits
|
|
system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 590 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_misses::total 590 # number of ReadReq MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::cpu0.inst 590 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.demand_mshr_misses::total 590 # number of demand (read+write) MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::cpu0.inst 590 # number of overall MSHR misses
|
|
system.cpu0.icache.overall_mshr_misses::total 590 # number of overall MSHR misses
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 21166500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_latency::total 21166500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 21166500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.demand_mshr_miss_latency::total 21166500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 21166500 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.overall_mshr_miss_latency::total 21166500 # number of overall MSHR miss cycles
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.099983 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.099983 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.099983 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.demand_mshr_miss_rate::total 0.099983 # mshr miss rate for demand accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.099983 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.overall_mshr_miss_rate::total 0.099983 # mshr miss rate for overall accesses
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 35875.423729 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 35875.423729 # average ReadReq mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 35875.423729 # average overall mshr miss latency
|
|
system.cpu0.icache.demand_avg_mshr_miss_latency::total 35875.423729 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 35875.423729 # average overall mshr miss latency
|
|
system.cpu0.icache.overall_avg_mshr_miss_latency::total 35875.423729 # average overall mshr miss latency
|
|
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu0.dcache.replacements 2 # number of replacements
|
|
system.cpu0.dcache.tagsinuse 143.449906 # Cycle average of tags in use
|
|
system.cpu0.dcache.total_refs 154093 # Total number of references to valid blocks.
|
|
system.cpu0.dcache.sampled_refs 170 # Sample count of references to valid blocks.
|
|
system.cpu0.dcache.avg_refs 906.429412 # Average number of references to valid blocks.
|
|
system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu0.dcache.occ_blocks::cpu0.data 143.449906 # Average occupied blocks per requestor
|
|
system.cpu0.dcache.occ_percent::cpu0.data 0.280176 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.occ_percent::total 0.280176 # Average percentage of cache occupancy
|
|
system.cpu0.dcache.ReadReq_hits::cpu0.data 78219 # number of ReadReq hits
|
|
system.cpu0.dcache.ReadReq_hits::total 78219 # number of ReadReq hits
|
|
system.cpu0.dcache.WriteReq_hits::cpu0.data 75963 # number of WriteReq hits
|
|
system.cpu0.dcache.WriteReq_hits::total 75963 # number of WriteReq hits
|
|
system.cpu0.dcache.SwapReq_hits::cpu0.data 21 # number of SwapReq hits
|
|
system.cpu0.dcache.SwapReq_hits::total 21 # number of SwapReq hits
|
|
system.cpu0.dcache.demand_hits::cpu0.data 154182 # number of demand (read+write) hits
|
|
system.cpu0.dcache.demand_hits::total 154182 # number of demand (read+write) hits
|
|
system.cpu0.dcache.overall_hits::cpu0.data 154182 # number of overall hits
|
|
system.cpu0.dcache.overall_hits::total 154182 # number of overall hits
|
|
system.cpu0.dcache.ReadReq_misses::cpu0.data 475 # number of ReadReq misses
|
|
system.cpu0.dcache.ReadReq_misses::total 475 # number of ReadReq misses
|
|
system.cpu0.dcache.WriteReq_misses::cpu0.data 544 # number of WriteReq misses
|
|
system.cpu0.dcache.WriteReq_misses::total 544 # number of WriteReq misses
|
|
system.cpu0.dcache.SwapReq_misses::cpu0.data 21 # number of SwapReq misses
|
|
system.cpu0.dcache.SwapReq_misses::total 21 # number of SwapReq misses
|
|
system.cpu0.dcache.demand_misses::cpu0.data 1019 # number of demand (read+write) misses
|
|
system.cpu0.dcache.demand_misses::total 1019 # number of demand (read+write) misses
|
|
system.cpu0.dcache.overall_misses::cpu0.data 1019 # number of overall misses
|
|
system.cpu0.dcache.overall_misses::total 1019 # number of overall misses
|
|
system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 11954500 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.ReadReq_miss_latency::total 11954500 # number of ReadReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 24681495 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.WriteReq_miss_latency::total 24681495 # number of WriteReq miss cycles
|
|
system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 599500 # number of SwapReq miss cycles
|
|
system.cpu0.dcache.SwapReq_miss_latency::total 599500 # number of SwapReq miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::cpu0.data 36635995 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.demand_miss_latency::total 36635995 # number of demand (read+write) miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::cpu0.data 36635995 # number of overall miss cycles
|
|
system.cpu0.dcache.overall_miss_latency::total 36635995 # number of overall miss cycles
|
|
system.cpu0.dcache.ReadReq_accesses::cpu0.data 78694 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.ReadReq_accesses::total 78694 # number of ReadReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::cpu0.data 76507 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.WriteReq_accesses::total 76507 # number of WriteReq accesses(hits+misses)
|
|
system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 # number of SwapReq accesses(hits+misses)
|
|
system.cpu0.dcache.SwapReq_accesses::total 42 # number of SwapReq accesses(hits+misses)
|
|
system.cpu0.dcache.demand_accesses::cpu0.data 155201 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.demand_accesses::total 155201 # number of demand (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::cpu0.data 155201 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.overall_accesses::total 155201 # number of overall (read+write) accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006036 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_miss_rate::total 0.006036 # miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.007110 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_miss_rate::total 0.007110 # miss rate for WriteReq accesses
|
|
system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.500000 # miss rate for SwapReq accesses
|
|
system.cpu0.dcache.SwapReq_miss_rate::total 0.500000 # miss rate for SwapReq accesses
|
|
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006566 # miss rate for demand accesses
|
|
system.cpu0.dcache.demand_miss_rate::total 0.006566 # miss rate for demand accesses
|
|
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006566 # miss rate for overall accesses
|
|
system.cpu0.dcache.overall_miss_rate::total 0.006566 # miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 25167.368421 # average ReadReq miss latency
|
|
system.cpu0.dcache.ReadReq_avg_miss_latency::total 25167.368421 # average ReadReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 45370.395221 # average WriteReq miss latency
|
|
system.cpu0.dcache.WriteReq_avg_miss_latency::total 45370.395221 # average WriteReq miss latency
|
|
system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 28547.619048 # average SwapReq miss latency
|
|
system.cpu0.dcache.SwapReq_avg_miss_latency::total 28547.619048 # average SwapReq miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 35952.890088 # average overall miss latency
|
|
system.cpu0.dcache.demand_avg_miss_latency::total 35952.890088 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 35952.890088 # average overall miss latency
|
|
system.cpu0.dcache.overall_avg_miss_latency::total 35952.890088 # average overall miss latency
|
|
system.cpu0.dcache.blocked_cycles::no_mshrs 184 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_mshrs 14 # number of cycles access was blocked
|
|
system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 13.142857 # average number of cycles each access was blocked
|
|
system.cpu0.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu0.dcache.writebacks::writebacks 1 # number of writebacks
|
|
system.cpu0.dcache.writebacks::total 1 # number of writebacks
|
|
system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 286 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_hits::total 286 # number of ReadReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 373 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.WriteReq_mshr_hits::total 373 # number of WriteReq MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::cpu0.data 659 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.demand_mshr_hits::total 659 # number of demand (read+write) MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::cpu0.data 659 # number of overall MSHR hits
|
|
system.cpu0.dcache.overall_mshr_hits::total 659 # number of overall MSHR hits
|
|
system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 189 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_misses::total 189 # number of ReadReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 171 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.WriteReq_mshr_misses::total 171 # number of WriteReq MSHR misses
|
|
system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 21 # number of SwapReq MSHR misses
|
|
system.cpu0.dcache.SwapReq_mshr_misses::total 21 # number of SwapReq MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::cpu0.data 360 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.demand_mshr_misses::total 360 # number of demand (read+write) MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::cpu0.data 360 # number of overall MSHR misses
|
|
system.cpu0.dcache.overall_mshr_misses::total 360 # number of overall MSHR misses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 5407500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 5407500 # number of ReadReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 5740000 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 5740000 # number of WriteReq MSHR miss cycles
|
|
system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 557500 # number of SwapReq MSHR miss cycles
|
|
system.cpu0.dcache.SwapReq_mshr_miss_latency::total 557500 # number of SwapReq MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 11147500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.demand_mshr_miss_latency::total 11147500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 11147500 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.overall_mshr_miss_latency::total 11147500 # number of overall MSHR miss cycles
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002402 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002402 # mshr miss rate for ReadReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.002235 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.002235 # mshr miss rate for WriteReq accesses
|
|
system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for SwapReq accesses
|
|
system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.500000 # mshr miss rate for SwapReq accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002320 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.demand_mshr_miss_rate::total 0.002320 # mshr miss rate for demand accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002320 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.overall_mshr_miss_rate::total 0.002320 # mshr miss rate for overall accesses
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 28611.111111 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 28611.111111 # average ReadReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 33567.251462 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 33567.251462 # average WriteReq mshr miss latency
|
|
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 26547.619048 # average SwapReq mshr miss latency
|
|
system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 26547.619048 # average SwapReq mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 30965.277778 # average overall mshr miss latency
|
|
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 30965.277778 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 30965.277778 # average overall mshr miss latency
|
|
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 30965.277778 # average overall mshr miss latency
|
|
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.branchPred.lookups 56473 # Number of BP lookups
|
|
system.cpu1.branchPred.condPredicted 53777 # Number of conditional branches predicted
|
|
system.cpu1.branchPred.condIncorrect 1278 # Number of conditional branches incorrect
|
|
system.cpu1.branchPred.BTBLookups 50438 # Number of BTB lookups
|
|
system.cpu1.branchPred.BTBHits 49675 # Number of BTB hits
|
|
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu1.branchPred.BTBHitPct 98.487252 # BTB Hit Percentage
|
|
system.cpu1.branchPred.usedRAS 680 # Number of times the RAS was used to get a target.
|
|
system.cpu1.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions.
|
|
system.cpu1.numCycles 175078 # number of cpu cycles simulated
|
|
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu1.fetch.icacheStallCycles 25485 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu1.fetch.Insts 320653 # Number of instructions fetch has processed
|
|
system.cpu1.fetch.Branches 56473 # Number of branches that fetch encountered
|
|
system.cpu1.fetch.predictedBranches 50355 # Number of branches that fetch has predicted taken
|
|
system.cpu1.fetch.Cycles 109933 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu1.fetch.SquashCycles 3703 # Number of cycles fetch has spent squashing
|
|
system.cpu1.fetch.BlockedCycles 25650 # Number of cycles fetch has spent blocked
|
|
system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu1.fetch.NoActiveThreadStallCycles 6381 # Number of stall cycles due to no active thread to fetch from
|
|
system.cpu1.fetch.PendingTrapStallCycles 795 # Number of stall cycles due to pending traps
|
|
system.cpu1.fetch.CacheLines 16660 # Number of cache lines fetched
|
|
system.cpu1.fetch.IcacheSquashes 263 # Number of outstanding Icache misses that were squashed
|
|
system.cpu1.fetch.rateDist::samples 170597 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::mean 1.879593 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::stdev 2.199930 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::0 60664 35.56% 35.56% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::1 55109 32.30% 67.86% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::2 4624 2.71% 70.57% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::3 3194 1.87% 72.45% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::4 685 0.40% 72.85% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::5 41191 24.15% 96.99% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::6 1119 0.66% 97.65% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::7 783 0.46% 98.11% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::8 3228 1.89% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.rateDist::total 170597 # Number of instructions fetched each cycle (Total)
|
|
system.cpu1.fetch.branchRate 0.322559 # Number of branch fetches per cycle
|
|
system.cpu1.fetch.rate 1.831487 # Number of inst fetches per cycle
|
|
system.cpu1.decode.IdleCycles 29160 # Number of cycles decode is idle
|
|
system.cpu1.decode.BlockedCycles 23609 # Number of cycles decode is blocked
|
|
system.cpu1.decode.RunCycles 105420 # Number of cycles decode is running
|
|
system.cpu1.decode.UnblockCycles 3678 # Number of cycles decode is unblocking
|
|
system.cpu1.decode.SquashCycles 2349 # Number of cycles decode is squashing
|
|
system.cpu1.decode.DecodedInsts 317245 # Number of instructions handled by decode
|
|
system.cpu1.rename.SquashCycles 2349 # Number of cycles rename is squashing
|
|
system.cpu1.rename.IdleCycles 29851 # Number of cycles rename is idle
|
|
system.cpu1.rename.BlockCycles 11179 # Number of cycles rename is blocking
|
|
system.cpu1.rename.serializeStallCycles 11654 # count of cycles rename stalled for serializing inst
|
|
system.cpu1.rename.RunCycles 102051 # Number of cycles rename is running
|
|
system.cpu1.rename.UnblockCycles 7132 # Number of cycles rename is unblocking
|
|
system.cpu1.rename.RenamedInsts 315250 # Number of instructions processed by rename
|
|
system.cpu1.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full
|
|
system.cpu1.rename.LSQFullEvents 41 # Number of times rename has blocked due to LSQ full
|
|
system.cpu1.rename.RenamedOperands 222317 # Number of destination operands rename has renamed
|
|
system.cpu1.rename.RenameLookups 613423 # Number of register rename lookups that rename has made
|
|
system.cpu1.rename.int_rename_lookups 613423 # Number of integer rename lookups
|
|
system.cpu1.rename.CommittedMaps 209500 # Number of HB maps that are committed
|
|
system.cpu1.rename.UndoneMaps 12817 # Number of HB maps that are undone due to squashing
|
|
system.cpu1.rename.serializingInsts 1100 # count of serializing insts renamed
|
|
system.cpu1.rename.tempSerializingInsts 1225 # count of temporary serializing insts renamed
|
|
system.cpu1.rename.skidInsts 9565 # count of insts added to the skid buffer
|
|
system.cpu1.memDep0.insertedLoads 91347 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu1.memDep0.insertedStores 44397 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu1.memDep0.conflictingLoads 43115 # Number of conflicting loads.
|
|
system.cpu1.memDep0.conflictingStores 39365 # Number of conflicting stores.
|
|
system.cpu1.iq.iqInstsAdded 263703 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu1.iq.iqNonSpecInstsAdded 4783 # Number of non-speculative instructions added to the IQ
|
|
system.cpu1.iq.iqInstsIssued 264442 # Number of instructions issued
|
|
system.cpu1.iq.iqSquashedInstsIssued 134 # Number of squashed instructions issued
|
|
system.cpu1.iq.iqSquashedInstsExamined 10738 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu1.iq.iqSquashedOperandsExamined 10286 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu1.iq.iqSquashedNonSpecRemoved 531 # Number of squashed non-spec instructions that were removed
|
|
system.cpu1.iq.issued_per_cycle::samples 170597 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::mean 1.550098 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::stdev 1.309842 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::0 57935 33.96% 33.96% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::1 18114 10.62% 44.58% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::2 44440 26.05% 70.63% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::3 45139 26.46% 97.09% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::4 3372 1.98% 99.06% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::5 1210 0.71% 99.77% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::6 275 0.16% 99.93% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::7 53 0.03% 99.97% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu1.iq.issued_per_cycle::total 170597 # Number of insts issued each cycle
|
|
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntAlu 17 5.80% 5.80% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntMult 0 0.00% 5.80% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IntDiv 0 0.00% 5.80% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatAdd 0 0.00% 5.80% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatCmp 0 0.00% 5.80% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatCvt 0 0.00% 5.80% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatMult 0 0.00% 5.80% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatDiv 0 0.00% 5.80% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 5.80% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAdd 0 0.00% 5.80% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 5.80% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdAlu 0 0.00% 5.80% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdCmp 0 0.00% 5.80% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdCvt 0 0.00% 5.80% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMisc 0 0.00% 5.80% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMult 0 0.00% 5.80% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 5.80% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdShift 0 0.00% 5.80% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 5.80% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 5.80% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 5.80% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 5.80% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 5.80% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 5.80% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 5.80% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 5.80% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 5.80% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.80% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 5.80% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::MemRead 66 22.53% 28.33% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::MemWrite 210 71.67% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntAlu 126483 47.83% 47.83% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntMult 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.83% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::MemRead 94216 35.63% 83.46% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::MemWrite 43743 16.54% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu1.iq.FU_type_0::total 264442 # Type of FU issued
|
|
system.cpu1.iq.rate 1.510424 # Inst issue rate
|
|
system.cpu1.iq.fu_busy_cnt 293 # FU busy when requested
|
|
system.cpu1.iq.fu_busy_rate 0.001108 # FU busy rate (busy events/executed inst)
|
|
system.cpu1.iq.int_inst_queue_reads 699908 # Number of integer instruction queue reads
|
|
system.cpu1.iq.int_inst_queue_writes 279269 # Number of integer instruction queue writes
|
|
system.cpu1.iq.int_inst_queue_wakeup_accesses 262662 # Number of integer instruction queue wakeup accesses
|
|
system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
|
|
system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
|
|
system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
|
|
system.cpu1.iq.int_alu_accesses 264735 # Number of integer alu accesses
|
|
system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses
|
|
system.cpu1.iew.lsq.thread0.forwLoads 39130 # Number of loads that had data forwarded from stores
|
|
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu1.iew.lsq.thread0.squashedLoads 2377 # Number of loads squashed
|
|
system.cpu1.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu1.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations
|
|
system.cpu1.iew.lsq.thread0.squashedStores 1437 # Number of stores squashed
|
|
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu1.iew.iewSquashCycles 2349 # Number of cycles IEW is squashing
|
|
system.cpu1.iew.iewBlockCycles 1341 # Number of cycles IEW is blocking
|
|
system.cpu1.iew.iewUnblockCycles 64 # Number of cycles IEW is unblocking
|
|
system.cpu1.iew.iewDispatchedInsts 312497 # Number of instructions dispatched to IQ
|
|
system.cpu1.iew.iewDispSquashedInsts 345 # Number of squashed instructions skipped by dispatch
|
|
system.cpu1.iew.iewDispLoadInsts 91347 # Number of dispatched load instructions
|
|
system.cpu1.iew.iewDispStoreInsts 44397 # Number of dispatched store instructions
|
|
system.cpu1.iew.iewDispNonSpecInsts 1061 # Number of dispatched non-speculative instructions
|
|
system.cpu1.iew.iewIQFullEvents 64 # Number of times the IQ has become full, causing a stall
|
|
system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu1.iew.memOrderViolationEvents 45 # Number of memory order violations
|
|
system.cpu1.iew.predictedTakenIncorrect 459 # Number of branches that were predicted taken incorrectly
|
|
system.cpu1.iew.predictedNotTakenIncorrect 950 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu1.iew.branchMispredicts 1409 # Number of branch mispredicts detected at execute
|
|
system.cpu1.iew.iewExecutedInsts 263311 # Number of executed instructions
|
|
system.cpu1.iew.iewExecLoadInsts 90404 # Number of load instructions executed
|
|
system.cpu1.iew.iewExecSquashedInsts 1131 # Number of squashed instructions skipped in execute
|
|
system.cpu1.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu1.iew.exec_nop 44011 # number of nop insts executed
|
|
system.cpu1.iew.exec_refs 134069 # number of memory reference insts executed
|
|
system.cpu1.iew.exec_branches 53318 # Number of branches executed
|
|
system.cpu1.iew.exec_stores 43665 # Number of stores executed
|
|
system.cpu1.iew.exec_rate 1.503964 # Inst execution rate
|
|
system.cpu1.iew.wb_sent 262943 # cumulative count of insts sent to commit
|
|
system.cpu1.iew.wb_count 262662 # cumulative count of insts written-back
|
|
system.cpu1.iew.wb_producers 150856 # num instructions producing a value
|
|
system.cpu1.iew.wb_consumers 155566 # num instructions consuming a value
|
|
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu1.iew.wb_rate 1.500257 # insts written-back per cycle
|
|
system.cpu1.iew.wb_fanout 0.969723 # average fanout of values written-back
|
|
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu1.commit.commitSquashedInsts 12295 # The number of squashed insts skipped by commit
|
|
system.cpu1.commit.commitNonSpecStalls 4252 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu1.commit.branchMispredicts 1278 # The number of times a branch was mispredicted
|
|
system.cpu1.commit.committed_per_cycle::samples 161867 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::mean 1.854590 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::stdev 2.083667 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::0 55765 34.45% 34.45% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::1 51311 31.70% 66.15% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::2 6076 3.75% 69.90% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::3 5204 3.21% 73.12% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::4 1553 0.96% 74.08% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::5 39486 24.39% 98.47% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::6 647 0.40% 98.87% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::7 1002 0.62% 99.49% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::8 823 0.51% 100.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu1.commit.committed_per_cycle::total 161867 # Number of insts commited each cycle
|
|
system.cpu1.commit.committedInsts 300197 # Number of instructions committed
|
|
system.cpu1.commit.committedOps 300197 # Number of ops (including micro ops) committed
|
|
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu1.commit.refs 131930 # Number of memory references committed
|
|
system.cpu1.commit.loads 88970 # Number of loads committed
|
|
system.cpu1.commit.membars 3544 # Number of memory barriers committed
|
|
system.cpu1.commit.branches 52469 # Number of branches committed
|
|
system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions.
|
|
system.cpu1.commit.int_insts 206526 # Number of committed integer instructions.
|
|
system.cpu1.commit.function_calls 322 # Number of function calls committed.
|
|
system.cpu1.commit.bw_lim_events 823 # number cycles where commit BW limit reached
|
|
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu1.rob.rob_reads 472949 # The number of ROB reads
|
|
system.cpu1.rob.rob_writes 627337 # The number of ROB writes
|
|
system.cpu1.timesIdled 228 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu1.idleCycles 4481 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu1.quiesceCycles 36812 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu1.committedInsts 253388 # Number of Instructions Simulated
|
|
system.cpu1.committedOps 253388 # Number of Ops (including micro ops) Simulated
|
|
system.cpu1.committedInsts_total 253388 # Number of Instructions Simulated
|
|
system.cpu1.cpi 0.690948 # CPI: Cycles Per Instruction
|
|
system.cpu1.cpi_total 0.690948 # CPI: Total CPI of All Threads
|
|
system.cpu1.ipc 1.447286 # IPC: Instructions Per Cycle
|
|
system.cpu1.ipc_total 1.447286 # IPC: Total IPC of All Threads
|
|
system.cpu1.int_regfile_reads 460976 # number of integer regfile reads
|
|
system.cpu1.int_regfile_writes 214498 # number of integer regfile writes
|
|
system.cpu1.fp_regfile_writes 64 # number of floating regfile writes
|
|
system.cpu1.misc_regfile_reads 135647 # number of misc regfile reads
|
|
system.cpu1.misc_regfile_writes 648 # number of misc regfile writes
|
|
system.cpu1.icache.replacements 317 # number of replacements
|
|
system.cpu1.icache.tagsinuse 85.226466 # Cycle average of tags in use
|
|
system.cpu1.icache.total_refs 16176 # Total number of references to valid blocks.
|
|
system.cpu1.icache.sampled_refs 425 # Sample count of references to valid blocks.
|
|
system.cpu1.icache.avg_refs 38.061176 # Average number of references to valid blocks.
|
|
system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.icache.occ_blocks::cpu1.inst 85.226466 # Average occupied blocks per requestor
|
|
system.cpu1.icache.occ_percent::cpu1.inst 0.166458 # Average percentage of cache occupancy
|
|
system.cpu1.icache.occ_percent::total 0.166458 # Average percentage of cache occupancy
|
|
system.cpu1.icache.ReadReq_hits::cpu1.inst 16176 # number of ReadReq hits
|
|
system.cpu1.icache.ReadReq_hits::total 16176 # number of ReadReq hits
|
|
system.cpu1.icache.demand_hits::cpu1.inst 16176 # number of demand (read+write) hits
|
|
system.cpu1.icache.demand_hits::total 16176 # number of demand (read+write) hits
|
|
system.cpu1.icache.overall_hits::cpu1.inst 16176 # number of overall hits
|
|
system.cpu1.icache.overall_hits::total 16176 # number of overall hits
|
|
system.cpu1.icache.ReadReq_misses::cpu1.inst 484 # number of ReadReq misses
|
|
system.cpu1.icache.ReadReq_misses::total 484 # number of ReadReq misses
|
|
system.cpu1.icache.demand_misses::cpu1.inst 484 # number of demand (read+write) misses
|
|
system.cpu1.icache.demand_misses::total 484 # number of demand (read+write) misses
|
|
system.cpu1.icache.overall_misses::cpu1.inst 484 # number of overall misses
|
|
system.cpu1.icache.overall_misses::total 484 # number of overall misses
|
|
system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 10452000 # number of ReadReq miss cycles
|
|
system.cpu1.icache.ReadReq_miss_latency::total 10452000 # number of ReadReq miss cycles
|
|
system.cpu1.icache.demand_miss_latency::cpu1.inst 10452000 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.demand_miss_latency::total 10452000 # number of demand (read+write) miss cycles
|
|
system.cpu1.icache.overall_miss_latency::cpu1.inst 10452000 # number of overall miss cycles
|
|
system.cpu1.icache.overall_miss_latency::total 10452000 # number of overall miss cycles
|
|
system.cpu1.icache.ReadReq_accesses::cpu1.inst 16660 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.ReadReq_accesses::total 16660 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.icache.demand_accesses::cpu1.inst 16660 # number of demand (read+write) accesses
|
|
system.cpu1.icache.demand_accesses::total 16660 # number of demand (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::cpu1.inst 16660 # number of overall (read+write) accesses
|
|
system.cpu1.icache.overall_accesses::total 16660 # number of overall (read+write) accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.029052 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_miss_rate::total 0.029052 # miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_miss_rate::cpu1.inst 0.029052 # miss rate for demand accesses
|
|
system.cpu1.icache.demand_miss_rate::total 0.029052 # miss rate for demand accesses
|
|
system.cpu1.icache.overall_miss_rate::cpu1.inst 0.029052 # miss rate for overall accesses
|
|
system.cpu1.icache.overall_miss_rate::total 0.029052 # miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 21595.041322 # average ReadReq miss latency
|
|
system.cpu1.icache.ReadReq_avg_miss_latency::total 21595.041322 # average ReadReq miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 21595.041322 # average overall miss latency
|
|
system.cpu1.icache.demand_avg_miss_latency::total 21595.041322 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 21595.041322 # average overall miss latency
|
|
system.cpu1.icache.overall_avg_miss_latency::total 21595.041322 # average overall miss latency
|
|
system.cpu1.icache.blocked_cycles::no_mshrs 44 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_mshrs 1 # number of cycles access was blocked
|
|
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_mshrs 44 # average number of cycles each access was blocked
|
|
system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 59 # number of ReadReq MSHR hits
|
|
system.cpu1.icache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits
|
|
system.cpu1.icache.demand_mshr_hits::cpu1.inst 59 # number of demand (read+write) MSHR hits
|
|
system.cpu1.icache.demand_mshr_hits::total 59 # number of demand (read+write) MSHR hits
|
|
system.cpu1.icache.overall_mshr_hits::cpu1.inst 59 # number of overall MSHR hits
|
|
system.cpu1.icache.overall_mshr_hits::total 59 # number of overall MSHR hits
|
|
system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 425 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_misses::total 425 # number of ReadReq MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::cpu1.inst 425 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.demand_mshr_misses::total 425 # number of demand (read+write) MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::cpu1.inst 425 # number of overall MSHR misses
|
|
system.cpu1.icache.overall_mshr_misses::total 425 # number of overall MSHR misses
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 8244000 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_latency::total 8244000 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 8244000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.demand_mshr_miss_latency::total 8244000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 8244000 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.overall_mshr_miss_latency::total 8244000 # number of overall MSHR miss cycles
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.025510 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.025510 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.025510 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.demand_mshr_miss_rate::total 0.025510 # mshr miss rate for demand accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.025510 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.overall_mshr_miss_rate::total 0.025510 # mshr miss rate for overall accesses
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 19397.647059 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 19397.647059 # average ReadReq mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 19397.647059 # average overall mshr miss latency
|
|
system.cpu1.icache.demand_avg_mshr_miss_latency::total 19397.647059 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 19397.647059 # average overall mshr miss latency
|
|
system.cpu1.icache.overall_avg_mshr_miss_latency::total 19397.647059 # average overall mshr miss latency
|
|
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu1.dcache.replacements 0 # number of replacements
|
|
system.cpu1.dcache.tagsinuse 27.077196 # Cycle average of tags in use
|
|
system.cpu1.dcache.total_refs 49103 # Total number of references to valid blocks.
|
|
system.cpu1.dcache.sampled_refs 29 # Sample count of references to valid blocks.
|
|
system.cpu1.dcache.avg_refs 1693.206897 # Average number of references to valid blocks.
|
|
system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu1.dcache.occ_blocks::cpu1.data 27.077196 # Average occupied blocks per requestor
|
|
system.cpu1.dcache.occ_percent::cpu1.data 0.052885 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.occ_percent::total 0.052885 # Average percentage of cache occupancy
|
|
system.cpu1.dcache.ReadReq_hits::cpu1.data 50842 # number of ReadReq hits
|
|
system.cpu1.dcache.ReadReq_hits::total 50842 # number of ReadReq hits
|
|
system.cpu1.dcache.WriteReq_hits::cpu1.data 42756 # number of WriteReq hits
|
|
system.cpu1.dcache.WriteReq_hits::total 42756 # number of WriteReq hits
|
|
system.cpu1.dcache.SwapReq_hits::cpu1.data 12 # number of SwapReq hits
|
|
system.cpu1.dcache.SwapReq_hits::total 12 # number of SwapReq hits
|
|
system.cpu1.dcache.demand_hits::cpu1.data 93598 # number of demand (read+write) hits
|
|
system.cpu1.dcache.demand_hits::total 93598 # number of demand (read+write) hits
|
|
system.cpu1.dcache.overall_hits::cpu1.data 93598 # number of overall hits
|
|
system.cpu1.dcache.overall_hits::total 93598 # number of overall hits
|
|
system.cpu1.dcache.ReadReq_misses::cpu1.data 415 # number of ReadReq misses
|
|
system.cpu1.dcache.ReadReq_misses::total 415 # number of ReadReq misses
|
|
system.cpu1.dcache.WriteReq_misses::cpu1.data 142 # number of WriteReq misses
|
|
system.cpu1.dcache.WriteReq_misses::total 142 # number of WriteReq misses
|
|
system.cpu1.dcache.SwapReq_misses::cpu1.data 50 # number of SwapReq misses
|
|
system.cpu1.dcache.SwapReq_misses::total 50 # number of SwapReq misses
|
|
system.cpu1.dcache.demand_misses::cpu1.data 557 # number of demand (read+write) misses
|
|
system.cpu1.dcache.demand_misses::total 557 # number of demand (read+write) misses
|
|
system.cpu1.dcache.overall_misses::cpu1.data 557 # number of overall misses
|
|
system.cpu1.dcache.overall_misses::total 557 # number of overall misses
|
|
system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 8012000 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.ReadReq_miss_latency::total 8012000 # number of ReadReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3190500 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.WriteReq_miss_latency::total 3190500 # number of WriteReq miss cycles
|
|
system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 514000 # number of SwapReq miss cycles
|
|
system.cpu1.dcache.SwapReq_miss_latency::total 514000 # number of SwapReq miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::cpu1.data 11202500 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.demand_miss_latency::total 11202500 # number of demand (read+write) miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::cpu1.data 11202500 # number of overall miss cycles
|
|
system.cpu1.dcache.overall_miss_latency::total 11202500 # number of overall miss cycles
|
|
system.cpu1.dcache.ReadReq_accesses::cpu1.data 51257 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.ReadReq_accesses::total 51257 # number of ReadReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::cpu1.data 42898 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.WriteReq_accesses::total 42898 # number of WriteReq accesses(hits+misses)
|
|
system.cpu1.dcache.SwapReq_accesses::cpu1.data 62 # number of SwapReq accesses(hits+misses)
|
|
system.cpu1.dcache.SwapReq_accesses::total 62 # number of SwapReq accesses(hits+misses)
|
|
system.cpu1.dcache.demand_accesses::cpu1.data 94155 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.demand_accesses::total 94155 # number of demand (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::cpu1.data 94155 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.overall_accesses::total 94155 # number of overall (read+write) accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.008096 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_miss_rate::total 0.008096 # miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.003310 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_miss_rate::total 0.003310 # miss rate for WriteReq accesses
|
|
system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.806452 # miss rate for SwapReq accesses
|
|
system.cpu1.dcache.SwapReq_miss_rate::total 0.806452 # miss rate for SwapReq accesses
|
|
system.cpu1.dcache.demand_miss_rate::cpu1.data 0.005916 # miss rate for demand accesses
|
|
system.cpu1.dcache.demand_miss_rate::total 0.005916 # miss rate for demand accesses
|
|
system.cpu1.dcache.overall_miss_rate::cpu1.data 0.005916 # miss rate for overall accesses
|
|
system.cpu1.dcache.overall_miss_rate::total 0.005916 # miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 19306.024096 # average ReadReq miss latency
|
|
system.cpu1.dcache.ReadReq_avg_miss_latency::total 19306.024096 # average ReadReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 22468.309859 # average WriteReq miss latency
|
|
system.cpu1.dcache.WriteReq_avg_miss_latency::total 22468.309859 # average WriteReq miss latency
|
|
system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 10280 # average SwapReq miss latency
|
|
system.cpu1.dcache.SwapReq_avg_miss_latency::total 10280 # average SwapReq miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 20112.208259 # average overall miss latency
|
|
system.cpu1.dcache.demand_avg_miss_latency::total 20112.208259 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 20112.208259 # average overall miss latency
|
|
system.cpu1.dcache.overall_avg_miss_latency::total 20112.208259 # average overall miss latency
|
|
system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 264 # number of ReadReq MSHR hits
|
|
system.cpu1.dcache.ReadReq_mshr_hits::total 264 # number of ReadReq MSHR hits
|
|
system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 34 # number of WriteReq MSHR hits
|
|
system.cpu1.dcache.WriteReq_mshr_hits::total 34 # number of WriteReq MSHR hits
|
|
system.cpu1.dcache.demand_mshr_hits::cpu1.data 298 # number of demand (read+write) MSHR hits
|
|
system.cpu1.dcache.demand_mshr_hits::total 298 # number of demand (read+write) MSHR hits
|
|
system.cpu1.dcache.overall_mshr_hits::cpu1.data 298 # number of overall MSHR hits
|
|
system.cpu1.dcache.overall_mshr_hits::total 298 # number of overall MSHR hits
|
|
system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 151 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_misses::total 151 # number of ReadReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 108 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.WriteReq_mshr_misses::total 108 # number of WriteReq MSHR misses
|
|
system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 50 # number of SwapReq MSHR misses
|
|
system.cpu1.dcache.SwapReq_mshr_misses::total 50 # number of SwapReq MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::cpu1.data 259 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.demand_mshr_misses::total 259 # number of demand (read+write) MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::cpu1.data 259 # number of overall MSHR misses
|
|
system.cpu1.dcache.overall_mshr_misses::total 259 # number of overall MSHR misses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1741000 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1741000 # number of ReadReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1514500 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1514500 # number of WriteReq MSHR miss cycles
|
|
system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 414000 # number of SwapReq MSHR miss cycles
|
|
system.cpu1.dcache.SwapReq_mshr_miss_latency::total 414000 # number of SwapReq MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3255500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.demand_mshr_miss_latency::total 3255500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3255500 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.overall_mshr_miss_latency::total 3255500 # number of overall MSHR miss cycles
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002946 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.002946 # mshr miss rate for ReadReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002518 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002518 # mshr miss rate for WriteReq accesses
|
|
system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.806452 # mshr miss rate for SwapReq accesses
|
|
system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.806452 # mshr miss rate for SwapReq accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.002751 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.demand_mshr_miss_rate::total 0.002751 # mshr miss rate for demand accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.002751 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.overall_mshr_miss_rate::total 0.002751 # mshr miss rate for overall accesses
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11529.801325 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 11529.801325 # average ReadReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14023.148148 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14023.148148 # average WriteReq mshr miss latency
|
|
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 8280 # average SwapReq mshr miss latency
|
|
system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 8280 # average SwapReq mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 12569.498069 # average overall mshr miss latency
|
|
system.cpu1.dcache.demand_avg_mshr_miss_latency::total 12569.498069 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 12569.498069 # average overall mshr miss latency
|
|
system.cpu1.dcache.overall_avg_mshr_miss_latency::total 12569.498069 # average overall mshr miss latency
|
|
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu2.branchPred.lookups 48435 # Number of BP lookups
|
|
system.cpu2.branchPred.condPredicted 45756 # Number of conditional branches predicted
|
|
system.cpu2.branchPred.condIncorrect 1281 # Number of conditional branches incorrect
|
|
system.cpu2.branchPred.BTBLookups 42366 # Number of BTB lookups
|
|
system.cpu2.branchPred.BTBHits 41626 # Number of BTB hits
|
|
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu2.branchPred.BTBHitPct 98.253316 # BTB Hit Percentage
|
|
system.cpu2.branchPred.usedRAS 643 # Number of times the RAS was used to get a target.
|
|
system.cpu2.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions.
|
|
system.cpu2.numCycles 174747 # number of cpu cycles simulated
|
|
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu2.fetch.icacheStallCycles 30691 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu2.fetch.Insts 266889 # Number of instructions fetch has processed
|
|
system.cpu2.fetch.Branches 48435 # Number of branches that fetch encountered
|
|
system.cpu2.fetch.predictedBranches 42269 # Number of branches that fetch has predicted taken
|
|
system.cpu2.fetch.Cycles 96584 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu2.fetch.SquashCycles 3759 # Number of cycles fetch has spent squashing
|
|
system.cpu2.fetch.BlockedCycles 36275 # Number of cycles fetch has spent blocked
|
|
system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu2.fetch.NoActiveThreadStallCycles 6390 # Number of stall cycles due to no active thread to fetch from
|
|
system.cpu2.fetch.PendingTrapStallCycles 712 # Number of stall cycles due to pending traps
|
|
system.cpu2.fetch.CacheLines 22267 # Number of cache lines fetched
|
|
system.cpu2.fetch.IcacheSquashes 266 # Number of outstanding Icache misses that were squashed
|
|
system.cpu2.fetch.rateDist::samples 173057 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::mean 1.542203 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::stdev 2.085998 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::0 76473 44.19% 44.19% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::1 49798 28.78% 72.96% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::2 7404 4.28% 77.24% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::3 3211 1.86% 79.10% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::4 674 0.39% 79.49% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::5 30262 17.49% 96.97% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::6 1242 0.72% 97.69% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::7 752 0.43% 98.13% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::8 3241 1.87% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.rateDist::total 173057 # Number of instructions fetched each cycle (Total)
|
|
system.cpu2.fetch.branchRate 0.277172 # Number of branch fetches per cycle
|
|
system.cpu2.fetch.rate 1.527288 # Number of inst fetches per cycle
|
|
system.cpu2.decode.IdleCycles 36897 # Number of cycles decode is idle
|
|
system.cpu2.decode.BlockedCycles 31644 # Number of cycles decode is blocked
|
|
system.cpu2.decode.RunCycles 89441 # Number of cycles decode is running
|
|
system.cpu2.decode.UnblockCycles 6284 # Number of cycles decode is unblocking
|
|
system.cpu2.decode.SquashCycles 2401 # Number of cycles decode is squashing
|
|
system.cpu2.decode.DecodedInsts 263319 # Number of instructions handled by decode
|
|
system.cpu2.rename.SquashCycles 2401 # Number of cycles rename is squashing
|
|
system.cpu2.rename.IdleCycles 37621 # Number of cycles rename is idle
|
|
system.cpu2.rename.BlockCycles 18625 # Number of cycles rename is blocking
|
|
system.cpu2.rename.serializeStallCycles 12236 # count of cycles rename stalled for serializing inst
|
|
system.cpu2.rename.RunCycles 83428 # Number of cycles rename is running
|
|
system.cpu2.rename.UnblockCycles 12356 # Number of cycles rename is unblocking
|
|
system.cpu2.rename.RenamedInsts 261093 # Number of instructions processed by rename
|
|
system.cpu2.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full
|
|
system.cpu2.rename.LSQFullEvents 35 # Number of times rename has blocked due to LSQ full
|
|
system.cpu2.rename.RenamedOperands 181374 # Number of destination operands rename has renamed
|
|
system.cpu2.rename.RenameLookups 493566 # Number of register rename lookups that rename has made
|
|
system.cpu2.rename.int_rename_lookups 493566 # Number of integer rename lookups
|
|
system.cpu2.rename.CommittedMaps 168473 # Number of HB maps that are committed
|
|
system.cpu2.rename.UndoneMaps 12901 # Number of HB maps that are undone due to squashing
|
|
system.cpu2.rename.serializingInsts 1100 # count of serializing insts renamed
|
|
system.cpu2.rename.tempSerializingInsts 1220 # count of temporary serializing insts renamed
|
|
system.cpu2.rename.skidInsts 15080 # count of insts added to the skid buffer
|
|
system.cpu2.memDep0.insertedLoads 72313 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu2.memDep0.insertedStores 33498 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu2.memDep0.conflictingLoads 35025 # Number of conflicting loads.
|
|
system.cpu2.memDep0.conflictingStores 28444 # Number of conflicting stores.
|
|
system.cpu2.iq.iqInstsAdded 214608 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu2.iq.iqNonSpecInstsAdded 7657 # Number of non-speculative instructions added to the IQ
|
|
system.cpu2.iq.iqInstsIssued 217768 # Number of instructions issued
|
|
system.cpu2.iq.iqSquashedInstsIssued 130 # Number of squashed instructions issued
|
|
system.cpu2.iq.iqSquashedInstsExamined 10976 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu2.iq.iqSquashedOperandsExamined 11107 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu2.iq.iqSquashedNonSpecRemoved 637 # Number of squashed non-spec instructions that were removed
|
|
system.cpu2.iq.issued_per_cycle::samples 173057 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::mean 1.258360 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::stdev 1.300957 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::0 74099 42.82% 42.82% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::1 26214 15.15% 57.97% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::2 33561 19.39% 77.36% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::3 34357 19.85% 97.21% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::4 3304 1.91% 99.12% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::5 1156 0.67% 99.79% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::6 256 0.15% 99.94% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::7 51 0.03% 99.97% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::8 59 0.03% 100.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu2.iq.issued_per_cycle::total 173057 # Number of insts issued each cycle
|
|
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IntAlu 17 5.65% 5.65% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IntMult 0 0.00% 5.65% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IntDiv 0 0.00% 5.65% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatAdd 0 0.00% 5.65% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatCmp 0 0.00% 5.65% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatCvt 0 0.00% 5.65% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatMult 0 0.00% 5.65% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatDiv 0 0.00% 5.65% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 5.65% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdAdd 0 0.00% 5.65% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 5.65% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdAlu 0 0.00% 5.65% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdCmp 0 0.00% 5.65% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdCvt 0 0.00% 5.65% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdMisc 0 0.00% 5.65% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdMult 0 0.00% 5.65% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 5.65% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdShift 0 0.00% 5.65% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 5.65% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 5.65% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 5.65% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 5.65% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 5.65% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 5.65% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 5.65% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 5.65% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 5.65% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 5.65% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 5.65% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::MemRead 74 24.58% 30.23% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::MemWrite 210 69.77% 100.00% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IntAlu 107188 49.22% 49.22% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.22% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.22% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.22% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.22% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.22% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.22% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.22% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.22% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.22% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.22% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.22% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.22% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.22% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.22% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.22% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.22% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.22% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.22% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.22% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.22% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.22% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.22% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.22% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.22% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.22% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.22% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.22% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.22% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::MemRead 77805 35.73% 84.95% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::MemWrite 32775 15.05% 100.00% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu2.iq.FU_type_0::total 217768 # Type of FU issued
|
|
system.cpu2.iq.rate 1.246190 # Inst issue rate
|
|
system.cpu2.iq.fu_busy_cnt 301 # FU busy when requested
|
|
system.cpu2.iq.fu_busy_rate 0.001382 # FU busy rate (busy events/executed inst)
|
|
system.cpu2.iq.int_inst_queue_reads 609024 # Number of integer instruction queue reads
|
|
system.cpu2.iq.int_inst_queue_writes 233287 # Number of integer instruction queue writes
|
|
system.cpu2.iq.int_inst_queue_wakeup_accesses 215963 # Number of integer instruction queue wakeup accesses
|
|
system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
|
|
system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
|
|
system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
|
|
system.cpu2.iq.int_alu_accesses 218069 # Number of integer alu accesses
|
|
system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses
|
|
system.cpu2.iew.lsq.thread0.forwLoads 28178 # Number of loads that had data forwarded from stores
|
|
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu2.iew.lsq.thread0.squashedLoads 2489 # Number of loads squashed
|
|
system.cpu2.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu2.iew.lsq.thread0.memOrderViolation 46 # Number of memory ordering violations
|
|
system.cpu2.iew.lsq.thread0.squashedStores 1471 # Number of stores squashed
|
|
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu2.iew.iewSquashCycles 2401 # Number of cycles IEW is squashing
|
|
system.cpu2.iew.iewBlockCycles 915 # Number of cycles IEW is blocking
|
|
system.cpu2.iew.iewUnblockCycles 65 # Number of cycles IEW is unblocking
|
|
system.cpu2.iew.iewDispatchedInsts 258202 # Number of instructions dispatched to IQ
|
|
system.cpu2.iew.iewDispSquashedInsts 343 # Number of squashed instructions skipped by dispatch
|
|
system.cpu2.iew.iewDispLoadInsts 72313 # Number of dispatched load instructions
|
|
system.cpu2.iew.iewDispStoreInsts 33498 # Number of dispatched store instructions
|
|
system.cpu2.iew.iewDispNonSpecInsts 1067 # Number of dispatched non-speculative instructions
|
|
system.cpu2.iew.iewIQFullEvents 66 # Number of times the IQ has become full, causing a stall
|
|
system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu2.iew.memOrderViolationEvents 46 # Number of memory order violations
|
|
system.cpu2.iew.predictedTakenIncorrect 465 # Number of branches that were predicted taken incorrectly
|
|
system.cpu2.iew.predictedNotTakenIncorrect 926 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu2.iew.branchMispredicts 1391 # Number of branch mispredicts detected at execute
|
|
system.cpu2.iew.iewExecutedInsts 216605 # Number of executed instructions
|
|
system.cpu2.iew.iewExecLoadInsts 71227 # Number of load instructions executed
|
|
system.cpu2.iew.iewExecSquashedInsts 1163 # Number of squashed instructions skipped in execute
|
|
system.cpu2.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu2.iew.exec_nop 35937 # number of nop insts executed
|
|
system.cpu2.iew.exec_refs 103922 # number of memory reference insts executed
|
|
system.cpu2.iew.exec_branches 45106 # Number of branches executed
|
|
system.cpu2.iew.exec_stores 32695 # Number of stores executed
|
|
system.cpu2.iew.exec_rate 1.239535 # Inst execution rate
|
|
system.cpu2.iew.wb_sent 216253 # cumulative count of insts sent to commit
|
|
system.cpu2.iew.wb_count 215963 # cumulative count of insts written-back
|
|
system.cpu2.iew.wb_producers 120625 # num instructions producing a value
|
|
system.cpu2.iew.wb_consumers 125288 # num instructions consuming a value
|
|
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu2.iew.wb_rate 1.235861 # insts written-back per cycle
|
|
system.cpu2.iew.wb_fanout 0.962782 # average fanout of values written-back
|
|
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu2.commit.commitSquashedInsts 12625 # The number of squashed insts skipped by commit
|
|
system.cpu2.commit.commitNonSpecStalls 7020 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu2.commit.branchMispredicts 1281 # The number of times a branch was mispredicted
|
|
system.cpu2.commit.committed_per_cycle::samples 164266 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::mean 1.494880 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::stdev 1.964665 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::0 74448 45.32% 45.32% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::1 43200 26.30% 71.62% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::2 6076 3.70% 75.32% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::3 7927 4.83% 80.15% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::4 1577 0.96% 81.11% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::5 28745 17.50% 98.60% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::6 476 0.29% 98.89% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::7 1000 0.61% 99.50% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::8 817 0.50% 100.00% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu2.commit.committed_per_cycle::total 164266 # Number of insts commited each cycle
|
|
system.cpu2.commit.committedInsts 245558 # Number of instructions committed
|
|
system.cpu2.commit.committedOps 245558 # Number of ops (including micro ops) committed
|
|
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu2.commit.refs 101851 # Number of memory references committed
|
|
system.cpu2.commit.loads 69824 # Number of loads committed
|
|
system.cpu2.commit.membars 6301 # Number of memory barriers committed
|
|
system.cpu2.commit.branches 44289 # Number of branches committed
|
|
system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions.
|
|
system.cpu2.commit.int_insts 168258 # Number of committed integer instructions.
|
|
system.cpu2.commit.function_calls 322 # Number of function calls committed.
|
|
system.cpu2.commit.bw_lim_events 817 # number cycles where commit BW limit reached
|
|
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu2.rob.rob_reads 421045 # The number of ROB reads
|
|
system.cpu2.rob.rob_writes 518771 # The number of ROB writes
|
|
system.cpu2.timesIdled 216 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu2.idleCycles 1690 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu2.quiesceCycles 37143 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu2.committedInsts 204183 # Number of Instructions Simulated
|
|
system.cpu2.committedOps 204183 # Number of Ops (including micro ops) Simulated
|
|
system.cpu2.committedInsts_total 204183 # Number of Instructions Simulated
|
|
system.cpu2.cpi 0.855835 # CPI: Cycles Per Instruction
|
|
system.cpu2.cpi_total 0.855835 # CPI: Total CPI of All Threads
|
|
system.cpu2.ipc 1.168449 # IPC: Instructions Per Cycle
|
|
system.cpu2.ipc_total 1.168449 # IPC: Total IPC of All Threads
|
|
system.cpu2.int_regfile_reads 370277 # number of integer regfile reads
|
|
system.cpu2.int_regfile_writes 173276 # number of integer regfile writes
|
|
system.cpu2.fp_regfile_writes 64 # number of floating regfile writes
|
|
system.cpu2.misc_regfile_reads 105484 # number of misc regfile reads
|
|
system.cpu2.misc_regfile_writes 648 # number of misc regfile writes
|
|
system.cpu2.icache.replacements 319 # number of replacements
|
|
system.cpu2.icache.tagsinuse 83.493778 # Cycle average of tags in use
|
|
system.cpu2.icache.total_refs 21789 # Total number of references to valid blocks.
|
|
system.cpu2.icache.sampled_refs 430 # Sample count of references to valid blocks.
|
|
system.cpu2.icache.avg_refs 50.672093 # Average number of references to valid blocks.
|
|
system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu2.icache.occ_blocks::cpu2.inst 83.493778 # Average occupied blocks per requestor
|
|
system.cpu2.icache.occ_percent::cpu2.inst 0.163074 # Average percentage of cache occupancy
|
|
system.cpu2.icache.occ_percent::total 0.163074 # Average percentage of cache occupancy
|
|
system.cpu2.icache.ReadReq_hits::cpu2.inst 21789 # number of ReadReq hits
|
|
system.cpu2.icache.ReadReq_hits::total 21789 # number of ReadReq hits
|
|
system.cpu2.icache.demand_hits::cpu2.inst 21789 # number of demand (read+write) hits
|
|
system.cpu2.icache.demand_hits::total 21789 # number of demand (read+write) hits
|
|
system.cpu2.icache.overall_hits::cpu2.inst 21789 # number of overall hits
|
|
system.cpu2.icache.overall_hits::total 21789 # number of overall hits
|
|
system.cpu2.icache.ReadReq_misses::cpu2.inst 478 # number of ReadReq misses
|
|
system.cpu2.icache.ReadReq_misses::total 478 # number of ReadReq misses
|
|
system.cpu2.icache.demand_misses::cpu2.inst 478 # number of demand (read+write) misses
|
|
system.cpu2.icache.demand_misses::total 478 # number of demand (read+write) misses
|
|
system.cpu2.icache.overall_misses::cpu2.inst 478 # number of overall misses
|
|
system.cpu2.icache.overall_misses::total 478 # number of overall misses
|
|
system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 6833500 # number of ReadReq miss cycles
|
|
system.cpu2.icache.ReadReq_miss_latency::total 6833500 # number of ReadReq miss cycles
|
|
system.cpu2.icache.demand_miss_latency::cpu2.inst 6833500 # number of demand (read+write) miss cycles
|
|
system.cpu2.icache.demand_miss_latency::total 6833500 # number of demand (read+write) miss cycles
|
|
system.cpu2.icache.overall_miss_latency::cpu2.inst 6833500 # number of overall miss cycles
|
|
system.cpu2.icache.overall_miss_latency::total 6833500 # number of overall miss cycles
|
|
system.cpu2.icache.ReadReq_accesses::cpu2.inst 22267 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.icache.ReadReq_accesses::total 22267 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.icache.demand_accesses::cpu2.inst 22267 # number of demand (read+write) accesses
|
|
system.cpu2.icache.demand_accesses::total 22267 # number of demand (read+write) accesses
|
|
system.cpu2.icache.overall_accesses::cpu2.inst 22267 # number of overall (read+write) accesses
|
|
system.cpu2.icache.overall_accesses::total 22267 # number of overall (read+write) accesses
|
|
system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.021467 # miss rate for ReadReq accesses
|
|
system.cpu2.icache.ReadReq_miss_rate::total 0.021467 # miss rate for ReadReq accesses
|
|
system.cpu2.icache.demand_miss_rate::cpu2.inst 0.021467 # miss rate for demand accesses
|
|
system.cpu2.icache.demand_miss_rate::total 0.021467 # miss rate for demand accesses
|
|
system.cpu2.icache.overall_miss_rate::cpu2.inst 0.021467 # miss rate for overall accesses
|
|
system.cpu2.icache.overall_miss_rate::total 0.021467 # miss rate for overall accesses
|
|
system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14296.025105 # average ReadReq miss latency
|
|
system.cpu2.icache.ReadReq_avg_miss_latency::total 14296.025105 # average ReadReq miss latency
|
|
system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14296.025105 # average overall miss latency
|
|
system.cpu2.icache.demand_avg_miss_latency::total 14296.025105 # average overall miss latency
|
|
system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14296.025105 # average overall miss latency
|
|
system.cpu2.icache.overall_avg_miss_latency::total 14296.025105 # average overall miss latency
|
|
system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu2.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu2.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu2.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 48 # number of ReadReq MSHR hits
|
|
system.cpu2.icache.ReadReq_mshr_hits::total 48 # number of ReadReq MSHR hits
|
|
system.cpu2.icache.demand_mshr_hits::cpu2.inst 48 # number of demand (read+write) MSHR hits
|
|
system.cpu2.icache.demand_mshr_hits::total 48 # number of demand (read+write) MSHR hits
|
|
system.cpu2.icache.overall_mshr_hits::cpu2.inst 48 # number of overall MSHR hits
|
|
system.cpu2.icache.overall_mshr_hits::total 48 # number of overall MSHR hits
|
|
system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 430 # number of ReadReq MSHR misses
|
|
system.cpu2.icache.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses
|
|
system.cpu2.icache.demand_mshr_misses::cpu2.inst 430 # number of demand (read+write) MSHR misses
|
|
system.cpu2.icache.demand_mshr_misses::total 430 # number of demand (read+write) MSHR misses
|
|
system.cpu2.icache.overall_mshr_misses::cpu2.inst 430 # number of overall MSHR misses
|
|
system.cpu2.icache.overall_mshr_misses::total 430 # number of overall MSHR misses
|
|
system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 5518500 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.icache.ReadReq_mshr_miss_latency::total 5518500 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 5518500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.icache.demand_mshr_miss_latency::total 5518500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 5518500 # number of overall MSHR miss cycles
|
|
system.cpu2.icache.overall_mshr_miss_latency::total 5518500 # number of overall MSHR miss cycles
|
|
system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.019311 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.019311 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.019311 # mshr miss rate for demand accesses
|
|
system.cpu2.icache.demand_mshr_miss_rate::total 0.019311 # mshr miss rate for demand accesses
|
|
system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.019311 # mshr miss rate for overall accesses
|
|
system.cpu2.icache.overall_mshr_miss_rate::total 0.019311 # mshr miss rate for overall accesses
|
|
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 12833.720930 # average ReadReq mshr miss latency
|
|
system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 12833.720930 # average ReadReq mshr miss latency
|
|
system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 12833.720930 # average overall mshr miss latency
|
|
system.cpu2.icache.demand_avg_mshr_miss_latency::total 12833.720930 # average overall mshr miss latency
|
|
system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 12833.720930 # average overall mshr miss latency
|
|
system.cpu2.icache.overall_avg_mshr_miss_latency::total 12833.720930 # average overall mshr miss latency
|
|
system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu2.dcache.replacements 0 # number of replacements
|
|
system.cpu2.dcache.tagsinuse 25.660288 # Cycle average of tags in use
|
|
system.cpu2.dcache.total_refs 38032 # Total number of references to valid blocks.
|
|
system.cpu2.dcache.sampled_refs 28 # Sample count of references to valid blocks.
|
|
system.cpu2.dcache.avg_refs 1358.285714 # Average number of references to valid blocks.
|
|
system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu2.dcache.occ_blocks::cpu2.data 25.660288 # Average occupied blocks per requestor
|
|
system.cpu2.dcache.occ_percent::cpu2.data 0.050118 # Average percentage of cache occupancy
|
|
system.cpu2.dcache.occ_percent::total 0.050118 # Average percentage of cache occupancy
|
|
system.cpu2.dcache.ReadReq_hits::cpu2.data 42624 # number of ReadReq hits
|
|
system.cpu2.dcache.ReadReq_hits::total 42624 # number of ReadReq hits
|
|
system.cpu2.dcache.WriteReq_hits::cpu2.data 31820 # number of WriteReq hits
|
|
system.cpu2.dcache.WriteReq_hits::total 31820 # number of WriteReq hits
|
|
system.cpu2.dcache.SwapReq_hits::cpu2.data 15 # number of SwapReq hits
|
|
system.cpu2.dcache.SwapReq_hits::total 15 # number of SwapReq hits
|
|
system.cpu2.dcache.demand_hits::cpu2.data 74444 # number of demand (read+write) hits
|
|
system.cpu2.dcache.demand_hits::total 74444 # number of demand (read+write) hits
|
|
system.cpu2.dcache.overall_hits::cpu2.data 74444 # number of overall hits
|
|
system.cpu2.dcache.overall_hits::total 74444 # number of overall hits
|
|
system.cpu2.dcache.ReadReq_misses::cpu2.data 407 # number of ReadReq misses
|
|
system.cpu2.dcache.ReadReq_misses::total 407 # number of ReadReq misses
|
|
system.cpu2.dcache.WriteReq_misses::cpu2.data 134 # number of WriteReq misses
|
|
system.cpu2.dcache.WriteReq_misses::total 134 # number of WriteReq misses
|
|
system.cpu2.dcache.SwapReq_misses::cpu2.data 58 # number of SwapReq misses
|
|
system.cpu2.dcache.SwapReq_misses::total 58 # number of SwapReq misses
|
|
system.cpu2.dcache.demand_misses::cpu2.data 541 # number of demand (read+write) misses
|
|
system.cpu2.dcache.demand_misses::total 541 # number of demand (read+write) misses
|
|
system.cpu2.dcache.overall_misses::cpu2.data 541 # number of overall misses
|
|
system.cpu2.dcache.overall_misses::total 541 # number of overall misses
|
|
system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 5612500 # number of ReadReq miss cycles
|
|
system.cpu2.dcache.ReadReq_miss_latency::total 5612500 # number of ReadReq miss cycles
|
|
system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 2750000 # number of WriteReq miss cycles
|
|
system.cpu2.dcache.WriteReq_miss_latency::total 2750000 # number of WriteReq miss cycles
|
|
system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 572000 # number of SwapReq miss cycles
|
|
system.cpu2.dcache.SwapReq_miss_latency::total 572000 # number of SwapReq miss cycles
|
|
system.cpu2.dcache.demand_miss_latency::cpu2.data 8362500 # number of demand (read+write) miss cycles
|
|
system.cpu2.dcache.demand_miss_latency::total 8362500 # number of demand (read+write) miss cycles
|
|
system.cpu2.dcache.overall_miss_latency::cpu2.data 8362500 # number of overall miss cycles
|
|
system.cpu2.dcache.overall_miss_latency::total 8362500 # number of overall miss cycles
|
|
system.cpu2.dcache.ReadReq_accesses::cpu2.data 43031 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.dcache.ReadReq_accesses::total 43031 # number of ReadReq accesses(hits+misses)
|
|
system.cpu2.dcache.WriteReq_accesses::cpu2.data 31954 # number of WriteReq accesses(hits+misses)
|
|
system.cpu2.dcache.WriteReq_accesses::total 31954 # number of WriteReq accesses(hits+misses)
|
|
system.cpu2.dcache.SwapReq_accesses::cpu2.data 73 # number of SwapReq accesses(hits+misses)
|
|
system.cpu2.dcache.SwapReq_accesses::total 73 # number of SwapReq accesses(hits+misses)
|
|
system.cpu2.dcache.demand_accesses::cpu2.data 74985 # number of demand (read+write) accesses
|
|
system.cpu2.dcache.demand_accesses::total 74985 # number of demand (read+write) accesses
|
|
system.cpu2.dcache.overall_accesses::cpu2.data 74985 # number of overall (read+write) accesses
|
|
system.cpu2.dcache.overall_accesses::total 74985 # number of overall (read+write) accesses
|
|
system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.009458 # miss rate for ReadReq accesses
|
|
system.cpu2.dcache.ReadReq_miss_rate::total 0.009458 # miss rate for ReadReq accesses
|
|
system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004194 # miss rate for WriteReq accesses
|
|
system.cpu2.dcache.WriteReq_miss_rate::total 0.004194 # miss rate for WriteReq accesses
|
|
system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.794521 # miss rate for SwapReq accesses
|
|
system.cpu2.dcache.SwapReq_miss_rate::total 0.794521 # miss rate for SwapReq accesses
|
|
system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007215 # miss rate for demand accesses
|
|
system.cpu2.dcache.demand_miss_rate::total 0.007215 # miss rate for demand accesses
|
|
system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007215 # miss rate for overall accesses
|
|
system.cpu2.dcache.overall_miss_rate::total 0.007215 # miss rate for overall accesses
|
|
system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 13789.926290 # average ReadReq miss latency
|
|
system.cpu2.dcache.ReadReq_avg_miss_latency::total 13789.926290 # average ReadReq miss latency
|
|
system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 20522.388060 # average WriteReq miss latency
|
|
system.cpu2.dcache.WriteReq_avg_miss_latency::total 20522.388060 # average WriteReq miss latency
|
|
system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 9862.068966 # average SwapReq miss latency
|
|
system.cpu2.dcache.SwapReq_avg_miss_latency::total 9862.068966 # average SwapReq miss latency
|
|
system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 15457.486137 # average overall miss latency
|
|
system.cpu2.dcache.demand_avg_miss_latency::total 15457.486137 # average overall miss latency
|
|
system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 15457.486137 # average overall miss latency
|
|
system.cpu2.dcache.overall_avg_miss_latency::total 15457.486137 # average overall miss latency
|
|
system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu2.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu2.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu2.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 246 # number of ReadReq MSHR hits
|
|
system.cpu2.dcache.ReadReq_mshr_hits::total 246 # number of ReadReq MSHR hits
|
|
system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 33 # number of WriteReq MSHR hits
|
|
system.cpu2.dcache.WriteReq_mshr_hits::total 33 # number of WriteReq MSHR hits
|
|
system.cpu2.dcache.demand_mshr_hits::cpu2.data 279 # number of demand (read+write) MSHR hits
|
|
system.cpu2.dcache.demand_mshr_hits::total 279 # number of demand (read+write) MSHR hits
|
|
system.cpu2.dcache.overall_mshr_hits::cpu2.data 279 # number of overall MSHR hits
|
|
system.cpu2.dcache.overall_mshr_hits::total 279 # number of overall MSHR hits
|
|
system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 161 # number of ReadReq MSHR misses
|
|
system.cpu2.dcache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses
|
|
system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 101 # number of WriteReq MSHR misses
|
|
system.cpu2.dcache.WriteReq_mshr_misses::total 101 # number of WriteReq MSHR misses
|
|
system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 58 # number of SwapReq MSHR misses
|
|
system.cpu2.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses
|
|
system.cpu2.dcache.demand_mshr_misses::cpu2.data 262 # number of demand (read+write) MSHR misses
|
|
system.cpu2.dcache.demand_mshr_misses::total 262 # number of demand (read+write) MSHR misses
|
|
system.cpu2.dcache.overall_mshr_misses::cpu2.data 262 # number of overall MSHR misses
|
|
system.cpu2.dcache.overall_mshr_misses::total 262 # number of overall MSHR misses
|
|
system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1373500 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1373500 # number of ReadReq MSHR miss cycles
|
|
system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1349000 # number of WriteReq MSHR miss cycles
|
|
system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1349000 # number of WriteReq MSHR miss cycles
|
|
system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 456000 # number of SwapReq MSHR miss cycles
|
|
system.cpu2.dcache.SwapReq_mshr_miss_latency::total 456000 # number of SwapReq MSHR miss cycles
|
|
system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2722500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.dcache.demand_mshr_miss_latency::total 2722500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2722500 # number of overall MSHR miss cycles
|
|
system.cpu2.dcache.overall_mshr_miss_latency::total 2722500 # number of overall MSHR miss cycles
|
|
system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003741 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003741 # mshr miss rate for ReadReq accesses
|
|
system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003161 # mshr miss rate for WriteReq accesses
|
|
system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003161 # mshr miss rate for WriteReq accesses
|
|
system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.794521 # mshr miss rate for SwapReq accesses
|
|
system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.794521 # mshr miss rate for SwapReq accesses
|
|
system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003494 # mshr miss rate for demand accesses
|
|
system.cpu2.dcache.demand_mshr_miss_rate::total 0.003494 # mshr miss rate for demand accesses
|
|
system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003494 # mshr miss rate for overall accesses
|
|
system.cpu2.dcache.overall_mshr_miss_rate::total 0.003494 # mshr miss rate for overall accesses
|
|
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 8531.055901 # average ReadReq mshr miss latency
|
|
system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 8531.055901 # average ReadReq mshr miss latency
|
|
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 13356.435644 # average WriteReq mshr miss latency
|
|
system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 13356.435644 # average WriteReq mshr miss latency
|
|
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 7862.068966 # average SwapReq mshr miss latency
|
|
system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 7862.068966 # average SwapReq mshr miss latency
|
|
system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 10391.221374 # average overall mshr miss latency
|
|
system.cpu2.dcache.demand_avg_mshr_miss_latency::total 10391.221374 # average overall mshr miss latency
|
|
system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 10391.221374 # average overall mshr miss latency
|
|
system.cpu2.dcache.overall_avg_mshr_miss_latency::total 10391.221374 # average overall mshr miss latency
|
|
system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu3.branchPred.lookups 45379 # Number of BP lookups
|
|
system.cpu3.branchPred.condPredicted 42609 # Number of conditional branches predicted
|
|
system.cpu3.branchPred.condIncorrect 1294 # Number of conditional branches incorrect
|
|
system.cpu3.branchPred.BTBLookups 39317 # Number of BTB lookups
|
|
system.cpu3.branchPred.BTBHits 38445 # Number of BTB hits
|
|
system.cpu3.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
|
|
system.cpu3.branchPred.BTBHitPct 97.782130 # BTB Hit Percentage
|
|
system.cpu3.branchPred.usedRAS 651 # Number of times the RAS was used to get a target.
|
|
system.cpu3.branchPred.RASInCorrect 232 # Number of incorrect RAS predictions.
|
|
system.cpu3.numCycles 174437 # number of cpu cycles simulated
|
|
system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started
|
|
system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed
|
|
system.cpu3.fetch.icacheStallCycles 32466 # Number of cycles fetch is stalled on an Icache miss
|
|
system.cpu3.fetch.Insts 246453 # Number of instructions fetch has processed
|
|
system.cpu3.fetch.Branches 45379 # Number of branches that fetch encountered
|
|
system.cpu3.fetch.predictedBranches 39096 # Number of branches that fetch has predicted taken
|
|
system.cpu3.fetch.Cycles 91198 # Number of cycles fetch has run and was not squashing or blocked
|
|
system.cpu3.fetch.SquashCycles 3791 # Number of cycles fetch has spent squashing
|
|
system.cpu3.fetch.BlockedCycles 39692 # Number of cycles fetch has spent blocked
|
|
system.cpu3.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
|
|
system.cpu3.fetch.NoActiveThreadStallCycles 6399 # Number of stall cycles due to no active thread to fetch from
|
|
system.cpu3.fetch.PendingTrapStallCycles 699 # Number of stall cycles due to pending traps
|
|
system.cpu3.fetch.CacheLines 24152 # Number of cache lines fetched
|
|
system.cpu3.fetch.IcacheSquashes 266 # Number of outstanding Icache misses that were squashed
|
|
system.cpu3.fetch.rateDist::samples 172879 # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::mean 1.425581 # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::stdev 2.034525 # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::0 81681 47.25% 47.25% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::1 47531 27.49% 74.74% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::2 8280 4.79% 79.53% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::3 3183 1.84% 81.37% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::4 751 0.43% 81.81% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::5 26265 15.19% 97.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::6 1130 0.65% 97.65% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::7 760 0.44% 98.09% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::8 3298 1.91% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.rateDist::total 172879 # Number of instructions fetched each cycle (Total)
|
|
system.cpu3.fetch.branchRate 0.260145 # Number of branch fetches per cycle
|
|
system.cpu3.fetch.rate 1.412848 # Number of inst fetches per cycle
|
|
system.cpu3.decode.IdleCycles 39667 # Number of cycles decode is idle
|
|
system.cpu3.decode.BlockedCycles 34044 # Number of cycles decode is blocked
|
|
system.cpu3.decode.RunCycles 83244 # Number of cycles decode is running
|
|
system.cpu3.decode.UnblockCycles 7105 # Number of cycles decode is unblocking
|
|
system.cpu3.decode.SquashCycles 2420 # Number of cycles decode is squashing
|
|
system.cpu3.decode.DecodedInsts 242894 # Number of instructions handled by decode
|
|
system.cpu3.rename.SquashCycles 2420 # Number of cycles rename is squashing
|
|
system.cpu3.rename.IdleCycles 40390 # Number of cycles rename is idle
|
|
system.cpu3.rename.BlockCycles 21128 # Number of cycles rename is blocking
|
|
system.cpu3.rename.serializeStallCycles 12127 # count of cycles rename stalled for serializing inst
|
|
system.cpu3.rename.RunCycles 76402 # Number of cycles rename is running
|
|
system.cpu3.rename.UnblockCycles 14013 # Number of cycles rename is unblocking
|
|
system.cpu3.rename.RenamedInsts 240516 # Number of instructions processed by rename
|
|
system.cpu3.rename.IQFullEvents 1 # Number of times rename has blocked due to IQ full
|
|
system.cpu3.rename.LSQFullEvents 44 # Number of times rename has blocked due to LSQ full
|
|
system.cpu3.rename.RenamedOperands 166179 # Number of destination operands rename has renamed
|
|
system.cpu3.rename.RenameLookups 449032 # Number of register rename lookups that rename has made
|
|
system.cpu3.rename.int_rename_lookups 449032 # Number of integer rename lookups
|
|
system.cpu3.rename.CommittedMaps 153365 # Number of HB maps that are committed
|
|
system.cpu3.rename.UndoneMaps 12814 # Number of HB maps that are undone due to squashing
|
|
system.cpu3.rename.serializingInsts 1105 # count of serializing insts renamed
|
|
system.cpu3.rename.tempSerializingInsts 1221 # count of temporary serializing insts renamed
|
|
system.cpu3.rename.skidInsts 16705 # count of insts added to the skid buffer
|
|
system.cpu3.memDep0.insertedLoads 65194 # Number of loads inserted to the mem dependence unit.
|
|
system.cpu3.memDep0.insertedStores 29511 # Number of stores inserted to the mem dependence unit.
|
|
system.cpu3.memDep0.conflictingLoads 31885 # Number of conflicting loads.
|
|
system.cpu3.memDep0.conflictingStores 24466 # Number of conflicting stores.
|
|
system.cpu3.iq.iqInstsAdded 196370 # Number of instructions added to the IQ (excludes non-spec)
|
|
system.cpu3.iq.iqNonSpecInstsAdded 8514 # Number of non-speculative instructions added to the IQ
|
|
system.cpu3.iq.iqInstsIssued 200412 # Number of instructions issued
|
|
system.cpu3.iq.iqSquashedInstsIssued 127 # Number of squashed instructions issued
|
|
system.cpu3.iq.iqSquashedInstsExamined 10978 # Number of squashed instructions iterated over during squash; mainly for profiling
|
|
system.cpu3.iq.iqSquashedOperandsExamined 11006 # Number of squashed operands that are examined and possibly removed from graph
|
|
system.cpu3.iq.iqSquashedNonSpecRemoved 643 # Number of squashed non-spec instructions that were removed
|
|
system.cpu3.iq.issued_per_cycle::samples 172879 # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::mean 1.159262 # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::stdev 1.284832 # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::0 79312 45.88% 45.88% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::1 28822 16.67% 62.55% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::2 29551 17.09% 79.64% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::3 30339 17.55% 97.19% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::4 3334 1.93% 99.12% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::5 1154 0.67% 99.79% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::6 261 0.15% 99.94% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::7 49 0.03% 99.97% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::8 57 0.03% 100.00% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
|
|
system.cpu3.iq.issued_per_cycle::total 172879 # Number of insts issued each cycle
|
|
system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::IntAlu 12 4.07% 4.07% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::IntMult 0 0.00% 4.07% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::IntDiv 0 0.00% 4.07% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::FloatAdd 0 0.00% 4.07% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::FloatCmp 0 0.00% 4.07% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::FloatCvt 0 0.00% 4.07% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::FloatMult 0 0.00% 4.07% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::FloatDiv 0 0.00% 4.07% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 4.07% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdAdd 0 0.00% 4.07% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 4.07% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdAlu 0 0.00% 4.07% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdCmp 0 0.00% 4.07% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdCvt 0 0.00% 4.07% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdMisc 0 0.00% 4.07% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdMult 0 0.00% 4.07% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 4.07% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdShift 0 0.00% 4.07% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 4.07% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 4.07% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 4.07% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 4.07% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 4.07% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 4.07% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 4.07% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 4.07% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 4.07% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.07% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 4.07% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::MemRead 73 24.75% 28.81% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::MemWrite 210 71.19% 100.00% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
|
|
system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::IntAlu 100076 49.94% 49.94% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::IntMult 0 0.00% 49.94% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 49.94% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 49.94% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 49.94% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 49.94% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 49.94% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 49.94% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 49.94% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 49.94% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 49.94% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 49.94% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 49.94% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 49.94% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 49.94% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 49.94% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 49.94% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 49.94% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.94% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 49.94% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.94% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.94% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.94% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.94% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.94% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.94% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 49.94% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.94% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.94% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::MemRead 71520 35.69% 85.62% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::MemWrite 28816 14.38% 100.00% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
|
|
system.cpu3.iq.FU_type_0::total 200412 # Type of FU issued
|
|
system.cpu3.iq.rate 1.148908 # Inst issue rate
|
|
system.cpu3.iq.fu_busy_cnt 295 # FU busy when requested
|
|
system.cpu3.iq.fu_busy_rate 0.001472 # FU busy rate (busy events/executed inst)
|
|
system.cpu3.iq.int_inst_queue_reads 574125 # Number of integer instruction queue reads
|
|
system.cpu3.iq.int_inst_queue_writes 215907 # Number of integer instruction queue writes
|
|
system.cpu3.iq.int_inst_queue_wakeup_accesses 198595 # Number of integer instruction queue wakeup accesses
|
|
system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads
|
|
system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes
|
|
system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses
|
|
system.cpu3.iq.int_alu_accesses 200707 # Number of integer alu accesses
|
|
system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses
|
|
system.cpu3.iew.lsq.thread0.forwLoads 24188 # Number of loads that had data forwarded from stores
|
|
system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
|
|
system.cpu3.iew.lsq.thread0.squashedLoads 2497 # Number of loads squashed
|
|
system.cpu3.iew.lsq.thread0.ignoredResponses 3 # Number of memory responses ignored because the instruction is squashed
|
|
system.cpu3.iew.lsq.thread0.memOrderViolation 45 # Number of memory ordering violations
|
|
system.cpu3.iew.lsq.thread0.squashedStores 1474 # Number of stores squashed
|
|
system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
|
|
system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
|
|
system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
|
|
system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
|
|
system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle
|
|
system.cpu3.iew.iewSquashCycles 2420 # Number of cycles IEW is squashing
|
|
system.cpu3.iew.iewBlockCycles 942 # Number of cycles IEW is blocking
|
|
system.cpu3.iew.iewUnblockCycles 58 # Number of cycles IEW is unblocking
|
|
system.cpu3.iew.iewDispatchedInsts 237691 # Number of instructions dispatched to IQ
|
|
system.cpu3.iew.iewDispSquashedInsts 354 # Number of squashed instructions skipped by dispatch
|
|
system.cpu3.iew.iewDispLoadInsts 65194 # Number of dispatched load instructions
|
|
system.cpu3.iew.iewDispStoreInsts 29511 # Number of dispatched store instructions
|
|
system.cpu3.iew.iewDispNonSpecInsts 1069 # Number of dispatched non-speculative instructions
|
|
system.cpu3.iew.iewIQFullEvents 58 # Number of times the IQ has become full, causing a stall
|
|
system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
|
|
system.cpu3.iew.memOrderViolationEvents 45 # Number of memory order violations
|
|
system.cpu3.iew.predictedTakenIncorrect 475 # Number of branches that were predicted taken incorrectly
|
|
system.cpu3.iew.predictedNotTakenIncorrect 932 # Number of branches that were predicted not taken incorrectly
|
|
system.cpu3.iew.branchMispredicts 1407 # Number of branch mispredicts detected at execute
|
|
system.cpu3.iew.iewExecutedInsts 199248 # Number of executed instructions
|
|
system.cpu3.iew.iewExecLoadInsts 64095 # Number of load instructions executed
|
|
system.cpu3.iew.iewExecSquashedInsts 1164 # Number of squashed instructions skipped in execute
|
|
system.cpu3.iew.exec_swp 0 # number of swp insts executed
|
|
system.cpu3.iew.exec_nop 32807 # number of nop insts executed
|
|
system.cpu3.iew.exec_refs 92831 # number of memory reference insts executed
|
|
system.cpu3.iew.exec_branches 41971 # Number of branches executed
|
|
system.cpu3.iew.exec_stores 28736 # Number of stores executed
|
|
system.cpu3.iew.exec_rate 1.142235 # Inst execution rate
|
|
system.cpu3.iew.wb_sent 198881 # cumulative count of insts sent to commit
|
|
system.cpu3.iew.wb_count 198595 # cumulative count of insts written-back
|
|
system.cpu3.iew.wb_producers 109565 # num instructions producing a value
|
|
system.cpu3.iew.wb_consumers 114222 # num instructions consuming a value
|
|
system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
|
|
system.cpu3.iew.wb_rate 1.138491 # insts written-back per cycle
|
|
system.cpu3.iew.wb_fanout 0.959229 # average fanout of values written-back
|
|
system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
|
|
system.cpu3.commit.commitSquashedInsts 12643 # The number of squashed insts skipped by commit
|
|
system.cpu3.commit.commitNonSpecStalls 7871 # The number of times commit has been forced to stall to communicate backwards
|
|
system.cpu3.commit.branchMispredicts 1294 # The number of times a branch was mispredicted
|
|
system.cpu3.commit.committed_per_cycle::samples 164060 # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::mean 1.371620 # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::stdev 1.908371 # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::0 80528 49.08% 49.08% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::1 40048 24.41% 73.50% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::2 6110 3.72% 77.22% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::3 8758 5.34% 82.56% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::4 1552 0.95% 83.50% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::5 24728 15.07% 98.58% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::6 520 0.32% 98.89% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::7 1010 0.62% 99.51% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::8 806 0.49% 100.00% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
|
|
system.cpu3.commit.committed_per_cycle::total 164060 # Number of insts commited each cycle
|
|
system.cpu3.commit.committedInsts 225028 # Number of instructions committed
|
|
system.cpu3.commit.committedOps 225028 # Number of ops (including micro ops) committed
|
|
system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed
|
|
system.cpu3.commit.refs 90734 # Number of memory references committed
|
|
system.cpu3.commit.loads 62697 # Number of loads committed
|
|
system.cpu3.commit.membars 7153 # Number of memory barriers committed
|
|
system.cpu3.commit.branches 41151 # Number of branches committed
|
|
system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions.
|
|
system.cpu3.commit.int_insts 154003 # Number of committed integer instructions.
|
|
system.cpu3.commit.function_calls 322 # Number of function calls committed.
|
|
system.cpu3.commit.bw_lim_events 806 # number cycles where commit BW limit reached
|
|
system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits
|
|
system.cpu3.rob.rob_reads 400338 # The number of ROB reads
|
|
system.cpu3.rob.rob_writes 477767 # The number of ROB writes
|
|
system.cpu3.timesIdled 220 # Number of times that the entire CPU went into an idle state and unscheduled itself
|
|
system.cpu3.idleCycles 1558 # Total number of cycles that the CPU has spent unscheduled due to idling
|
|
system.cpu3.quiesceCycles 37453 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
|
|
system.cpu3.committedInsts 185938 # Number of Instructions Simulated
|
|
system.cpu3.committedOps 185938 # Number of Ops (including micro ops) Simulated
|
|
system.cpu3.committedInsts_total 185938 # Number of Instructions Simulated
|
|
system.cpu3.cpi 0.938146 # CPI: Cycles Per Instruction
|
|
system.cpu3.cpi_total 0.938146 # CPI: Total CPI of All Threads
|
|
system.cpu3.ipc 1.065932 # IPC: Instructions Per Cycle
|
|
system.cpu3.ipc_total 1.065932 # IPC: Total IPC of All Threads
|
|
system.cpu3.int_regfile_reads 337021 # number of integer regfile reads
|
|
system.cpu3.int_regfile_writes 158120 # number of integer regfile writes
|
|
system.cpu3.fp_regfile_writes 64 # number of floating regfile writes
|
|
system.cpu3.misc_regfile_reads 94371 # number of misc regfile reads
|
|
system.cpu3.misc_regfile_writes 648 # number of misc regfile writes
|
|
system.cpu3.icache.replacements 318 # number of replacements
|
|
system.cpu3.icache.tagsinuse 80.241223 # Cycle average of tags in use
|
|
system.cpu3.icache.total_refs 23677 # Total number of references to valid blocks.
|
|
system.cpu3.icache.sampled_refs 429 # Sample count of references to valid blocks.
|
|
system.cpu3.icache.avg_refs 55.191142 # Average number of references to valid blocks.
|
|
system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu3.icache.occ_blocks::cpu3.inst 80.241223 # Average occupied blocks per requestor
|
|
system.cpu3.icache.occ_percent::cpu3.inst 0.156721 # Average percentage of cache occupancy
|
|
system.cpu3.icache.occ_percent::total 0.156721 # Average percentage of cache occupancy
|
|
system.cpu3.icache.ReadReq_hits::cpu3.inst 23677 # number of ReadReq hits
|
|
system.cpu3.icache.ReadReq_hits::total 23677 # number of ReadReq hits
|
|
system.cpu3.icache.demand_hits::cpu3.inst 23677 # number of demand (read+write) hits
|
|
system.cpu3.icache.demand_hits::total 23677 # number of demand (read+write) hits
|
|
system.cpu3.icache.overall_hits::cpu3.inst 23677 # number of overall hits
|
|
system.cpu3.icache.overall_hits::total 23677 # number of overall hits
|
|
system.cpu3.icache.ReadReq_misses::cpu3.inst 475 # number of ReadReq misses
|
|
system.cpu3.icache.ReadReq_misses::total 475 # number of ReadReq misses
|
|
system.cpu3.icache.demand_misses::cpu3.inst 475 # number of demand (read+write) misses
|
|
system.cpu3.icache.demand_misses::total 475 # number of demand (read+write) misses
|
|
system.cpu3.icache.overall_misses::cpu3.inst 475 # number of overall misses
|
|
system.cpu3.icache.overall_misses::total 475 # number of overall misses
|
|
system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 6195500 # number of ReadReq miss cycles
|
|
system.cpu3.icache.ReadReq_miss_latency::total 6195500 # number of ReadReq miss cycles
|
|
system.cpu3.icache.demand_miss_latency::cpu3.inst 6195500 # number of demand (read+write) miss cycles
|
|
system.cpu3.icache.demand_miss_latency::total 6195500 # number of demand (read+write) miss cycles
|
|
system.cpu3.icache.overall_miss_latency::cpu3.inst 6195500 # number of overall miss cycles
|
|
system.cpu3.icache.overall_miss_latency::total 6195500 # number of overall miss cycles
|
|
system.cpu3.icache.ReadReq_accesses::cpu3.inst 24152 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.icache.ReadReq_accesses::total 24152 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.icache.demand_accesses::cpu3.inst 24152 # number of demand (read+write) accesses
|
|
system.cpu3.icache.demand_accesses::total 24152 # number of demand (read+write) accesses
|
|
system.cpu3.icache.overall_accesses::cpu3.inst 24152 # number of overall (read+write) accesses
|
|
system.cpu3.icache.overall_accesses::total 24152 # number of overall (read+write) accesses
|
|
system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.019667 # miss rate for ReadReq accesses
|
|
system.cpu3.icache.ReadReq_miss_rate::total 0.019667 # miss rate for ReadReq accesses
|
|
system.cpu3.icache.demand_miss_rate::cpu3.inst 0.019667 # miss rate for demand accesses
|
|
system.cpu3.icache.demand_miss_rate::total 0.019667 # miss rate for demand accesses
|
|
system.cpu3.icache.overall_miss_rate::cpu3.inst 0.019667 # miss rate for overall accesses
|
|
system.cpu3.icache.overall_miss_rate::total 0.019667 # miss rate for overall accesses
|
|
system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 13043.157895 # average ReadReq miss latency
|
|
system.cpu3.icache.ReadReq_avg_miss_latency::total 13043.157895 # average ReadReq miss latency
|
|
system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 13043.157895 # average overall miss latency
|
|
system.cpu3.icache.demand_avg_miss_latency::total 13043.157895 # average overall miss latency
|
|
system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 13043.157895 # average overall miss latency
|
|
system.cpu3.icache.overall_avg_miss_latency::total 13043.157895 # average overall miss latency
|
|
system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu3.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu3.icache.fast_writes 0 # number of fast writes performed
|
|
system.cpu3.icache.cache_copies 0 # number of cache copies performed
|
|
system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 46 # number of ReadReq MSHR hits
|
|
system.cpu3.icache.ReadReq_mshr_hits::total 46 # number of ReadReq MSHR hits
|
|
system.cpu3.icache.demand_mshr_hits::cpu3.inst 46 # number of demand (read+write) MSHR hits
|
|
system.cpu3.icache.demand_mshr_hits::total 46 # number of demand (read+write) MSHR hits
|
|
system.cpu3.icache.overall_mshr_hits::cpu3.inst 46 # number of overall MSHR hits
|
|
system.cpu3.icache.overall_mshr_hits::total 46 # number of overall MSHR hits
|
|
system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 429 # number of ReadReq MSHR misses
|
|
system.cpu3.icache.ReadReq_mshr_misses::total 429 # number of ReadReq MSHR misses
|
|
system.cpu3.icache.demand_mshr_misses::cpu3.inst 429 # number of demand (read+write) MSHR misses
|
|
system.cpu3.icache.demand_mshr_misses::total 429 # number of demand (read+write) MSHR misses
|
|
system.cpu3.icache.overall_mshr_misses::cpu3.inst 429 # number of overall MSHR misses
|
|
system.cpu3.icache.overall_mshr_misses::total 429 # number of overall MSHR misses
|
|
system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 4977500 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.icache.ReadReq_mshr_miss_latency::total 4977500 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 4977500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.icache.demand_mshr_miss_latency::total 4977500 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 4977500 # number of overall MSHR miss cycles
|
|
system.cpu3.icache.overall_mshr_miss_latency::total 4977500 # number of overall MSHR miss cycles
|
|
system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.017763 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.017763 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.017763 # mshr miss rate for demand accesses
|
|
system.cpu3.icache.demand_mshr_miss_rate::total 0.017763 # mshr miss rate for demand accesses
|
|
system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.017763 # mshr miss rate for overall accesses
|
|
system.cpu3.icache.overall_mshr_miss_rate::total 0.017763 # mshr miss rate for overall accesses
|
|
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 11602.564103 # average ReadReq mshr miss latency
|
|
system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 11602.564103 # average ReadReq mshr miss latency
|
|
system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 11602.564103 # average overall mshr miss latency
|
|
system.cpu3.icache.demand_avg_mshr_miss_latency::total 11602.564103 # average overall mshr miss latency
|
|
system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 11602.564103 # average overall mshr miss latency
|
|
system.cpu3.icache.overall_avg_mshr_miss_latency::total 11602.564103 # average overall mshr miss latency
|
|
system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.cpu3.dcache.replacements 0 # number of replacements
|
|
system.cpu3.dcache.tagsinuse 24.570062 # Cycle average of tags in use
|
|
system.cpu3.dcache.total_refs 34044 # Total number of references to valid blocks.
|
|
system.cpu3.dcache.sampled_refs 28 # Sample count of references to valid blocks.
|
|
system.cpu3.dcache.avg_refs 1215.857143 # Average number of references to valid blocks.
|
|
system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.cpu3.dcache.occ_blocks::cpu3.data 24.570062 # Average occupied blocks per requestor
|
|
system.cpu3.dcache.occ_percent::cpu3.data 0.047988 # Average percentage of cache occupancy
|
|
system.cpu3.dcache.occ_percent::total 0.047988 # Average percentage of cache occupancy
|
|
system.cpu3.dcache.ReadReq_hits::cpu3.data 39468 # number of ReadReq hits
|
|
system.cpu3.dcache.ReadReq_hits::total 39468 # number of ReadReq hits
|
|
system.cpu3.dcache.WriteReq_hits::cpu3.data 27827 # number of WriteReq hits
|
|
system.cpu3.dcache.WriteReq_hits::total 27827 # number of WriteReq hits
|
|
system.cpu3.dcache.SwapReq_hits::cpu3.data 14 # number of SwapReq hits
|
|
system.cpu3.dcache.SwapReq_hits::total 14 # number of SwapReq hits
|
|
system.cpu3.dcache.demand_hits::cpu3.data 67295 # number of demand (read+write) hits
|
|
system.cpu3.dcache.demand_hits::total 67295 # number of demand (read+write) hits
|
|
system.cpu3.dcache.overall_hits::cpu3.data 67295 # number of overall hits
|
|
system.cpu3.dcache.overall_hits::total 67295 # number of overall hits
|
|
system.cpu3.dcache.ReadReq_misses::cpu3.data 421 # number of ReadReq misses
|
|
system.cpu3.dcache.ReadReq_misses::total 421 # number of ReadReq misses
|
|
system.cpu3.dcache.WriteReq_misses::cpu3.data 138 # number of WriteReq misses
|
|
system.cpu3.dcache.WriteReq_misses::total 138 # number of WriteReq misses
|
|
system.cpu3.dcache.SwapReq_misses::cpu3.data 58 # number of SwapReq misses
|
|
system.cpu3.dcache.SwapReq_misses::total 58 # number of SwapReq misses
|
|
system.cpu3.dcache.demand_misses::cpu3.data 559 # number of demand (read+write) misses
|
|
system.cpu3.dcache.demand_misses::total 559 # number of demand (read+write) misses
|
|
system.cpu3.dcache.overall_misses::cpu3.data 559 # number of overall misses
|
|
system.cpu3.dcache.overall_misses::total 559 # number of overall misses
|
|
system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 5610000 # number of ReadReq miss cycles
|
|
system.cpu3.dcache.ReadReq_miss_latency::total 5610000 # number of ReadReq miss cycles
|
|
system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2578000 # number of WriteReq miss cycles
|
|
system.cpu3.dcache.WriteReq_miss_latency::total 2578000 # number of WriteReq miss cycles
|
|
system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 603500 # number of SwapReq miss cycles
|
|
system.cpu3.dcache.SwapReq_miss_latency::total 603500 # number of SwapReq miss cycles
|
|
system.cpu3.dcache.demand_miss_latency::cpu3.data 8188000 # number of demand (read+write) miss cycles
|
|
system.cpu3.dcache.demand_miss_latency::total 8188000 # number of demand (read+write) miss cycles
|
|
system.cpu3.dcache.overall_miss_latency::cpu3.data 8188000 # number of overall miss cycles
|
|
system.cpu3.dcache.overall_miss_latency::total 8188000 # number of overall miss cycles
|
|
system.cpu3.dcache.ReadReq_accesses::cpu3.data 39889 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.dcache.ReadReq_accesses::total 39889 # number of ReadReq accesses(hits+misses)
|
|
system.cpu3.dcache.WriteReq_accesses::cpu3.data 27965 # number of WriteReq accesses(hits+misses)
|
|
system.cpu3.dcache.WriteReq_accesses::total 27965 # number of WriteReq accesses(hits+misses)
|
|
system.cpu3.dcache.SwapReq_accesses::cpu3.data 72 # number of SwapReq accesses(hits+misses)
|
|
system.cpu3.dcache.SwapReq_accesses::total 72 # number of SwapReq accesses(hits+misses)
|
|
system.cpu3.dcache.demand_accesses::cpu3.data 67854 # number of demand (read+write) accesses
|
|
system.cpu3.dcache.demand_accesses::total 67854 # number of demand (read+write) accesses
|
|
system.cpu3.dcache.overall_accesses::cpu3.data 67854 # number of overall (read+write) accesses
|
|
system.cpu3.dcache.overall_accesses::total 67854 # number of overall (read+write) accesses
|
|
system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.010554 # miss rate for ReadReq accesses
|
|
system.cpu3.dcache.ReadReq_miss_rate::total 0.010554 # miss rate for ReadReq accesses
|
|
system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.004935 # miss rate for WriteReq accesses
|
|
system.cpu3.dcache.WriteReq_miss_rate::total 0.004935 # miss rate for WriteReq accesses
|
|
system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.805556 # miss rate for SwapReq accesses
|
|
system.cpu3.dcache.SwapReq_miss_rate::total 0.805556 # miss rate for SwapReq accesses
|
|
system.cpu3.dcache.demand_miss_rate::cpu3.data 0.008238 # miss rate for demand accesses
|
|
system.cpu3.dcache.demand_miss_rate::total 0.008238 # miss rate for demand accesses
|
|
system.cpu3.dcache.overall_miss_rate::cpu3.data 0.008238 # miss rate for overall accesses
|
|
system.cpu3.dcache.overall_miss_rate::total 0.008238 # miss rate for overall accesses
|
|
system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 13325.415677 # average ReadReq miss latency
|
|
system.cpu3.dcache.ReadReq_avg_miss_latency::total 13325.415677 # average ReadReq miss latency
|
|
system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 18681.159420 # average WriteReq miss latency
|
|
system.cpu3.dcache.WriteReq_avg_miss_latency::total 18681.159420 # average WriteReq miss latency
|
|
system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 10405.172414 # average SwapReq miss latency
|
|
system.cpu3.dcache.SwapReq_avg_miss_latency::total 10405.172414 # average SwapReq miss latency
|
|
system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 14647.584973 # average overall miss latency
|
|
system.cpu3.dcache.demand_avg_miss_latency::total 14647.584973 # average overall miss latency
|
|
system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 14647.584973 # average overall miss latency
|
|
system.cpu3.dcache.overall_avg_miss_latency::total 14647.584973 # average overall miss latency
|
|
system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.cpu3.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.cpu3.dcache.fast_writes 0 # number of fast writes performed
|
|
system.cpu3.dcache.cache_copies 0 # number of cache copies performed
|
|
system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 258 # number of ReadReq MSHR hits
|
|
system.cpu3.dcache.ReadReq_mshr_hits::total 258 # number of ReadReq MSHR hits
|
|
system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 32 # number of WriteReq MSHR hits
|
|
system.cpu3.dcache.WriteReq_mshr_hits::total 32 # number of WriteReq MSHR hits
|
|
system.cpu3.dcache.demand_mshr_hits::cpu3.data 290 # number of demand (read+write) MSHR hits
|
|
system.cpu3.dcache.demand_mshr_hits::total 290 # number of demand (read+write) MSHR hits
|
|
system.cpu3.dcache.overall_mshr_hits::cpu3.data 290 # number of overall MSHR hits
|
|
system.cpu3.dcache.overall_mshr_hits::total 290 # number of overall MSHR hits
|
|
system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 163 # number of ReadReq MSHR misses
|
|
system.cpu3.dcache.ReadReq_mshr_misses::total 163 # number of ReadReq MSHR misses
|
|
system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 106 # number of WriteReq MSHR misses
|
|
system.cpu3.dcache.WriteReq_mshr_misses::total 106 # number of WriteReq MSHR misses
|
|
system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 58 # number of SwapReq MSHR misses
|
|
system.cpu3.dcache.SwapReq_mshr_misses::total 58 # number of SwapReq MSHR misses
|
|
system.cpu3.dcache.demand_mshr_misses::cpu3.data 269 # number of demand (read+write) MSHR misses
|
|
system.cpu3.dcache.demand_mshr_misses::total 269 # number of demand (read+write) MSHR misses
|
|
system.cpu3.dcache.overall_mshr_misses::cpu3.data 269 # number of overall MSHR misses
|
|
system.cpu3.dcache.overall_mshr_misses::total 269 # number of overall MSHR misses
|
|
system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1447000 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1447000 # number of ReadReq MSHR miss cycles
|
|
system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1250000 # number of WriteReq MSHR miss cycles
|
|
system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1250000 # number of WriteReq MSHR miss cycles
|
|
system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 487500 # number of SwapReq MSHR miss cycles
|
|
system.cpu3.dcache.SwapReq_mshr_miss_latency::total 487500 # number of SwapReq MSHR miss cycles
|
|
system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2697000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.dcache.demand_mshr_miss_latency::total 2697000 # number of demand (read+write) MSHR miss cycles
|
|
system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2697000 # number of overall MSHR miss cycles
|
|
system.cpu3.dcache.overall_mshr_miss_latency::total 2697000 # number of overall MSHR miss cycles
|
|
system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.004086 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.004086 # mshr miss rate for ReadReq accesses
|
|
system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.003790 # mshr miss rate for WriteReq accesses
|
|
system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.003790 # mshr miss rate for WriteReq accesses
|
|
system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.805556 # mshr miss rate for SwapReq accesses
|
|
system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.805556 # mshr miss rate for SwapReq accesses
|
|
system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.003964 # mshr miss rate for demand accesses
|
|
system.cpu3.dcache.demand_mshr_miss_rate::total 0.003964 # mshr miss rate for demand accesses
|
|
system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.003964 # mshr miss rate for overall accesses
|
|
system.cpu3.dcache.overall_mshr_miss_rate::total 0.003964 # mshr miss rate for overall accesses
|
|
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 8877.300613 # average ReadReq mshr miss latency
|
|
system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 8877.300613 # average ReadReq mshr miss latency
|
|
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 11792.452830 # average WriteReq mshr miss latency
|
|
system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 11792.452830 # average WriteReq mshr miss latency
|
|
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 8405.172414 # average SwapReq mshr miss latency
|
|
system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 8405.172414 # average SwapReq mshr miss latency
|
|
system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 10026.022305 # average overall mshr miss latency
|
|
system.cpu3.dcache.demand_avg_mshr_miss_latency::total 10026.022305 # average overall mshr miss latency
|
|
system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 10026.022305 # average overall mshr miss latency
|
|
system.cpu3.dcache.overall_avg_mshr_miss_latency::total 10026.022305 # average overall mshr miss latency
|
|
system.cpu3.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
system.l2c.replacements 0 # number of replacements
|
|
system.l2c.tagsinuse 425.302863 # Cycle average of tags in use
|
|
system.l2c.total_refs 1445 # Total number of references to valid blocks.
|
|
system.l2c.sampled_refs 527 # Sample count of references to valid blocks.
|
|
system.l2c.avg_refs 2.741935 # Average number of references to valid blocks.
|
|
system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
|
system.l2c.occ_blocks::writebacks 0.824834 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu0.inst 289.870828 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu0.data 59.081037 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu1.inst 62.204312 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu1.data 5.605545 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu2.inst 4.564656 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu2.data 0.760691 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu3.inst 1.668516 # Average occupied blocks per requestor
|
|
system.l2c.occ_blocks::cpu3.data 0.722445 # Average occupied blocks per requestor
|
|
system.l2c.occ_percent::writebacks 0.000013 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu0.inst 0.004423 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu0.data 0.000902 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu1.inst 0.000949 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu1.data 0.000086 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu2.inst 0.000070 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu2.data 0.000012 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu3.inst 0.000025 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::cpu3.data 0.000011 # Average percentage of cache occupancy
|
|
system.l2c.occ_percent::total 0.006490 # Average percentage of cache occupancy
|
|
system.l2c.ReadReq_hits::cpu0.inst 230 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.inst 343 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu1.data 5 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu2.inst 416 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu2.data 11 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu3.inst 424 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::cpu3.data 11 # number of ReadReq hits
|
|
system.l2c.ReadReq_hits::total 1445 # number of ReadReq hits
|
|
system.l2c.Writeback_hits::writebacks 1 # number of Writeback hits
|
|
system.l2c.Writeback_hits::total 1 # number of Writeback hits
|
|
system.l2c.UpgradeReq_hits::cpu0.data 3 # number of UpgradeReq hits
|
|
system.l2c.UpgradeReq_hits::total 3 # number of UpgradeReq hits
|
|
system.l2c.demand_hits::cpu0.inst 230 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.inst 343 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu1.data 5 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.inst 416 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu2.data 11 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu3.inst 424 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::cpu3.data 11 # number of demand (read+write) hits
|
|
system.l2c.demand_hits::total 1445 # number of demand (read+write) hits
|
|
system.l2c.overall_hits::cpu0.inst 230 # number of overall hits
|
|
system.l2c.overall_hits::cpu0.data 5 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.inst 343 # number of overall hits
|
|
system.l2c.overall_hits::cpu1.data 5 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.inst 416 # number of overall hits
|
|
system.l2c.overall_hits::cpu2.data 11 # number of overall hits
|
|
system.l2c.overall_hits::cpu3.inst 424 # number of overall hits
|
|
system.l2c.overall_hits::cpu3.data 11 # number of overall hits
|
|
system.l2c.overall_hits::total 1445 # number of overall hits
|
|
system.l2c.ReadReq_misses::cpu0.inst 360 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu0.data 74 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.inst 82 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu1.data 7 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu2.inst 14 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu3.inst 5 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq misses
|
|
system.l2c.ReadReq_misses::total 544 # number of ReadReq misses
|
|
system.l2c.UpgradeReq_misses::cpu0.data 18 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu1.data 20 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu2.data 17 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::cpu3.data 19 # number of UpgradeReq misses
|
|
system.l2c.UpgradeReq_misses::total 74 # number of UpgradeReq misses
|
|
system.l2c.ReadExReq_misses::cpu0.data 94 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu1.data 13 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu2.data 12 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::cpu3.data 12 # number of ReadExReq misses
|
|
system.l2c.ReadExReq_misses::total 131 # number of ReadExReq misses
|
|
system.l2c.demand_misses::cpu0.inst 360 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu0.data 168 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.inst 82 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu1.data 20 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.inst 14 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu2.data 13 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu3.inst 5 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::cpu3.data 13 # number of demand (read+write) misses
|
|
system.l2c.demand_misses::total 675 # number of demand (read+write) misses
|
|
system.l2c.overall_misses::cpu0.inst 360 # number of overall misses
|
|
system.l2c.overall_misses::cpu0.data 168 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.inst 82 # number of overall misses
|
|
system.l2c.overall_misses::cpu1.data 20 # number of overall misses
|
|
system.l2c.overall_misses::cpu2.inst 14 # number of overall misses
|
|
system.l2c.overall_misses::cpu2.data 13 # number of overall misses
|
|
system.l2c.overall_misses::cpu3.inst 5 # number of overall misses
|
|
system.l2c.overall_misses::cpu3.data 13 # number of overall misses
|
|
system.l2c.overall_misses::total 675 # number of overall misses
|
|
system.l2c.ReadReq_miss_latency::cpu0.inst 18249500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu0.data 4603000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.inst 4327000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu1.data 666000 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu2.inst 840500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu2.data 68500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu3.inst 216500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::cpu3.data 68500 # number of ReadReq miss cycles
|
|
system.l2c.ReadReq_miss_latency::total 29039500 # number of ReadReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu0.data 5402500 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu1.data 997000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu2.data 868500 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::cpu3.data 757000 # number of ReadExReq miss cycles
|
|
system.l2c.ReadExReq_miss_latency::total 8025000 # number of ReadExReq miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.inst 18249500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu0.data 10005500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.inst 4327000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu1.data 1663000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu2.inst 840500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu2.data 937000 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu3.inst 216500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::cpu3.data 825500 # number of demand (read+write) miss cycles
|
|
system.l2c.demand_miss_latency::total 37064500 # number of demand (read+write) miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.inst 18249500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu0.data 10005500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.inst 4327000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu1.data 1663000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu2.inst 840500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu2.data 937000 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu3.inst 216500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::cpu3.data 825500 # number of overall miss cycles
|
|
system.l2c.overall_miss_latency::total 37064500 # number of overall miss cycles
|
|
system.l2c.ReadReq_accesses::cpu0.inst 590 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu0.data 79 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.inst 425 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu1.data 12 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu2.inst 430 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu2.data 12 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu3.inst 429 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::cpu3.data 12 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.ReadReq_accesses::total 1989 # number of ReadReq accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::writebacks 1 # number of Writeback accesses(hits+misses)
|
|
system.l2c.Writeback_accesses::total 1 # number of Writeback accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu0.data 21 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu1.data 20 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu2.data 17 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::cpu3.data 19 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.UpgradeReq_accesses::total 77 # number of UpgradeReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu0.data 94 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu1.data 13 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::cpu3.data 12 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.ReadExReq_accesses::total 131 # number of ReadExReq accesses(hits+misses)
|
|
system.l2c.demand_accesses::cpu0.inst 590 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu0.data 173 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.inst 425 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu1.data 25 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu2.inst 430 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu2.data 24 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu3.inst 429 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::cpu3.data 24 # number of demand (read+write) accesses
|
|
system.l2c.demand_accesses::total 2120 # number of demand (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.inst 590 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu0.data 173 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.inst 425 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu1.data 25 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu2.inst 430 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu2.data 24 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu3.inst 429 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::cpu3.data 24 # number of overall (read+write) accesses
|
|
system.l2c.overall_accesses::total 2120 # number of overall (read+write) accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.inst 0.610169 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu0.data 0.936709 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.inst 0.192941 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu1.data 0.583333 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu2.inst 0.032558 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu2.data 0.083333 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu3.inst 0.011655 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::cpu3.data 0.083333 # miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_miss_rate::total 0.273504 # miss rate for ReadReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.857143 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu1.data 1 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu2.data 1 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::cpu3.data 1 # miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_miss_rate::total 0.961039 # miss rate for UpgradeReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
|
|
system.l2c.demand_miss_rate::cpu0.inst 0.610169 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu0.data 0.971098 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.inst 0.192941 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu1.data 0.800000 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu2.inst 0.032558 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu2.data 0.541667 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu3.inst 0.011655 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::cpu3.data 0.541667 # miss rate for demand accesses
|
|
system.l2c.demand_miss_rate::total 0.318396 # miss rate for demand accesses
|
|
system.l2c.overall_miss_rate::cpu0.inst 0.610169 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu0.data 0.971098 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.inst 0.192941 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu1.data 0.800000 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu2.inst 0.032558 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu2.data 0.541667 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu3.inst 0.011655 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::cpu3.data 0.541667 # miss rate for overall accesses
|
|
system.l2c.overall_miss_rate::total 0.318396 # miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.inst 50693.055556 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu0.data 62202.702703 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 52768.292683 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu1.data 95142.857143 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 60035.714286 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu2.data 68500 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu3.inst 43300 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::cpu3.data 68500 # average ReadReq miss latency
|
|
system.l2c.ReadReq_avg_miss_latency::total 53381.433824 # average ReadReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu0.data 57473.404255 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 76692.307692 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 72375 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::cpu3.data 63083.333333 # average ReadExReq miss latency
|
|
system.l2c.ReadExReq_avg_miss_latency::total 61259.541985 # average ReadExReq miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.inst 50693.055556 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu0.data 59556.547619 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.inst 52768.292683 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu1.data 83150 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu2.inst 60035.714286 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu2.data 72076.923077 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu3.inst 43300 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::cpu3.data 63500 # average overall miss latency
|
|
system.l2c.demand_avg_miss_latency::total 54910.370370 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.inst 50693.055556 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu0.data 59556.547619 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.inst 52768.292683 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu1.data 83150 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu2.inst 60035.714286 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu2.data 72076.923077 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu3.inst 43300 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::cpu3.data 63500 # average overall miss latency
|
|
system.l2c.overall_avg_miss_latency::total 54910.370370 # average overall miss latency
|
|
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
|
|
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
|
|
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
|
|
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
|
|
system.l2c.fast_writes 0 # number of fast writes performed
|
|
system.l2c.cache_copies 0 # number of cache copies performed
|
|
system.l2c.ReadReq_mshr_hits::cpu0.inst 2 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_hits::cpu1.inst 4 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_hits::cpu2.inst 6 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_hits::cpu3.inst 2 # number of ReadReq MSHR hits
|
|
system.l2c.ReadReq_mshr_hits::total 14 # number of ReadReq MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu0.inst 2 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu1.inst 4 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu2.inst 6 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::cpu3.inst 2 # number of demand (read+write) MSHR hits
|
|
system.l2c.demand_mshr_hits::total 14 # number of demand (read+write) MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu0.inst 2 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu1.inst 4 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu2.inst 6 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::cpu3.inst 2 # number of overall MSHR hits
|
|
system.l2c.overall_mshr_hits::total 14 # number of overall MSHR hits
|
|
system.l2c.ReadReq_mshr_misses::cpu0.inst 358 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu0.data 74 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu1.inst 78 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu1.data 7 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu2.inst 8 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu2.data 1 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu3.inst 3 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::cpu3.data 1 # number of ReadReq MSHR misses
|
|
system.l2c.ReadReq_mshr_misses::total 530 # number of ReadReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu0.data 18 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu1.data 20 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu2.data 17 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::cpu3.data 19 # number of UpgradeReq MSHR misses
|
|
system.l2c.UpgradeReq_mshr_misses::total 74 # number of UpgradeReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu0.data 94 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu1.data 13 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu2.data 12 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::cpu3.data 12 # number of ReadExReq MSHR misses
|
|
system.l2c.ReadExReq_mshr_misses::total 131 # number of ReadExReq MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.inst 358 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu0.data 168 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.inst 78 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu1.data 20 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu2.inst 8 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu2.data 13 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu3.inst 3 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::cpu3.data 13 # number of demand (read+write) MSHR misses
|
|
system.l2c.demand_mshr_misses::total 661 # number of demand (read+write) MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.inst 358 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu0.data 168 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.inst 78 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu1.data 20 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu2.inst 8 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu2.data 13 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu3.inst 3 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::cpu3.data 13 # number of overall MSHR misses
|
|
system.l2c.overall_mshr_misses::total 661 # number of overall MSHR misses
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.inst 13764287 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu0.data 3693044 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 3149062 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 578256 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 315757 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu2.data 56251 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu3.inst 113753 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::cpu3.data 56251 # number of ReadReq MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_latency::total 21726661 # number of ReadReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu0.data 184010 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 201018 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 172013 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::cpu3.data 200514 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.UpgradeReq_mshr_miss_latency::total 757555 # number of UpgradeReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 4247058 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 839755 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 720010 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 608510 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.ReadExReq_mshr_miss_latency::total 6415333 # number of ReadExReq MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.inst 13764287 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu0.data 7940102 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.inst 3149062 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu1.data 1418011 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu2.inst 315757 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu2.data 776261 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu3.inst 113753 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::cpu3.data 664761 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.demand_mshr_miss_latency::total 28141994 # number of demand (read+write) MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.inst 13764287 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu0.data 7940102 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.inst 3149062 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu1.data 1418011 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu2.inst 315757 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu2.data 776261 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu3.inst 113753 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::cpu3.data 664761 # number of overall MSHR miss cycles
|
|
system.l2c.overall_mshr_miss_latency::total 28141994 # number of overall MSHR miss cycles
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.606780 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.936709 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.183529 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.583333 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.018605 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.083333 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.006993 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.083333 # mshr miss rate for ReadReq accesses
|
|
system.l2c.ReadReq_mshr_miss_rate::total 0.266466 # mshr miss rate for ReadReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.857143 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.UpgradeReq_mshr_miss_rate::total 0.961039 # mshr miss rate for UpgradeReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.inst 0.606780 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.183529 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.018605 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu3.inst 0.006993 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for demand accesses
|
|
system.l2c.demand_mshr_miss_rate::total 0.311792 # mshr miss rate for demand accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.inst 0.606780 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu0.data 0.971098 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.183529 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu1.data 0.800000 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.018605 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu2.data 0.541667 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu3.inst 0.006993 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::cpu3.data 0.541667 # mshr miss rate for overall accesses
|
|
system.l2c.overall_mshr_miss_rate::total 0.311792 # mshr miss rate for overall accesses
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 38447.729050 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 49906 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40372.589744 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 82608 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 39469.625000 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 56251 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.inst 37917.666667 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 56251 # average ReadReq mshr miss latency
|
|
system.l2c.ReadReq_avg_mshr_miss_latency::total 40993.700000 # average ReadReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10222.777778 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10050.900000 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10118.411765 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu3.data 10553.368421 # average UpgradeReq mshr miss latency
|
|
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10237.229730 # average UpgradeReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 45181.468085 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 64596.538462 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 60000.833333 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 50709.166667 # average ReadExReq mshr miss latency
|
|
system.l2c.ReadExReq_avg_mshr_miss_latency::total 48972.007634 # average ReadExReq mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 38447.729050 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu0.data 47262.511905 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40372.589744 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 70900.550000 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 39469.625000 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 59712.384615 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 37917.666667 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::cpu3.data 51135.461538 # average overall mshr miss latency
|
|
system.l2c.demand_avg_mshr_miss_latency::total 42574.877458 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 38447.729050 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu0.data 47262.511905 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40372.589744 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 70900.550000 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 39469.625000 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 59712.384615 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 37917.666667 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::cpu3.data 51135.461538 # average overall mshr miss latency
|
|
system.l2c.overall_avg_mshr_miss_latency::total 42574.877458 # average overall mshr miss latency
|
|
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
|
|
|
|
---------- End Simulation Statistics ----------
|