3bc4ecdcb4
This patch changes the class names of the variuos DRAM configurations to better reflect what memory they are based on. The speed and interface width is now part of the name, and also the alias that is used to select them on the command line. Some minor changes are done to the actual parameters, to better reflect the named configurations. As a result of these changes the regressions change slightly and the stats will be bumped in a separate patch.
82 lines
3.4 KiB
Python
82 lines
3.4 KiB
Python
# Copyright (c) 2012 Mark D. Hill and David A. Wood
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Nilay Vaish
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import m5, os, optparse, sys
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from m5.objects import *
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m5.util.addToPath('../configs/common')
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from Benchmarks import SysConfig
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import FSConfig
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m5.util.addToPath('../configs/ruby')
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m5.util.addToPath('../configs/topologies')
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import Ruby
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import Options
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# Add the ruby specific and protocol specific options
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parser = optparse.OptionParser()
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Options.addCommonOptions(parser)
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Ruby.define_options(parser)
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(options, args) = parser.parse_args()
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# Set the default cache size and associativity to be very small to encourage
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# races between requests and writebacks.
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options.l1d_size="32kB"
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options.l1i_size="32kB"
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options.l2_size="4MB"
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options.l1d_assoc=2
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options.l1i_assoc=2
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options.l2_assoc=2
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options.num_cpus = 2
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#the system
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mdesc = SysConfig(disk = 'linux-x86.img')
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system = FSConfig.makeLinuxX86System('timing', DDR3_1600_x64, options.num_cpus,
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mdesc=mdesc, Ruby=True)
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system.kernel = FSConfig.binary('x86_64-vmlinux-2.6.22.9.smp')
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system.cpu = [TimingSimpleCPU(cpu_id=i) for i in xrange(options.num_cpus)]
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Ruby.create_system(options, system, system.piobus, system._dma_ports)
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for (i, cpu) in enumerate(system.cpu):
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# create the interrupt controller
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cpu.createInterruptController()
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# Tie the cpu ports to the correct ruby system ports
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cpu.icache_port = system.ruby._cpu_ruby_ports[i].slave
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cpu.dcache_port = system.ruby._cpu_ruby_ports[i].slave
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cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].slave
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cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].slave
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cpu.interrupts.pio = system.piobus.master
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cpu.interrupts.int_master = system.piobus.slave
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cpu.interrupts.int_slave = system.piobus.master
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cpu.clock = '2GHz'
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# Set access_phys_mem to True for ruby port
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system.ruby._cpu_ruby_ports[i].access_phys_mem = True
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root = Root(full_system = True, system = system)
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m5.ticks.setGlobalFrequency('1THz')
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