b64eae5e52
SConscript:
Added more files to compile: dev/pcifake.cc, dev/isa_fake.cc, kern/freebsd/freebsd_system.cc, kern/freebsd/freebsd_events.cc.
arch/alpha/isa_traits.hh:
Added constant for argument register 2 as it is needed by FreebsdSystem::doCalibrateClocks().
cpu/exec_context.hh:
cpu/o3/alpha_cpu.hh:
Replaced htoa()s with gtoh() and htog().
cpu/o3/fetch_impl.hh:
cpu/simple/cpu.cc:
Replaced htoa() with gtoh().
dev/disk_image.cc:
Replaced htoa()s with letoh()s.
dev/ide_ctrl.cc:
Got rid of magic numbers.
Added IdeChannel and IdeRegType type names where necessary.
dev/ide_ctrl.hh:
Got rid of unnecessary macros.
Changed RegType_t to IdeRegType.
Changed bmi_regs to allow accessing registers by name instead of just by array index.
Added IdeChannel enum type to use in place of bool variables which were used to specify IDE channel.
dev/ide_disk.cc:
Rewrote IdeDisk::read and IdeDisk::write functions to specify registers by name instead of indexing through an array.
dev/ide_disk.hh:
Updated command register struct.
dev/ns_gige.cc:
dev/ns_gige.hh:
Made ReadConfig and WriteConfig begin with a lower-case letter.
writeConfig() now takes a pointer to data as a parameter instead of a copy of data.
dev/pciconfigall.cc:
writeConfig() now takes a pointer to data as a parameter instead of a copy of data.
dev/pcidev.cc:
Cleaned up readConfig() and writeConfig() functions.
dev/pcidev.hh:
Added macros to make code that works with the BARs (base adress registers) more readable. writeConfig() now takes a pointer to data.
dev/pcireg.h:
Changed PCIConfig struct to make accessing elements more straight forward. Removed type 1 (for PCI-to-PCI bridges) PCI configuration space struct since it is not used.
dev/rtcreg.h:
Added macros for bit fields in RTC status registers A & B.
dev/sinic.cc:
Function name change: WriteConfig --> writeConfig.
writeConfig() now takes a pointer to data instead of a copy of data.
The accessing of elements of PCIConfig structure is updated.
dev/sinic.hh:
Function name change: WriteConfig --> writeConfig.
writeConfig() now takes a pointer to data instead of a copy of data.
dev/tsunami_io.cc:
Added implementation of new RTC and PIT classes.
dev/tsunami_io.hh:
Added classes for RTC and PIT modules.
dev/tsunamireg.h:
Added macros for DMA ports used by Tsunami-Tru64.
dev/uart8250.cc:
Got rid of a magic number.
Transmit (Tx) interrupts should clear upon a read of the Interrupt ID register.
dev/uart8250.hh:
Added comments and macros dealing with the UART Interrupt ID register.
kern/linux/linux_system.cc:
Replaced htoa() with htog().
python/m5/objects/Pci.py:
PciFake is a python class for Pci Devices that do nothing.
python/m5/objects/Tsunami.py:
TsunamiFake was renamed as IsaFake.
sim/system.cc:
Replaced htoa()s with htog()s.
dev/isa_fake.cc:
New BitKeeper file ``dev/isa_fake.cc''
TsunamiFake was renamed as IsaFake.
dev/isa_fake.hh:
New BitKeeper file ``dev/isa_fake.hh''
TsunmaiFake was renamed as IsaFake.
dev/pitreg.h:
New BitKeeper file ``dev/pitreg.h''
Useful macros for working with PIT (Periodic Interval Timer) registers.
--HG--
extra : convert_revision : 33f3a8a1034af4f6c71b32dd743e371c8613e780
157 lines
6 KiB
C
157 lines
6 KiB
C
/*
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* Copyright (c) 2001-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/* @file
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* Device register definitions for a device's PCI config space
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*/
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#ifndef __PCIREG_H__
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#define __PCIREG_H__
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#include <sys/types.h>
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union PCIConfig {
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uint8_t data[64];
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struct {
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uint16_t vendor;
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uint16_t device;
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uint16_t command;
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uint16_t status;
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uint8_t revision;
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uint8_t progIF;
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uint8_t subClassCode;
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uint8_t classCode;
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uint8_t cacheLineSize;
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uint8_t latencyTimer;
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uint8_t headerType;
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uint8_t bist;
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union {
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uint32_t baseAddr[6];
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struct {
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uint32_t baseAddr0;
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uint32_t baseAddr1;
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uint32_t baseAddr2;
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uint32_t baseAddr3;
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uint32_t baseAddr4;
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uint32_t baseAddr5;
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};
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};
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uint32_t cardbusCIS;
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uint16_t subsystemVendorID;
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uint16_t subsystemID;
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uint32_t expansionROM;
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uint32_t reserved0;
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uint32_t reserved1;
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uint8_t interruptLine;
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uint8_t interruptPin;
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uint8_t minimumGrant;
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uint8_t maximumLatency;
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};
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};
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// Common PCI offsets
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#define PCI_VENDOR_ID 0x00 // Vendor ID ro
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#define PCI_DEVICE_ID 0x02 // Device ID ro
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#define PCI_COMMAND 0x04 // Command rw
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#define PCI_STATUS 0x06 // Status rw
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#define PCI_REVISION_ID 0x08 // Revision ID ro
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#define PCI_CLASS_CODE 0x09 // Class Code ro
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#define PCI_SUB_CLASS_CODE 0x0A // Sub Class Code ro
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#define PCI_BASE_CLASS_CODE 0x0B // Base Class Code ro
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#define PCI_CACHE_LINE_SIZE 0x0C // Cache Line Size ro+
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#define PCI_LATENCY_TIMER 0x0D // Latency Timer ro+
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#define PCI_HEADER_TYPE 0x0E // Header Type ro
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#define PCI_BIST 0x0F // Built in self test rw
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// some pci command reg bitfields
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#define PCI_CMD_BME 0x04 // Bus master function enable
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#define PCI_CMD_MSE 0x02 // Memory Space Access enable
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#define PCI_CMD_IOSE 0x01 // I/O space enable
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// Type 0 PCI offsets
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#define PCI0_BASE_ADDR0 0x10 // Base Address 0 rw
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#define PCI0_BASE_ADDR1 0x14 // Base Address 1 rw
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#define PCI0_BASE_ADDR2 0x18 // Base Address 2 rw
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#define PCI0_BASE_ADDR3 0x1C // Base Address 3 rw
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#define PCI0_BASE_ADDR4 0x20 // Base Address 4 rw
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#define PCI0_BASE_ADDR5 0x24 // Base Address 5 rw
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#define PCI0_CIS 0x28 // CardBus CIS Pointer ro
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#define PCI0_SUB_VENDOR_ID 0x2C // Sub-Vendor ID ro
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#define PCI0_SUB_SYSTEM_ID 0x2E // Sub-System ID ro
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#define PCI0_ROM_BASE_ADDR 0x30 // Expansion ROM Base Address rw
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#define PCI0_RESERVED0 0x34
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#define PCI0_RESERVED1 0x38
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#define PCI0_INTERRUPT_LINE 0x3C // Interrupt Line rw
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#define PCI0_INTERRUPT_PIN 0x3D // Interrupt Pin ro
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#define PCI0_MINIMUM_GRANT 0x3E // Maximum Grant ro
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#define PCI0_MAXIMUM_LATENCY 0x3F // Maximum Latency ro
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// Type 1 PCI offsets
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#define PCI1_BASE_ADDR0 0x10 // Base Address 0 rw
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#define PCI1_BASE_ADDR1 0x14 // Base Address 1 rw
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#define PCI1_PRI_BUS_NUM 0x18 // Primary Bus Number rw
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#define PCI1_SEC_BUS_NUM 0x19 // Secondary Bus Number rw
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#define PCI1_SUB_BUS_NUM 0x1A // Subordinate Bus Number rw
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#define PCI1_SEC_LAT_TIMER 0x1B // Secondary Latency Timer ro+
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#define PCI1_IO_BASE 0x1C // I/O Base rw
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#define PCI1_IO_LIMIT 0x1D // I/O Limit rw
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#define PCI1_SECONDARY_STATUS 0x1E // Secondary Status rw
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#define PCI1_MEM_BASE 0x20 // Memory Base rw
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#define PCI1_MEM_LIMIT 0x22 // Memory Limit rw
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#define PCI1_PRF_MEM_BASE 0x24 // Prefetchable Memory Base rw
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#define PCI1_PRF_MEM_LIMIT 0x26 // Prefetchable Memory Limit rw
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#define PCI1_PRF_BASE_UPPER 0x28 // Prefetchable Base Upper 32 rw
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#define PCI1_PRF_LIMIT_UPPER 0x2C // Prefetchable Limit Upper 32 rw
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#define PCI1_IO_BASE_UPPER 0x30 // I/O Base Upper 16 bits rw
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#define PCI1_IO_LIMIT_UPPER 0x32 // I/O Limit Upper 16 bits rw
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#define PCI1_RESERVED 0x34 // Reserved ro
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#define PCI1_ROM_BASE_ADDR 0x38 // Expansion ROM Base Address rw
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#define PCI1_INTR_LINE 0x3C // Interrupt Line rw
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#define PCI1_INTR_PIN 0x3D // Interrupt Pin ro
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#define PCI1_BRIDGE_CTRL 0x3E // Bridge Control rw
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// Device specific offsets
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#define PCI_DEVICE_SPECIFIC 0x40 // 192 bytes
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// Some Vendor IDs
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#define PCI_VENDOR_DEC 0x1011
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#define PCI_VENDOR_NCR 0x101A
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#define PCI_VENDOR_QLOGIC 0x1077
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#define PCI_VENDOR_SIMOS 0x1291
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// Some Product IDs
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#define PCI_PRODUCT_DEC_PZA 0x0008
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#define PCI_PRODUCT_NCR_810 0x0001
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#define PCI_PRODUCT_QLOGIC_ISP1020 0x1020
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#define PCI_PRODUCT_SIMOS_SIMOS 0x1291
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#define PCI_PRODUCT_SIMOS_ETHER 0x1292
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#endif // __PCIREG_H__
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