sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity
gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-switcheroo-full/stats.txt
Andreas Hansson fd9343eb85 arm: Bump stats after FS config script update 
This patch updates the stats to reflect the change in kernel options
needed for armv8 (but used for all FS regressions).
2014-02-19 07:59:46 -05:00

2166 lines
248 KiB
Text
Raw Blame History

---------- Begin Simulation Statistics ----------
sim_seconds 2.403672 # Number of seconds simulated
sim_ticks 2403671650000 # Number of ticks simulated
final_tick 2403671650000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 179946 # Simulator instruction rate (inst/s)
host_op_rate 231118 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 7169234406 # Simulator tick rate (ticks/s)
host_mem_usage 425424 # Number of bytes of host memory used
host_seconds 335.28 # Real time elapsed on the host
sim_insts 60331512 # Number of instructions simulated
sim_ops 77488235 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.itb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.inst 512456 # Number of bytes read from this memory
system.physmem.bytes_read::cpu0.data 7063576 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.dtb.walker 64 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.inst 64640 # Number of bytes read from this memory
system.physmem.bytes_read::cpu1.data 678080 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.dtb.walker 640 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.inst 186240 # Number of bytes read from this memory
system.physmem.bytes_read::cpu2.data 1335136 # Number of bytes read from this memory
system.physmem.bytes_read::total 124660096 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu0.inst 512456 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu1.inst 64640 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::cpu2.inst 186240 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 763336 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 3743616 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.data 1298488 # Number of bytes written to this memory
system.physmem.bytes_written::cpu1.data 159300 # Number of bytes written to this memory
system.physmem.bytes_written::cpu2.data 1558028 # Number of bytes written to this memory
system.physmem.bytes_written::total 6759432 # Number of bytes written to this memory
system.physmem.num_reads::realview.clcd 14352384 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.dtb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.itb.walker 2 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.inst 14219 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu0.data 110404 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.dtb.walker 1 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.inst 1010 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu1.data 10595 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.dtb.walker 10 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.inst 2910 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu2.data 20869 # Number of read requests responded to by this memory
system.physmem.num_reads::total 14512405 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 58494 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.data 324622 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu1.data 39825 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu2.data 389507 # Number of write requests responded to by this memory
system.physmem.num_writes::total 812448 # Number of write requests responded to by this memory
system.physmem.bw_read::realview.clcd 47768202 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.dtb.walker 27 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.itb.walker 53 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.inst 213197 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu0.data 2938661 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.dtb.walker 27 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.inst 26892 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu1.data 282102 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.dtb.walker 266 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.inst 77481 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu2.data 555457 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 51862365 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu0.inst 213197 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu1.inst 26892 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu2.inst 77481 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 317571 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 1557457 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.data 540210 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu1.data 66274 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu2.data 648187 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 2812128 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 1557457 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::realview.clcd 47768202 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.itb.walker 53 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.inst 213197 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu0.data 3478871 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.dtb.walker 27 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.inst 26892 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu1.data 348375 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.dtb.walker 266 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.inst 77481 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu2.data 1203644 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 54674493 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 13478771 # Number of read requests accepted
system.physmem.writeReqs 446331 # Number of write requests accepted
system.physmem.readBursts 13478771 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 446331 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 862641344 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 2859200 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 109811808 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 2805264 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 401653 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 2355 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 837730 # Per bank write bursts
system.physmem.perBankRdBursts::1 837384 # Per bank write bursts
system.physmem.perBankRdBursts::2 837568 # Per bank write bursts
system.physmem.perBankRdBursts::3 837998 # Per bank write bursts
system.physmem.perBankRdBursts::4 839137 # Per bank write bursts
system.physmem.perBankRdBursts::5 839827 # Per bank write bursts
system.physmem.perBankRdBursts::6 839940 # Per bank write bursts
system.physmem.perBankRdBursts::7 841195 # Per bank write bursts
system.physmem.perBankRdBursts::8 842685 # Per bank write bursts
system.physmem.perBankRdBursts::9 845257 # Per bank write bursts
system.physmem.perBankRdBursts::10 845425 # Per bank write bursts
system.physmem.perBankRdBursts::11 845905 # Per bank write bursts
system.physmem.perBankRdBursts::12 847162 # Per bank write bursts
system.physmem.perBankRdBursts::13 848062 # Per bank write bursts
system.physmem.perBankRdBursts::14 846854 # Per bank write bursts
system.physmem.perBankRdBursts::15 846642 # Per bank write bursts
system.physmem.perBankWrBursts::0 2730 # Per bank write bursts
system.physmem.perBankWrBursts::1 2572 # Per bank write bursts
system.physmem.perBankWrBursts::2 2588 # Per bank write bursts
system.physmem.perBankWrBursts::3 3028 # Per bank write bursts
system.physmem.perBankWrBursts::4 3463 # Per bank write bursts
system.physmem.perBankWrBursts::5 3194 # Per bank write bursts
system.physmem.perBankWrBursts::6 2521 # Per bank write bursts
system.physmem.perBankWrBursts::7 2322 # Per bank write bursts
system.physmem.perBankWrBursts::8 2234 # Per bank write bursts
system.physmem.perBankWrBursts::9 2386 # Per bank write bursts
system.physmem.perBankWrBursts::10 2377 # Per bank write bursts
system.physmem.perBankWrBursts::11 2814 # Per bank write bursts
system.physmem.perBankWrBursts::12 3729 # Per bank write bursts
system.physmem.perBankWrBursts::13 3501 # Per bank write bursts
system.physmem.perBankWrBursts::14 2651 # Per bank write bursts
system.physmem.perBankWrBursts::15 2565 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 2402635561500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 8 # Read request sizes (log2)
system.physmem.readPktSize::3 13443376 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 35387 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 429332 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 16999 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 985231 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 962596 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 957159 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 3278666 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2351782 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 2351346 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 2368287 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 47071 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 52789 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 17803 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 17814 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 17764 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 17625 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 17616 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 17601 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 17598 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 23 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 2018 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 2412 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 2043 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 2191 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 2298 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 2012 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 2026 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 2035 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1989 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1980 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1974 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1969 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1962 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1958 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1955 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 1952 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 1953 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 1961 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 1959 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 1949 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 1945 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 2054 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 57 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 26 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 48736 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 17758.945502 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 3164.892038 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 18326.287457 # Bytes accessed per row activation
system.physmem.bytesPerActivate::64-71 8690 17.83% 17.83% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-135 4827 9.90% 27.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::192-199 1035 2.12% 29.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-263 694 1.42% 31.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::320-327 398 0.82% 32.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-391 429 0.88% 32.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::448-455 259 0.53% 33.51% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-519 302 0.62% 34.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::576-583 176 0.36% 34.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-647 149 0.31% 34.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::704-711 171 0.35% 35.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-775 272 0.56% 35.71% # Bytes accessed per row activation
system.physmem.bytesPerActivate::832-839 78 0.16% 35.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-903 84 0.17% 36.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::960-967 41 0.08% 36.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1031 422 0.87% 36.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1088-1095 26 0.05% 37.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1152-1159 34 0.07% 37.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1216-1223 22 0.05% 37.16% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1280-1287 232 0.48% 37.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1344-1351 28 0.06% 37.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1408-1415 166 0.34% 38.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1472-1479 13 0.03% 38.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1536-1543 104 0.21% 38.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1600-1607 12 0.02% 38.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1664-1671 32 0.07% 38.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1728-1735 7 0.01% 38.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1792-1799 80 0.16% 38.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1856-1863 11 0.02% 38.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1920-1927 11 0.02% 38.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1984-1991 7 0.01% 38.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2048-2055 239 0.49% 39.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2112-2119 4 0.01% 39.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2176-2183 11 0.02% 39.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2240-2247 7 0.01% 39.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2304-2311 71 0.15% 39.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2368-2375 4 0.01% 39.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2432-2439 5 0.01% 39.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2496-2503 2 0.00% 39.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2560-2567 72 0.15% 39.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2624-2631 2 0.00% 39.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2688-2695 3 0.01% 39.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2752-2759 1 0.00% 39.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2816-2823 3 0.01% 39.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2880-2887 2 0.00% 39.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::2944-2951 6 0.01% 39.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3008-3015 4 0.01% 39.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3072-3079 360 0.74% 40.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3136-3143 3 0.01% 40.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3200-3207 3 0.01% 40.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3264-3271 2 0.00% 40.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3328-3335 69 0.14% 40.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3392-3399 3 0.01% 40.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3456-3463 6 0.01% 40.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3520-3527 6 0.01% 40.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3584-3591 67 0.14% 40.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3648-3655 5 0.01% 40.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3712-3719 8 0.02% 40.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3776-3783 5 0.01% 40.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3840-3847 67 0.14% 40.73% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3904-3911 5 0.01% 40.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::3968-3975 9 0.02% 40.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4032-4039 4 0.01% 40.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4096-4103 338 0.69% 41.46% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4160-4167 3 0.01% 41.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4224-4231 7 0.01% 41.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4288-4295 5 0.01% 41.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4352-4359 70 0.14% 41.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4416-4423 13 0.03% 41.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4480-4487 5 0.01% 41.68% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4544-4551 7 0.01% 41.69% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4608-4615 72 0.15% 41.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4672-4679 1 0.00% 41.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4736-4743 5 0.01% 41.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4800-4807 3 0.01% 41.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4864-4871 64 0.13% 41.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4928-4935 3 0.01% 41.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::4992-4999 4 0.01% 42.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5056-5063 3 0.01% 42.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5120-5127 280 0.57% 42.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5184-5191 1 0.00% 42.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5248-5255 2 0.00% 42.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5376-5383 73 0.15% 42.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5440-5447 4 0.01% 42.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5504-5511 4 0.01% 42.75% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5568-5575 1 0.00% 42.76% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5632-5639 129 0.26% 43.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5760-5767 2 0.00% 43.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5824-5831 4 0.01% 43.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::5888-5895 176 0.36% 43.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6016-6023 1 0.00% 43.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6080-6087 10 0.02% 43.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6144-6151 327 0.67% 44.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6208-6215 5 0.01% 44.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6272-6279 7 0.01% 44.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6336-6343 1 0.00% 44.12% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6400-6407 98 0.20% 44.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6464-6471 1 0.00% 44.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6528-6535 1 0.00% 44.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6592-6599 2 0.00% 44.32% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6656-6663 73 0.15% 44.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6720-6727 4 0.01% 44.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6784-6791 8 0.02% 44.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6848-6855 2 0.00% 44.50% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6912-6919 60 0.12% 44.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::6976-6983 5 0.01% 44.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7040-7047 2 0.00% 44.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7104-7111 3 0.01% 44.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7168-7175 268 0.55% 45.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7296-7303 1 0.00% 45.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7360-7367 7 0.01% 45.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7424-7431 66 0.14% 45.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7552-7559 2 0.00% 45.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7616-7623 1 0.00% 45.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7680-7687 64 0.13% 45.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::7936-7943 42 0.09% 45.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8064-8071 2 0.00% 45.58% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8192-8199 515 1.06% 46.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8448-8455 42 0.09% 46.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8704-8711 66 0.14% 46.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::8960-8967 65 0.13% 46.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9216-9223 267 0.55% 47.54% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9472-9479 59 0.12% 47.66% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9728-9735 69 0.14% 47.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::9984-9991 94 0.19% 47.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10240-10247 322 0.66% 48.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10496-10503 138 0.28% 48.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::10752-10759 128 0.26% 49.20% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11008-11015 70 0.14% 49.34% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11264-11271 279 0.57% 49.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11520-11527 60 0.12% 50.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11648-11655 1 0.00% 50.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::11776-11783 64 0.13% 50.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12032-12039 65 0.13% 50.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12288-12295 328 0.67% 50.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12544-12551 63 0.13% 51.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12608-12615 1 0.00% 51.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::12800-12807 64 0.13% 51.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13056-13063 64 0.13% 51.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13312-13319 357 0.73% 52.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13824-13831 65 0.13% 52.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::13952-13959 1 0.00% 52.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14080-14087 64 0.13% 52.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14208-14215 1 0.00% 52.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14336-14343 229 0.47% 52.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14592-14599 64 0.13% 52.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::14848-14855 64 0.13% 53.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15104-15111 190 0.39% 53.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15360-15367 321 0.66% 54.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::15616-15623 65 0.13% 54.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16128-16135 64 0.13% 54.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16384-16391 672 1.38% 55.80% # Bytes accessed per row activation
system.physmem.bytesPerActivate::16640-16647 64 0.13% 55.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17152-17159 64 0.13% 56.06% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17408-17415 321 0.66% 56.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17664-17671 189 0.39% 57.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::17920-17927 65 0.13% 57.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18176-18183 64 0.13% 57.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18304-18311 1 0.00% 57.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18368-18375 1 0.00% 57.37% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18432-18439 229 0.47% 57.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18688-18695 64 0.13% 57.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::18944-18951 63 0.13% 58.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19008-19015 1 0.00% 58.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19200-19207 1 0.00% 58.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19456-19463 357 0.73% 58.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19712-19719 65 0.13% 58.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19904-19911 1 0.00% 58.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::19968-19975 65 0.13% 59.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20224-20231 64 0.13% 59.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20288-20295 1 0.00% 59.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20352-20359 1 0.00% 59.25% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20480-20487 327 0.67% 59.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20608-20615 1 0.00% 59.92% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20736-20743 64 0.13% 60.05% # Bytes accessed per row activation
system.physmem.bytesPerActivate::20992-20999 64 0.13% 60.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21248-21255 61 0.13% 60.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21504-21511 274 0.56% 60.87% # Bytes accessed per row activation
system.physmem.bytesPerActivate::21760-21767 69 0.14% 61.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22016-22023 128 0.26% 61.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22272-22279 137 0.28% 61.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22336-22343 1 0.00% 61.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22528-22535 323 0.66% 62.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22784-22791 93 0.19% 62.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::22848-22855 1 0.00% 62.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23040-23047 68 0.14% 62.55% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23296-23303 57 0.12% 62.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23552-23559 268 0.55% 63.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::23808-23815 65 0.13% 63.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24064-24071 65 0.13% 63.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24320-24327 43 0.09% 63.57% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24576-24583 514 1.05% 64.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24768-24775 1 0.00% 64.63% # Bytes accessed per row activation
system.physmem.bytesPerActivate::24832-24839 42 0.09% 64.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25088-25095 66 0.14% 64.85% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25344-25351 64 0.13% 64.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25408-25415 1 0.00% 64.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25472-25479 1 0.00% 64.99% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25600-25607 264 0.54% 65.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25728-25735 1 0.00% 65.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::25856-25863 57 0.12% 65.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26112-26119 69 0.14% 65.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26368-26375 95 0.19% 65.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26624-26631 323 0.66% 66.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26752-26759 1 0.00% 66.65% # Bytes accessed per row activation
system.physmem.bytesPerActivate::26880-26887 137 0.28% 66.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27008-27015 1 0.00% 66.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27136-27143 127 0.26% 67.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27392-27399 68 0.14% 67.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27648-27655 275 0.56% 67.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::27904-27911 61 0.13% 68.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28160-28167 64 0.13% 68.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28416-28423 65 0.13% 68.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28672-28679 329 0.68% 68.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::28928-28935 65 0.13% 69.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29184-29191 64 0.13% 69.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29440-29447 64 0.13% 69.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::29696-29703 356 0.73% 70.09% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30208-30215 65 0.13% 70.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30464-30471 64 0.13% 70.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30720-30727 228 0.47% 70.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::30976-30983 64 0.13% 70.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31232-31239 64 0.13% 71.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31488-31495 189 0.39% 71.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::31744-31751 321 0.66% 72.13% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32000-32007 63 0.13% 72.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32128-32135 1 0.00% 72.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32512-32519 64 0.13% 72.39% # Bytes accessed per row activation
system.physmem.bytesPerActivate::32768-32775 673 1.38% 73.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33024-33031 64 0.13% 73.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33408-33415 1 0.00% 73.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33536-33543 64 0.13% 74.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::33792-33799 321 0.66% 74.70% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34048-34055 189 0.39% 75.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34304-34311 64 0.13% 75.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34560-34567 65 0.13% 75.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::34816-34823 229 0.47% 75.82% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35072-35079 64 0.13% 75.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35328-35335 65 0.13% 76.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::35840-35847 356 0.73% 76.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36096-36103 64 0.13% 76.95% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36352-36359 64 0.13% 77.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36608-36615 65 0.13% 77.21% # Bytes accessed per row activation
system.physmem.bytesPerActivate::36864-36871 329 0.68% 77.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37120-37127 65 0.13% 78.02% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37376-37383 64 0.13% 78.15% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37632-37639 61 0.13% 78.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::37888-37895 276 0.57% 78.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38144-38151 68 0.14% 78.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38400-38407 127 0.26% 79.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38528-38535 1 0.00% 79.24% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38656-38663 137 0.28% 79.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::38912-38919 322 0.66% 80.19% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39168-39175 94 0.19% 80.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39424-39431 69 0.14% 80.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39680-39687 57 0.12% 80.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39808-39815 1 0.00% 80.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::39936-39943 264 0.54% 81.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40128-40135 1 0.00% 81.18% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40192-40199 64 0.13% 81.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40448-40455 65 0.13% 81.45% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40704-40711 42 0.09% 81.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::40960-40967 513 1.05% 82.59% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41216-41223 43 0.09% 82.67% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41472-41479 64 0.13% 82.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41728-41735 65 0.13% 82.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::41984-41991 266 0.55% 83.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42240-42247 57 0.12% 83.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42496-42503 68 0.14% 83.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42688-42695 1 0.00% 83.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::42752-42759 93 0.19% 83.93% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43008-43015 323 0.66% 84.60% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43264-43271 137 0.28% 84.88% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43520-43527 128 0.26% 85.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::43776-43783 69 0.14% 85.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44032-44039 274 0.56% 85.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44288-44295 61 0.13% 85.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44544-44551 64 0.13% 86.10% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44800-44807 64 0.13% 86.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::44928-44935 1 0.00% 86.23% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45056-45063 327 0.67% 86.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45184-45191 1 0.00% 86.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45248-45255 1 0.00% 86.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45312-45319 64 0.13% 87.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45568-45575 64 0.13% 87.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45632-45639 1 0.00% 87.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::45824-45831 64 0.13% 87.31% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46080-46087 356 0.73% 88.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46528-46535 1 0.00% 88.04% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46592-46599 63 0.13% 88.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::46848-46855 64 0.13% 88.30% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47104-47111 228 0.47% 88.77% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47360-47367 64 0.13% 88.90% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47616-47623 65 0.13% 89.03% # Bytes accessed per row activation
system.physmem.bytesPerActivate::47872-47879 190 0.39% 89.42% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48128-48135 322 0.66% 90.08% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48384-48391 67 0.14% 90.22% # Bytes accessed per row activation
system.physmem.bytesPerActivate::48896-48903 64 0.13% 90.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49024-49031 1 0.00% 90.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49088-49095 1 0.00% 90.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::49152-49159 4701 9.65% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 48736 # Bytes accessed per row activation
system.physmem.totQLat 326317088000 # Total ticks spent queuing
system.physmem.totMemAccLat 407972525500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 67393855000 # Total ticks spent in databus transfers
system.physmem.totBankLat 14261582500 # Total ticks spent accessing banks
system.physmem.avgQLat 24209.71 # Average queueing delay per DRAM burst
system.physmem.avgBankLat 1058.08 # Average bank access latency per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 30267.78 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 358.88 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 1.19 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 45.69 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 1.17 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 2.81 # Data bus utilization in percentage
system.physmem.busUtilRead 2.80 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.01 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 0.17 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.37 # Average write queue length when enqueuing
system.physmem.readRowHits 13435330 # Number of row buffer hits during reads
system.physmem.writeRowHits 39380 # Number of row buffer hits during writes
system.physmem.readRowHitRate 99.68 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 88.14 # Row buffer hit rate for writes
system.physmem.avgGap 172539.89 # Average gap between requests
system.physmem.pageHitRate 99.64 # Row buffer hit rate, read and write combined
system.physmem.prechargeAllPercent 0.87 # Percentage of time for which DRAM has all the banks in precharge state
system.realview.nvmem.bytes_read::cpu0.inst 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_read::total 20 # Number of bytes read from this memory
system.realview.nvmem.bytes_inst_read::cpu0.inst 20 # Number of instructions bytes read from this memory
system.realview.nvmem.bytes_inst_read::total 20 # Number of instructions bytes read from this memory
system.realview.nvmem.num_reads::cpu0.inst 5 # Number of read requests responded to by this memory
system.realview.nvmem.num_reads::total 5 # Number of read requests responded to by this memory
system.realview.nvmem.bw_read::cpu0.inst 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_read::total 8 # Total read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::cpu0.inst 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_inst_read::total 8 # Instruction read bandwidth from this memory (bytes/s)
system.realview.nvmem.bw_total::cpu0.inst 8 # Total bandwidth to/from this memory (bytes/s)
system.realview.nvmem.bw_total::total 8 # Total bandwidth to/from this memory (bytes/s)
system.membus.throughput 55671828 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 13814146 # Transaction distribution
system.membus.trans_dist::ReadResp 13814146 # Transaction distribution
system.membus.trans_dist::WriteReq 432166 # Transaction distribution
system.membus.trans_dist::WriteResp 432166 # Transaction distribution
system.membus.trans_dist::Writeback 16999 # Transaction distribution
system.membus.trans_dist::UpgradeReq 2355 # Transaction distribution
system.membus.trans_dist::UpgradeResp 2355 # Transaction distribution
system.membus.trans_dist::ReadExReq 27802 # Transaction distribution
system.membus.trans_dist::ReadExResp 27802 # Transaction distribution
system.membus.pkt_count_system.l2c.mem_side::system.bridge.slave 731808 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.realview.gic.pio 214 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 951163 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.l2c.mem_side::total 1683185 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::system.physmem.port 26886752 # Packet count per connected master and slave (bytes)
system.membus.pkt_count_system.iocache.mem_side::total 26886752 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 28569937 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.bridge.slave 735681 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.realview.gic.pio 428 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::system.physmem.port 5070064 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.l2c.mem_side::total 5806173 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::system.physmem.port 107547008 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size_system.iocache.mem_side::total 107547008 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 113353181 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 133816795 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 416936000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer2.occupancy 202000 # Layer occupancy (ticks)
system.membus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.membus.reqLayer6.occupancy 14607946000 # Layer occupancy (ticks)
system.membus.reqLayer6.utilization 0.6 # Layer utilization (%)
system.membus.respLayer1.occupancy 1594364889 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
system.membus.respLayer2.occupancy 30360976750 # Layer occupancy (ticks)
system.membus.respLayer2.utilization 1.3 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.l2c.tags.replacements 63237 # number of replacements
system.l2c.tags.tagsinuse 50379.569066 # Cycle average of tags in use
system.l2c.tags.total_refs 1749643 # Total number of references to valid blocks.
system.l2c.tags.sampled_refs 128631 # Sample count of references to valid blocks.
system.l2c.tags.avg_refs 13.602032 # Average number of references to valid blocks.
system.l2c.tags.warmup_cycle 2375594870500 # Cycle when the warmup percentage was hit.
system.l2c.tags.occ_blocks::writebacks 36839.610574 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.dtb.walker 0.000018 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.itb.walker 0.000124 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.inst 5231.934240 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu0.data 3832.971184 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.dtb.walker 0.993316 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.inst 504.116293 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu1.data 687.425497 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.dtb.walker 7.900489 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.inst 1683.581513 # Average occupied blocks per requestor
system.l2c.tags.occ_blocks::cpu2.data 1591.035818 # Average occupied blocks per requestor
system.l2c.tags.occ_percent::writebacks 0.562128 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.dtb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.itb.walker 0.000000 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.inst 0.079833 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu0.data 0.058486 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.dtb.walker 0.000015 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.inst 0.007692 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu1.data 0.010489 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.dtb.walker 0.000121 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.inst 0.025689 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::cpu2.data 0.024277 # Average percentage of cache occupancy
system.l2c.tags.occ_percent::total 0.768731 # Average percentage of cache occupancy
system.l2c.tags.occ_task_id_blocks::1023 2 # Occupied blocks per task id
system.l2c.tags.occ_task_id_blocks::1024 65392 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1023::4 2 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::1 340 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::2 2635 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::3 6494 # Occupied blocks per task id
system.l2c.tags.age_task_id_blocks_1024::4 55883 # Occupied blocks per task id
system.l2c.tags.occ_task_id_percent::1023 0.000031 # Percentage of cache occupancy per task id
system.l2c.tags.occ_task_id_percent::1024 0.997803 # Percentage of cache occupancy per task id
system.l2c.tags.tag_accesses 17683980 # Number of tag accesses
system.l2c.tags.data_accesses 17683980 # Number of data accesses
system.l2c.ReadReq_hits::cpu0.dtb.walker 8701 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.itb.walker 3143 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.inst 467937 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu0.data 177040 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.dtb.walker 2608 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.itb.walker 1169 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.inst 128901 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu1.data 64374 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.dtb.walker 18792 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.itb.walker 4308 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.inst 282422 # number of ReadReq hits
system.l2c.ReadReq_hits::cpu2.data 131846 # number of ReadReq hits
system.l2c.ReadReq_hits::total 1291241 # number of ReadReq hits
system.l2c.Writeback_hits::writebacks 597674 # number of Writeback hits
system.l2c.Writeback_hits::total 597674 # number of Writeback hits
system.l2c.UpgradeReq_hits::cpu0.data 14 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu1.data 4 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::cpu2.data 11 # number of UpgradeReq hits
system.l2c.UpgradeReq_hits::total 29 # number of UpgradeReq hits
system.l2c.SCUpgradeReq_hits::cpu2.data 2 # number of SCUpgradeReq hits
system.l2c.SCUpgradeReq_hits::total 2 # number of SCUpgradeReq hits
system.l2c.ReadExReq_hits::cpu0.data 62009 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu1.data 18402 # number of ReadExReq hits
system.l2c.ReadExReq_hits::cpu2.data 33187 # number of ReadExReq hits
system.l2c.ReadExReq_hits::total 113598 # number of ReadExReq hits
system.l2c.demand_hits::cpu0.dtb.walker 8701 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.itb.walker 3143 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.inst 467937 # number of demand (read+write) hits
system.l2c.demand_hits::cpu0.data 239049 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.dtb.walker 2608 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.itb.walker 1169 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.inst 128901 # number of demand (read+write) hits
system.l2c.demand_hits::cpu1.data 82776 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.dtb.walker 18792 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.itb.walker 4308 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.inst 282422 # number of demand (read+write) hits
system.l2c.demand_hits::cpu2.data 165033 # number of demand (read+write) hits
system.l2c.demand_hits::total 1404839 # number of demand (read+write) hits
system.l2c.overall_hits::cpu0.dtb.walker 8701 # number of overall hits
system.l2c.overall_hits::cpu0.itb.walker 3143 # number of overall hits
system.l2c.overall_hits::cpu0.inst 467937 # number of overall hits
system.l2c.overall_hits::cpu0.data 239049 # number of overall hits
system.l2c.overall_hits::cpu1.dtb.walker 2608 # number of overall hits
system.l2c.overall_hits::cpu1.itb.walker 1169 # number of overall hits
system.l2c.overall_hits::cpu1.inst 128901 # number of overall hits
system.l2c.overall_hits::cpu1.data 82776 # number of overall hits
system.l2c.overall_hits::cpu2.dtb.walker 18792 # number of overall hits
system.l2c.overall_hits::cpu2.itb.walker 4308 # number of overall hits
system.l2c.overall_hits::cpu2.inst 282422 # number of overall hits
system.l2c.overall_hits::cpu2.data 165033 # number of overall hits
system.l2c.overall_hits::total 1404839 # number of overall hits
system.l2c.ReadReq_misses::cpu0.dtb.walker 1 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.itb.walker 2 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.inst 7593 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu0.data 6469 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.dtb.walker 1 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.inst 1010 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu1.data 1115 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.dtb.walker 10 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.inst 2911 # number of ReadReq misses
system.l2c.ReadReq_misses::cpu2.data 2551 # number of ReadReq misses
system.l2c.ReadReq_misses::total 21663 # number of ReadReq misses
system.l2c.UpgradeReq_misses::cpu0.data 1419 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu1.data 466 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::cpu2.data 1020 # number of UpgradeReq misses
system.l2c.UpgradeReq_misses::total 2905 # number of UpgradeReq misses
system.l2c.ReadExReq_misses::cpu0.data 104688 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu1.data 9751 # number of ReadExReq misses
system.l2c.ReadExReq_misses::cpu2.data 18920 # number of ReadExReq misses
system.l2c.ReadExReq_misses::total 133359 # number of ReadExReq misses
system.l2c.demand_misses::cpu0.dtb.walker 1 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.itb.walker 2 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.inst 7593 # number of demand (read+write) misses
system.l2c.demand_misses::cpu0.data 111157 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.dtb.walker 1 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.inst 1010 # number of demand (read+write) misses
system.l2c.demand_misses::cpu1.data 10866 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.dtb.walker 10 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.inst 2911 # number of demand (read+write) misses
system.l2c.demand_misses::cpu2.data 21471 # number of demand (read+write) misses
system.l2c.demand_misses::total 155022 # number of demand (read+write) misses
system.l2c.overall_misses::cpu0.dtb.walker 1 # number of overall misses
system.l2c.overall_misses::cpu0.itb.walker 2 # number of overall misses
system.l2c.overall_misses::cpu0.inst 7593 # number of overall misses
system.l2c.overall_misses::cpu0.data 111157 # number of overall misses
system.l2c.overall_misses::cpu1.dtb.walker 1 # number of overall misses
system.l2c.overall_misses::cpu1.inst 1010 # number of overall misses
system.l2c.overall_misses::cpu1.data 10866 # number of overall misses
system.l2c.overall_misses::cpu2.dtb.walker 10 # number of overall misses
system.l2c.overall_misses::cpu2.inst 2911 # number of overall misses
system.l2c.overall_misses::cpu2.data 21471 # number of overall misses
system.l2c.overall_misses::total 155022 # number of overall misses
system.l2c.ReadReq_miss_latency::cpu1.dtb.walker 74500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.inst 72979250 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu1.data 86304000 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.dtb.walker 805500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.inst 221738500 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::cpu2.data 199604750 # number of ReadReq miss cycles
system.l2c.ReadReq_miss_latency::total 581506500 # number of ReadReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu1.data 93996 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::cpu2.data 139494 # number of UpgradeReq miss cycles
system.l2c.UpgradeReq_miss_latency::total 233490 # number of UpgradeReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu1.data 736617229 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::cpu2.data 1419662152 # number of ReadExReq miss cycles
system.l2c.ReadExReq_miss_latency::total 2156279381 # number of ReadExReq miss cycles
system.l2c.demand_miss_latency::cpu1.dtb.walker 74500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.inst 72979250 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu1.data 822921229 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.dtb.walker 805500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.inst 221738500 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::cpu2.data 1619266902 # number of demand (read+write) miss cycles
system.l2c.demand_miss_latency::total 2737785881 # number of demand (read+write) miss cycles
system.l2c.overall_miss_latency::cpu1.dtb.walker 74500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.inst 72979250 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu1.data 822921229 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.dtb.walker 805500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.inst 221738500 # number of overall miss cycles
system.l2c.overall_miss_latency::cpu2.data 1619266902 # number of overall miss cycles
system.l2c.overall_miss_latency::total 2737785881 # number of overall miss cycles
system.l2c.ReadReq_accesses::cpu0.dtb.walker 8702 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.itb.walker 3145 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.inst 475530 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu0.data 183509 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.dtb.walker 2609 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.itb.walker 1169 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.inst 129911 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu1.data 65489 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.dtb.walker 18802 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.itb.walker 4308 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.inst 285333 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::cpu2.data 134397 # number of ReadReq accesses(hits+misses)
system.l2c.ReadReq_accesses::total 1312904 # number of ReadReq accesses(hits+misses)
system.l2c.Writeback_accesses::writebacks 597674 # number of Writeback accesses(hits+misses)
system.l2c.Writeback_accesses::total 597674 # number of Writeback accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu0.data 1433 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu1.data 470 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::cpu2.data 1031 # number of UpgradeReq accesses(hits+misses)
system.l2c.UpgradeReq_accesses::total 2934 # number of UpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::cpu2.data 2 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.SCUpgradeReq_accesses::total 2 # number of SCUpgradeReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu0.data 166697 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu1.data 28153 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::cpu2.data 52107 # number of ReadExReq accesses(hits+misses)
system.l2c.ReadExReq_accesses::total 246957 # number of ReadExReq accesses(hits+misses)
system.l2c.demand_accesses::cpu0.dtb.walker 8702 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.itb.walker 3145 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.inst 475530 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu0.data 350206 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.dtb.walker 2609 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.itb.walker 1169 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.inst 129911 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu1.data 93642 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.dtb.walker 18802 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.itb.walker 4308 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.inst 285333 # number of demand (read+write) accesses
system.l2c.demand_accesses::cpu2.data 186504 # number of demand (read+write) accesses
system.l2c.demand_accesses::total 1559861 # number of demand (read+write) accesses
system.l2c.overall_accesses::cpu0.dtb.walker 8702 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.itb.walker 3145 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.inst 475530 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu0.data 350206 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.dtb.walker 2609 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.itb.walker 1169 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.inst 129911 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu1.data 93642 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.dtb.walker 18802 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.itb.walker 4308 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.inst 285333 # number of overall (read+write) accesses
system.l2c.overall_accesses::cpu2.data 186504 # number of overall (read+write) accesses
system.l2c.overall_accesses::total 1559861 # number of overall (read+write) accesses
system.l2c.ReadReq_miss_rate::cpu0.dtb.walker 0.000115 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.itb.walker 0.000636 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.inst 0.015967 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu0.data 0.035252 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.dtb.walker 0.000383 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.inst 0.007775 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu1.data 0.017026 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.dtb.walker 0.000532 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.inst 0.010202 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::cpu2.data 0.018981 # miss rate for ReadReq accesses
system.l2c.ReadReq_miss_rate::total 0.016500 # miss rate for ReadReq accesses
system.l2c.UpgradeReq_miss_rate::cpu0.data 0.990230 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu1.data 0.991489 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::cpu2.data 0.989331 # miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_miss_rate::total 0.990116 # miss rate for UpgradeReq accesses
system.l2c.ReadExReq_miss_rate::cpu0.data 0.628014 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu1.data 0.346357 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::cpu2.data 0.363099 # miss rate for ReadExReq accesses
system.l2c.ReadExReq_miss_rate::total 0.540009 # miss rate for ReadExReq accesses
system.l2c.demand_miss_rate::cpu0.dtb.walker 0.000115 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.itb.walker 0.000636 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.inst 0.015967 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu0.data 0.317405 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.dtb.walker 0.000383 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.inst 0.007775 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu1.data 0.116038 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.dtb.walker 0.000532 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.inst 0.010202 # miss rate for demand accesses
system.l2c.demand_miss_rate::cpu2.data 0.115124 # miss rate for demand accesses
system.l2c.demand_miss_rate::total 0.099382 # miss rate for demand accesses
system.l2c.overall_miss_rate::cpu0.dtb.walker 0.000115 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.itb.walker 0.000636 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.inst 0.015967 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu0.data 0.317405 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.dtb.walker 0.000383 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.inst 0.007775 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu1.data 0.116038 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.dtb.walker 0.000532 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.inst 0.010202 # miss rate for overall accesses
system.l2c.overall_miss_rate::cpu2.data 0.115124 # miss rate for overall accesses
system.l2c.overall_miss_rate::total 0.099382 # miss rate for overall accesses
system.l2c.ReadReq_avg_miss_latency::cpu1.dtb.walker 74500 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.inst 72256.683168 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu1.data 77402.690583 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.dtb.walker 80550 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.inst 76172.621092 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::cpu2.data 78245.687966 # average ReadReq miss latency
system.l2c.ReadReq_avg_miss_latency::total 26843.304251 # average ReadReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu1.data 201.708155 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::cpu2.data 136.758824 # average UpgradeReq miss latency
system.l2c.UpgradeReq_avg_miss_latency::total 80.375215 # average UpgradeReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu1.data 75542.737053 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::cpu2.data 75034.997463 # average ReadExReq miss latency
system.l2c.ReadExReq_avg_miss_latency::total 16168.982828 # average ReadExReq miss latency
system.l2c.demand_avg_miss_latency::cpu1.dtb.walker 74500 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.inst 72256.683168 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu1.data 75733.593687 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.dtb.walker 80550 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.inst 76172.621092 # average overall miss latency
system.l2c.demand_avg_miss_latency::cpu2.data 75416.464161 # average overall miss latency
system.l2c.demand_avg_miss_latency::total 17660.628046 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.dtb.walker 74500 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.inst 72256.683168 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu1.data 75733.593687 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.dtb.walker 80550 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.inst 76172.621092 # average overall miss latency
system.l2c.overall_avg_miss_latency::cpu2.data 75416.464161 # average overall miss latency
system.l2c.overall_avg_miss_latency::total 17660.628046 # average overall miss latency
system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked
system.l2c.blocked::no_targets 0 # number of cycles access was blocked
system.l2c.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.l2c.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.l2c.fast_writes 0 # number of fast writes performed
system.l2c.cache_copies 0 # number of cache copies performed
system.l2c.writebacks::writebacks 58494 # number of writebacks
system.l2c.writebacks::total 58494 # number of writebacks
system.l2c.ReadReq_mshr_hits::cpu2.inst 1 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::cpu2.data 12 # number of ReadReq MSHR hits
system.l2c.ReadReq_mshr_hits::total 13 # number of ReadReq MSHR hits
system.l2c.demand_mshr_hits::cpu2.inst 1 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::cpu2.data 12 # number of demand (read+write) MSHR hits
system.l2c.demand_mshr_hits::total 13 # number of demand (read+write) MSHR hits
system.l2c.overall_mshr_hits::cpu2.inst 1 # number of overall MSHR hits
system.l2c.overall_mshr_hits::cpu2.data 12 # number of overall MSHR hits
system.l2c.overall_mshr_hits::total 13 # number of overall MSHR hits
system.l2c.ReadReq_mshr_misses::cpu1.dtb.walker 1 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.inst 1010 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu1.data 1115 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.dtb.walker 10 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.inst 2910 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::cpu2.data 2539 # number of ReadReq MSHR misses
system.l2c.ReadReq_mshr_misses::total 7585 # number of ReadReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu1.data 466 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::cpu2.data 1020 # number of UpgradeReq MSHR misses
system.l2c.UpgradeReq_mshr_misses::total 1486 # number of UpgradeReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu1.data 9751 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::cpu2.data 18920 # number of ReadExReq MSHR misses
system.l2c.ReadExReq_mshr_misses::total 28671 # number of ReadExReq MSHR misses
system.l2c.demand_mshr_misses::cpu1.dtb.walker 1 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.inst 1010 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu1.data 10866 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.dtb.walker 10 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.inst 2910 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::cpu2.data 21459 # number of demand (read+write) MSHR misses
system.l2c.demand_mshr_misses::total 36256 # number of demand (read+write) MSHR misses
system.l2c.overall_mshr_misses::cpu1.dtb.walker 1 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.inst 1010 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu1.data 10866 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.dtb.walker 10 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.inst 2910 # number of overall MSHR misses
system.l2c.overall_mshr_misses::cpu2.data 21459 # number of overall MSHR misses
system.l2c.overall_mshr_misses::total 36256 # number of overall MSHR misses
system.l2c.ReadReq_mshr_miss_latency::cpu1.dtb.walker 62500 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.inst 60167250 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu1.data 72428000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.dtb.walker 680000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.inst 185219250 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::cpu2.data 167287000 # number of ReadReq MSHR miss cycles
system.l2c.ReadReq_mshr_miss_latency::total 485844000 # number of ReadReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu1.data 4660466 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::cpu2.data 10201020 # number of UpgradeReq MSHR miss cycles
system.l2c.UpgradeReq_mshr_miss_latency::total 14861486 # number of UpgradeReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 613187771 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1183833848 # number of ReadExReq MSHR miss cycles
system.l2c.ReadExReq_mshr_miss_latency::total 1797021619 # number of ReadExReq MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.dtb.walker 62500 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.inst 60167250 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu1.data 685615771 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.dtb.walker 680000 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.inst 185219250 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::cpu2.data 1351120848 # number of demand (read+write) MSHR miss cycles
system.l2c.demand_mshr_miss_latency::total 2282865619 # number of demand (read+write) MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.dtb.walker 62500 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.inst 60167250 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu1.data 685615771 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.dtb.walker 680000 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.inst 185219250 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::cpu2.data 1351120848 # number of overall MSHR miss cycles
system.l2c.overall_mshr_miss_latency::total 2282865619 # number of overall MSHR miss cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu1.data 25080786000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::cpu2.data 26172240000 # number of ReadReq MSHR uncacheable cycles
system.l2c.ReadReq_mshr_uncacheable_latency::total 51253026000 # number of ReadReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu1.data 932356006 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::cpu2.data 8515525000 # number of WriteReq MSHR uncacheable cycles
system.l2c.WriteReq_mshr_uncacheable_latency::total 9447881006 # number of WriteReq MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu1.data 26013142006 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::cpu2.data 34687765000 # number of overall MSHR uncacheable cycles
system.l2c.overall_mshr_uncacheable_latency::total 60700907006 # number of overall MSHR uncacheable cycles
system.l2c.ReadReq_mshr_miss_rate::cpu1.dtb.walker 0.000383 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.007775 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.017026 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.dtb.walker 0.000532 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.010199 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.018892 # mshr miss rate for ReadReq accesses
system.l2c.ReadReq_mshr_miss_rate::total 0.005777 # mshr miss rate for ReadReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 0.991489 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 0.989331 # mshr miss rate for UpgradeReq accesses
system.l2c.UpgradeReq_mshr_miss_rate::total 0.506476 # mshr miss rate for UpgradeReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 0.346357 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 0.363099 # mshr miss rate for ReadExReq accesses
system.l2c.ReadExReq_mshr_miss_rate::total 0.116097 # mshr miss rate for ReadExReq accesses
system.l2c.demand_mshr_miss_rate::cpu1.dtb.walker 0.000383 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007775 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu1.data 0.116038 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.dtb.walker 0.000532 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.inst 0.010199 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::cpu2.data 0.115059 # mshr miss rate for demand accesses
system.l2c.demand_mshr_miss_rate::total 0.023243 # mshr miss rate for demand accesses
system.l2c.overall_mshr_miss_rate::cpu1.dtb.walker 0.000383 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007775 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu1.data 0.116038 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.dtb.walker 0.000532 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.inst 0.010199 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::cpu2.data 0.115059 # mshr miss rate for overall accesses
system.l2c.overall_mshr_miss_rate::total 0.023243 # mshr miss rate for overall accesses
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 59571.534653 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 64957.847534 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.dtb.walker 68000 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 63649.226804 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 65886.963371 # average ReadReq mshr miss latency
system.l2c.ReadReq_avg_mshr_miss_latency::total 64053.263019 # average ReadReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10001 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 10001 # average UpgradeReq mshr miss latency
system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 62884.603733 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 62570.499366 # average ReadExReq mshr miss latency
system.l2c.ReadExReq_avg_mshr_miss_latency::total 62677.326183 # average ReadExReq mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 59571.534653 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu1.data 63097.346862 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.dtb.walker 68000 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 63649.226804 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::cpu2.data 62962.898924 # average overall mshr miss latency
system.l2c.demand_avg_mshr_miss_latency::total 62965.181460 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.dtb.walker 62500 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 59571.534653 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu1.data 63097.346862 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.dtb.walker 68000 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 63649.226804 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::cpu2.data 62962.898924 # average overall mshr miss latency
system.l2c.overall_avg_mshr_miss_latency::total 62965.181460 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
system.l2c.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.cf0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.cf0.dma_read_bytes 0 # Number of bytes transfered via DMA reads (not PRD).
system.cf0.dma_read_txs 0 # Number of DMA read transactions (not PRD).
system.cf0.dma_write_full_pages 0 # Number of full page size DMA writes.
system.cf0.dma_write_bytes 0 # Number of bytes transfered via DMA writes.
system.cf0.dma_write_txs 0 # Number of DMA write transactions.
system.toL2Bus.throughput 58818769 # Throughput (bytes/s)
system.toL2Bus.trans_dist::ReadReq 1020134 # Transaction distribution
system.toL2Bus.trans_dist::ReadResp 1020133 # Transaction distribution
system.toL2Bus.trans_dist::WriteReq 432166 # Transaction distribution
system.toL2Bus.trans_dist::WriteResp 432166 # Transaction distribution
system.toL2Bus.trans_dist::Writeback 265053 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeReq 1501 # Transaction distribution
system.toL2Bus.trans_dist::SCUpgradeReq 2 # Transaction distribution
system.toL2Bus.trans_dist::UpgradeResp 1503 # Transaction distribution
system.toL2Bus.trans_dist::ReadExReq 80260 # Transaction distribution
system.toL2Bus.trans_dist::ReadExResp 80260 # Transaction distribution
system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 831165 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 2419053 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.itb.walker.dma::system.l2c.cpu_side 15627 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 52402 # Packet count per connected master and slave (bytes)
system.toL2Bus.pkt_count::total 3318247 # Packet count per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 26575552 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 37346205 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.itb.walker.dma::system.l2c.cpu_side 21908 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size_system.cpu0.dtb.walker.dma::system.l2c.cpu_side 85644 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.tot_pkt_size::total 64029309 # Cumulative packet size per connected master and slave (bytes)
system.toL2Bus.data_through_bus 141280603 # Total data (bytes)
system.toL2Bus.snoop_data_through_bus 100404 # Total snoop data (bytes)
system.toL2Bus.reqLayer0.occupancy 2176001251 # Layer occupancy (ticks)
system.toL2Bus.reqLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.respLayer0.occupancy 1872526171 # Layer occupancy (ticks)
system.toL2Bus.respLayer0.utilization 0.1 # Layer utilization (%)
system.toL2Bus.respLayer1.occupancy 1845075146 # Layer occupancy (ticks)
system.toL2Bus.respLayer1.utilization 0.1 # Layer utilization (%)
system.toL2Bus.respLayer2.occupancy 10168460 # Layer occupancy (ticks)
system.toL2Bus.respLayer2.utilization 0.0 # Layer utilization (%)
system.toL2Bus.respLayer3.occupancy 31121231 # Layer occupancy (ticks)
system.toL2Bus.respLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.throughput 48762623 # Throughput (bytes/s)
system.iobus.trans_dist::ReadReq 13806510 # Transaction distribution
system.iobus.trans_dist::ReadResp 13806510 # Transaction distribution
system.iobus.trans_dist::WriteReq 2770 # Transaction distribution
system.iobus.trans_dist::WriteResp 2770 # Transaction distribution
system.iobus.pkt_count_system.bridge.master::system.realview.uart.pio 11390 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.realview_io.pio 3024 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer0.pio 18 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.timer1.pio 254 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.clcd.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi0.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.kmi1.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.cf_ctrl.pio 716834 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.dmac_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.uart3_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.smc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sp810_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.watchdog_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio0_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio1_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.gpio2_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.ssp_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.sci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.aaci_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.mmc_fake.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::system.realview.rtc.pio 16 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.bridge.master::total 731808 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::system.iocache.cpu_side 26886752 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count_system.realview.clcd.dma::total 26886752 # Packet count per connected master and slave (bytes)
system.iobus.pkt_count::total 27618560 # Packet count per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart.pio 15354 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.realview_io.pio 6048 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer0.pio 36 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.timer1.pio 508 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.clcd.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi0.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.kmi1.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.cf_ctrl.pio 713159 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.dmac_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.uart3_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.smc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sp810_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.watchdog_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio0_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio1_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.gpio2_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.ssp_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.sci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.aaci_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.mmc_fake.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::system.realview.rtc.pio 32 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.bridge.master::total 735681 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::system.iocache.cpu_side 107547008 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size_system.realview.clcd.dma::total 107547008 # Cumulative packet size per connected master and slave (bytes)
system.iobus.tot_pkt_size::total 108282689 # Cumulative packet size per connected master and slave (bytes)
system.iobus.data_through_bus 117209335 # Total data (bytes)
system.iobus.reqLayer0.occupancy 7953000 # Layer occupancy (ticks)
system.iobus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer1.occupancy 1512000 # Layer occupancy (ticks)
system.iobus.reqLayer1.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer2.occupancy 18000 # Layer occupancy (ticks)
system.iobus.reqLayer2.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer3.occupancy 127000 # Layer occupancy (ticks)
system.iobus.reqLayer3.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer4.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer4.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer5.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer5.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer6.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer6.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer7.occupancy 358920000 # Layer occupancy (ticks)
system.iobus.reqLayer7.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer9.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer9.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer10.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer10.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer11.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer11.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer12.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer12.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer13.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer13.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer14.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer14.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer15.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer15.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer16.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer16.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer17.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer17.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer18.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer18.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer19.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer19.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer20.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer20.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer21.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer21.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer22.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer22.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer23.occupancy 8000 # Layer occupancy (ticks)
system.iobus.reqLayer23.utilization 0.0 # Layer utilization (%)
system.iobus.reqLayer25.occupancy 13443376000 # Layer occupancy (ticks)
system.iobus.reqLayer25.utilization 0.6 # Layer utilization (%)
system.iobus.respLayer0.occupancy 729038000 # Layer occupancy (ticks)
system.iobus.respLayer0.utilization 0.0 # Layer utilization (%)
system.iobus.respLayer1.occupancy 36855449250 # Layer occupancy (ticks)
system.iobus.respLayer1.utilization 1.5 # Layer utilization (%)
system.cpu0.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.dtb.inst_hits 0 # ITB inst hits
system.cpu0.dtb.inst_misses 0 # ITB inst misses
system.cpu0.dtb.read_hits 7998897 # DTB read hits
system.cpu0.dtb.read_misses 6203 # DTB read misses
system.cpu0.dtb.write_hits 6598042 # DTB write hits
system.cpu0.dtb.write_misses 1992 # DTB write misses
system.cpu0.dtb.flush_tlb 556 # Number of times complete TLB was flushed
system.cpu0.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.dtb.flush_tlb_mva_asid 678 # Number of times TLB was flushed by MVA & ASID
system.cpu0.dtb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
system.cpu0.dtb.flush_entries 5672 # Number of entries that have been flushed from TLB
system.cpu0.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.dtb.prefetch_faults 123 # Number of TLB faults due to prefetch
system.cpu0.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.dtb.perms_faults 209 # Number of TLB faults due to permissions restrictions
system.cpu0.dtb.read_accesses 8005100 # DTB read accesses
system.cpu0.dtb.write_accesses 6600034 # DTB write accesses
system.cpu0.dtb.inst_accesses 0 # ITB inst accesses
system.cpu0.dtb.hits 14596939 # DTB hits
system.cpu0.dtb.misses 8195 # DTB misses
system.cpu0.dtb.accesses 14605134 # DTB accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu0.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu0.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu0.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu0.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu0.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu0.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu0.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu0.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu0.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu0.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu0.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu0.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu0.itb.inst_hits 32342389 # ITB inst hits
system.cpu0.itb.inst_misses 3452 # ITB inst misses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.write_hits 0 # DTB write hits
system.cpu0.itb.write_misses 0 # DTB write misses
system.cpu0.itb.flush_tlb 556 # Number of times complete TLB was flushed
system.cpu0.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu0.itb.flush_tlb_mva_asid 678 # Number of times TLB was flushed by MVA & ASID
system.cpu0.itb.flush_tlb_asid 30 # Number of times TLB was flushed by ASID
system.cpu0.itb.flush_entries 2628 # Number of entries that have been flushed from TLB
system.cpu0.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu0.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu0.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu0.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu0.itb.read_accesses 0 # DTB read accesses
system.cpu0.itb.write_accesses 0 # DTB write accesses
system.cpu0.itb.inst_accesses 32345841 # ITB inst accesses
system.cpu0.itb.hits 32342389 # DTB hits
system.cpu0.itb.misses 3452 # DTB misses
system.cpu0.itb.accesses 32345841 # DTB accesses
system.cpu0.numCycles 113704712 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu0.committedInsts 31867189 # Number of instructions committed
system.cpu0.committedOps 42038889 # Number of ops (including micro ops) committed
system.cpu0.num_int_alu_accesses 37421309 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 4937 # Number of float alu accesses
system.cpu0.num_func_calls 1198994 # number of times a function call or return occured
system.cpu0.num_conditional_control_insts 4247035 # number of instructions that are conditional controls
system.cpu0.num_int_insts 37421309 # number of integer instructions
system.cpu0.num_fp_insts 4937 # number of float instructions
system.cpu0.num_int_register_reads 193973220 # number of times the integer registers were read
system.cpu0.num_int_register_writes 39529492 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 3572 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 1366 # number of times the floating registers were written
system.cpu0.num_mem_refs 15264742 # number of memory refs
system.cpu0.num_load_insts 8367651 # Number of load instructions
system.cpu0.num_store_insts 6897091 # Number of store instructions
system.cpu0.num_idle_cycles 111017320.581957 # Number of idle cycles
system.cpu0.num_busy_cycles 2687391.418043 # Number of busy cycles
system.cpu0.not_idle_fraction 0.023635 # Percentage of non-idle cycles
system.cpu0.idle_fraction 0.976365 # Percentage of idle cycles
system.cpu0.Branches 5615714 # Number of branches fetched
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 82892 # number of quiesce instructions executed
system.cpu0.icache.tags.replacements 891676 # number of replacements
system.cpu0.icache.tags.tagsinuse 511.602493 # Cycle average of tags in use
system.cpu0.icache.tags.total_refs 43661110 # Total number of references to valid blocks.
system.cpu0.icache.tags.sampled_refs 892188 # Sample count of references to valid blocks.
system.cpu0.icache.tags.avg_refs 48.937119 # Average number of references to valid blocks.
system.cpu0.icache.tags.warmup_cycle 8187850250 # Cycle when the warmup percentage was hit.
system.cpu0.icache.tags.occ_blocks::cpu0.inst 495.418624 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu1.inst 7.559512 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_blocks::cpu2.inst 8.624357 # Average occupied blocks per requestor
system.cpu0.icache.tags.occ_percent::cpu0.inst 0.967615 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu1.inst 0.014765 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::cpu2.inst 0.016844 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_percent::total 0.999224 # Average percentage of cache occupancy
system.cpu0.icache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::1 217 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::2 160 # Occupied blocks per task id
system.cpu0.icache.tags.age_task_id_blocks_1024::3 3 # Occupied blocks per task id
system.cpu0.icache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.icache.tags.tag_accesses 45469557 # Number of tag accesses
system.cpu0.icache.tags.data_accesses 45469557 # Number of data accesses
system.cpu0.icache.ReadReq_hits::cpu0.inst 31868764 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu1.inst 8050810 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::cpu2.inst 3741536 # number of ReadReq hits
system.cpu0.icache.ReadReq_hits::total 43661110 # number of ReadReq hits
system.cpu0.icache.demand_hits::cpu0.inst 31868764 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu1.inst 8050810 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::cpu2.inst 3741536 # number of demand (read+write) hits
system.cpu0.icache.demand_hits::total 43661110 # number of demand (read+write) hits
system.cpu0.icache.overall_hits::cpu0.inst 31868764 # number of overall hits
system.cpu0.icache.overall_hits::cpu1.inst 8050810 # number of overall hits
system.cpu0.icache.overall_hits::cpu2.inst 3741536 # number of overall hits
system.cpu0.icache.overall_hits::total 43661110 # number of overall hits
system.cpu0.icache.ReadReq_misses::cpu0.inst 476273 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu1.inst 130180 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::cpu2.inst 309800 # number of ReadReq misses
system.cpu0.icache.ReadReq_misses::total 916253 # number of ReadReq misses
system.cpu0.icache.demand_misses::cpu0.inst 476273 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu1.inst 130180 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::cpu2.inst 309800 # number of demand (read+write) misses
system.cpu0.icache.demand_misses::total 916253 # number of demand (read+write) misses
system.cpu0.icache.overall_misses::cpu0.inst 476273 # number of overall misses
system.cpu0.icache.overall_misses::cpu1.inst 130180 # number of overall misses
system.cpu0.icache.overall_misses::cpu2.inst 309800 # number of overall misses
system.cpu0.icache.overall_misses::total 916253 # number of overall misses
system.cpu0.icache.ReadReq_miss_latency::cpu1.inst 1759106250 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::cpu2.inst 4179473576 # number of ReadReq miss cycles
system.cpu0.icache.ReadReq_miss_latency::total 5938579826 # number of ReadReq miss cycles
system.cpu0.icache.demand_miss_latency::cpu1.inst 1759106250 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::cpu2.inst 4179473576 # number of demand (read+write) miss cycles
system.cpu0.icache.demand_miss_latency::total 5938579826 # number of demand (read+write) miss cycles
system.cpu0.icache.overall_miss_latency::cpu1.inst 1759106250 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::cpu2.inst 4179473576 # number of overall miss cycles
system.cpu0.icache.overall_miss_latency::total 5938579826 # number of overall miss cycles
system.cpu0.icache.ReadReq_accesses::cpu0.inst 32345037 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu1.inst 8180990 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::cpu2.inst 4051336 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.ReadReq_accesses::total 44577363 # number of ReadReq accesses(hits+misses)
system.cpu0.icache.demand_accesses::cpu0.inst 32345037 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu1.inst 8180990 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::cpu2.inst 4051336 # number of demand (read+write) accesses
system.cpu0.icache.demand_accesses::total 44577363 # number of demand (read+write) accesses
system.cpu0.icache.overall_accesses::cpu0.inst 32345037 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu1.inst 8180990 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::cpu2.inst 4051336 # number of overall (read+write) accesses
system.cpu0.icache.overall_accesses::total 44577363 # number of overall (read+write) accesses
system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.014725 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu1.inst 0.015912 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::cpu2.inst 0.076469 # miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_miss_rate::total 0.020554 # miss rate for ReadReq accesses
system.cpu0.icache.demand_miss_rate::cpu0.inst 0.014725 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu1.inst 0.015912 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::cpu2.inst 0.076469 # miss rate for demand accesses
system.cpu0.icache.demand_miss_rate::total 0.020554 # miss rate for demand accesses
system.cpu0.icache.overall_miss_rate::cpu0.inst 0.014725 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu1.inst 0.015912 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::cpu2.inst 0.076469 # miss rate for overall accesses
system.cpu0.icache.overall_miss_rate::total 0.020554 # miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_miss_latency::cpu1.inst 13512.876402 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::cpu2.inst 13490.876617 # average ReadReq miss latency
system.cpu0.icache.ReadReq_avg_miss_latency::total 6481.375587 # average ReadReq miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu1.inst 13512.876402 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::cpu2.inst 13490.876617 # average overall miss latency
system.cpu0.icache.demand_avg_miss_latency::total 6481.375587 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu1.inst 13512.876402 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::cpu2.inst 13490.876617 # average overall miss latency
system.cpu0.icache.overall_avg_miss_latency::total 6481.375587 # average overall miss latency
system.cpu0.icache.blocked_cycles::no_mshrs 4072 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.blocked::no_mshrs 221 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu0.icache.avg_blocked_cycles::no_mshrs 18.425339 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
system.cpu0.icache.ReadReq_mshr_hits::cpu2.inst 24058 # number of ReadReq MSHR hits
system.cpu0.icache.ReadReq_mshr_hits::total 24058 # number of ReadReq MSHR hits
system.cpu0.icache.demand_mshr_hits::cpu2.inst 24058 # number of demand (read+write) MSHR hits
system.cpu0.icache.demand_mshr_hits::total 24058 # number of demand (read+write) MSHR hits
system.cpu0.icache.overall_mshr_hits::cpu2.inst 24058 # number of overall MSHR hits
system.cpu0.icache.overall_mshr_hits::total 24058 # number of overall MSHR hits
system.cpu0.icache.ReadReq_mshr_misses::cpu1.inst 130180 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::cpu2.inst 285742 # number of ReadReq MSHR misses
system.cpu0.icache.ReadReq_mshr_misses::total 415922 # number of ReadReq MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu1.inst 130180 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::cpu2.inst 285742 # number of demand (read+write) MSHR misses
system.cpu0.icache.demand_mshr_misses::total 415922 # number of demand (read+write) MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu1.inst 130180 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::cpu2.inst 285742 # number of overall MSHR misses
system.cpu0.icache.overall_mshr_misses::total 415922 # number of overall MSHR misses
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu1.inst 1498352750 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::cpu2.inst 3400846060 # number of ReadReq MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_latency::total 4899198810 # number of ReadReq MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu1.inst 1498352750 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::cpu2.inst 3400846060 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.demand_mshr_miss_latency::total 4899198810 # number of demand (read+write) MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu1.inst 1498352750 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::cpu2.inst 3400846060 # number of overall MSHR miss cycles
system.cpu0.icache.overall_mshr_miss_latency::total 4899198810 # number of overall MSHR miss cycles
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.015912 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.070530 # mshr miss rate for ReadReq accesses
system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.009330 # mshr miss rate for ReadReq accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu1.inst 0.015912 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::cpu2.inst 0.070530 # mshr miss rate for demand accesses
system.cpu0.icache.demand_mshr_miss_rate::total 0.009330 # mshr miss rate for demand accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu1.inst 0.015912 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::cpu2.inst 0.070530 # mshr miss rate for overall accesses
system.cpu0.icache.overall_mshr_miss_rate::total 0.009330 # mshr miss rate for overall accesses
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11509.853664 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11901.806735 # average ReadReq mshr miss latency
system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 11779.128803 # average ReadReq mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu1.inst 11509.853664 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::cpu2.inst 11901.806735 # average overall mshr miss latency
system.cpu0.icache.demand_avg_mshr_miss_latency::total 11779.128803 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu1.inst 11509.853664 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::cpu2.inst 11901.806735 # average overall mshr miss latency
system.cpu0.icache.overall_avg_mshr_miss_latency::total 11779.128803 # average overall mshr miss latency
system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.dcache.tags.replacements 629840 # number of replacements
system.cpu0.dcache.tags.tagsinuse 511.997118 # Cycle average of tags in use
system.cpu0.dcache.tags.total_refs 23225212 # Total number of references to valid blocks.
system.cpu0.dcache.tags.sampled_refs 630352 # Sample count of references to valid blocks.
system.cpu0.dcache.tags.avg_refs 36.844830 # Average number of references to valid blocks.
system.cpu0.dcache.tags.warmup_cycle 21768000 # Cycle when the warmup percentage was hit.
system.cpu0.dcache.tags.occ_blocks::cpu0.data 497.071711 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu1.data 8.097941 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_blocks::cpu2.data 6.827465 # Average occupied blocks per requestor
system.cpu0.dcache.tags.occ_percent::cpu0.data 0.970843 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu1.data 0.015816 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::cpu2.data 0.013335 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_percent::total 0.999994 # Average percentage of cache occupancy
system.cpu0.dcache.tags.occ_task_id_blocks::1024 512 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::0 198 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::1 296 # Occupied blocks per task id
system.cpu0.dcache.tags.age_task_id_blocks_1024::2 18 # Occupied blocks per task id
system.cpu0.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu0.dcache.tags.tag_accesses 98826568 # Number of tag accesses
system.cpu0.dcache.tags.data_accesses 98826568 # Number of data accesses
system.cpu0.dcache.ReadReq_hits::cpu0.data 6868032 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu1.data 1817018 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::cpu2.data 4638626 # number of ReadReq hits
system.cpu0.dcache.ReadReq_hits::total 13323676 # number of ReadReq hits
system.cpu0.dcache.WriteReq_hits::cpu0.data 5966375 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu1.data 1312197 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::cpu2.data 2134420 # number of WriteReq hits
system.cpu0.dcache.WriteReq_hits::total 9412992 # number of WriteReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu0.data 131825 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu1.data 32972 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::cpu2.data 73365 # number of LoadLockedReq hits
system.cpu0.dcache.LoadLockedReq_hits::total 238162 # number of LoadLockedReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu0.data 138288 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu1.data 34722 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::cpu2.data 74382 # number of StoreCondReq hits
system.cpu0.dcache.StoreCondReq_hits::total 247392 # number of StoreCondReq hits
system.cpu0.dcache.demand_hits::cpu0.data 12834407 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu1.data 3129215 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::cpu2.data 6773046 # number of demand (read+write) hits
system.cpu0.dcache.demand_hits::total 22736668 # number of demand (read+write) hits
system.cpu0.dcache.overall_hits::cpu0.data 12834407 # number of overall hits
system.cpu0.dcache.overall_hits::cpu1.data 3129215 # number of overall hits
system.cpu0.dcache.overall_hits::cpu2.data 6773046 # number of overall hits
system.cpu0.dcache.overall_hits::total 22736668 # number of overall hits
system.cpu0.dcache.ReadReq_misses::cpu0.data 177045 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu1.data 63739 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::cpu2.data 270648 # number of ReadReq misses
system.cpu0.dcache.ReadReq_misses::total 511432 # number of ReadReq misses
system.cpu0.dcache.WriteReq_misses::cpu0.data 168130 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu1.data 28623 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::cpu2.data 606733 # number of WriteReq misses
system.cpu0.dcache.WriteReq_misses::total 803486 # number of WriteReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu0.data 6464 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu1.data 1750 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::cpu2.data 3698 # number of LoadLockedReq misses
system.cpu0.dcache.LoadLockedReq_misses::total 11912 # number of LoadLockedReq misses
system.cpu0.dcache.StoreCondReq_misses::cpu2.data 2 # number of StoreCondReq misses
system.cpu0.dcache.StoreCondReq_misses::total 2 # number of StoreCondReq misses
system.cpu0.dcache.demand_misses::cpu0.data 345175 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu1.data 92362 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::cpu2.data 877381 # number of demand (read+write) misses
system.cpu0.dcache.demand_misses::total 1314918 # number of demand (read+write) misses
system.cpu0.dcache.overall_misses::cpu0.data 345175 # number of overall misses
system.cpu0.dcache.overall_misses::cpu1.data 92362 # number of overall misses
system.cpu0.dcache.overall_misses::cpu2.data 877381 # number of overall misses
system.cpu0.dcache.overall_misses::total 1314918 # number of overall misses
system.cpu0.dcache.ReadReq_miss_latency::cpu1.data 908043250 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::cpu2.data 3905088066 # number of ReadReq miss cycles
system.cpu0.dcache.ReadReq_miss_latency::total 4813131316 # number of ReadReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu1.data 1020010237 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::cpu2.data 23150589506 # number of WriteReq miss cycles
system.cpu0.dcache.WriteReq_miss_latency::total 24170599743 # number of WriteReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu1.data 23020750 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::cpu2.data 49421249 # number of LoadLockedReq miss cycles
system.cpu0.dcache.LoadLockedReq_miss_latency::total 72441999 # number of LoadLockedReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::cpu2.data 26000 # number of StoreCondReq miss cycles
system.cpu0.dcache.StoreCondReq_miss_latency::total 26000 # number of StoreCondReq miss cycles
system.cpu0.dcache.demand_miss_latency::cpu1.data 1928053487 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::cpu2.data 27055677572 # number of demand (read+write) miss cycles
system.cpu0.dcache.demand_miss_latency::total 28983731059 # number of demand (read+write) miss cycles
system.cpu0.dcache.overall_miss_latency::cpu1.data 1928053487 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::cpu2.data 27055677572 # number of overall miss cycles
system.cpu0.dcache.overall_miss_latency::total 28983731059 # number of overall miss cycles
system.cpu0.dcache.ReadReq_accesses::cpu0.data 7045077 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu1.data 1880757 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::cpu2.data 4909274 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.ReadReq_accesses::total 13835108 # number of ReadReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu0.data 6134505 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu1.data 1340820 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::cpu2.data 2741153 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.WriteReq_accesses::total 10216478 # number of WriteReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu0.data 138289 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu1.data 34722 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::cpu2.data 77063 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.LoadLockedReq_accesses::total 250074 # number of LoadLockedReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu0.data 138288 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu1.data 34722 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::cpu2.data 74384 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.StoreCondReq_accesses::total 247394 # number of StoreCondReq accesses(hits+misses)
system.cpu0.dcache.demand_accesses::cpu0.data 13179582 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu1.data 3221577 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::cpu2.data 7650427 # number of demand (read+write) accesses
system.cpu0.dcache.demand_accesses::total 24051586 # number of demand (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu0.data 13179582 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu1.data 3221577 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::cpu2.data 7650427 # number of overall (read+write) accesses
system.cpu0.dcache.overall_accesses::total 24051586 # number of overall (read+write) accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.025130 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu1.data 0.033890 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::cpu2.data 0.055130 # miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_miss_rate::total 0.036966 # miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.027407 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu1.data 0.021347 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::cpu2.data 0.221342 # miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_miss_rate::total 0.078646 # miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu0.data 0.046743 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu1.data 0.050400 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::cpu2.data 0.047987 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_miss_rate::total 0.047634 # miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::cpu2.data 0.000027 # miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_miss_rate::total 0.000008 # miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_miss_rate::cpu0.data 0.026190 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu1.data 0.028670 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::cpu2.data 0.114684 # miss rate for demand accesses
system.cpu0.dcache.demand_miss_rate::total 0.054671 # miss rate for demand accesses
system.cpu0.dcache.overall_miss_rate::cpu0.data 0.026190 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu1.data 0.028670 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::cpu2.data 0.114684 # miss rate for overall accesses
system.cpu0.dcache.overall_miss_rate::total 0.054671 # miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu1.data 14246.273867 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::cpu2.data 14428.660348 # average ReadReq miss latency
system.cpu0.dcache.ReadReq_avg_miss_latency::total 9411.087527 # average ReadReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu1.data 35636.035251 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::cpu2.data 38156.140355 # average WriteReq miss latency
system.cpu0.dcache.WriteReq_avg_miss_latency::total 30082.166638 # average WriteReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu1.data 13154.714286 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::cpu2.data 13364.318280 # average LoadLockedReq miss latency
system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 6081.430406 # average LoadLockedReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::cpu2.data 13000 # average StoreCondReq miss latency
system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 13000 # average StoreCondReq miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu1.data 20874.964672 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::cpu2.data 30836.862859 # average overall miss latency
system.cpu0.dcache.demand_avg_miss_latency::total 22042.234618 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu1.data 20874.964672 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::cpu2.data 30836.862859 # average overall miss latency
system.cpu0.dcache.overall_avg_miss_latency::total 22042.234618 # average overall miss latency
system.cpu0.dcache.blocked_cycles::no_mshrs 7997 # number of cycles access was blocked
system.cpu0.dcache.blocked_cycles::no_targets 3099 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_mshrs 875 # number of cycles access was blocked
system.cpu0.dcache.blocked::no_targets 50 # number of cycles access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_mshrs 9.139429 # average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles::no_targets 61.980000 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
system.cpu0.dcache.cache_copies 0 # number of cache copies performed
system.cpu0.dcache.writebacks::writebacks 597674 # number of writebacks
system.cpu0.dcache.writebacks::total 597674 # number of writebacks
system.cpu0.dcache.ReadReq_mshr_hits::cpu2.data 139516 # number of ReadReq MSHR hits
system.cpu0.dcache.ReadReq_mshr_hits::total 139516 # number of ReadReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::cpu2.data 553631 # number of WriteReq MSHR hits
system.cpu0.dcache.WriteReq_mshr_hits::total 553631 # number of WriteReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu2.data 397 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.LoadLockedReq_mshr_hits::total 397 # number of LoadLockedReq MSHR hits
system.cpu0.dcache.demand_mshr_hits::cpu2.data 693147 # number of demand (read+write) MSHR hits
system.cpu0.dcache.demand_mshr_hits::total 693147 # number of demand (read+write) MSHR hits
system.cpu0.dcache.overall_mshr_hits::cpu2.data 693147 # number of overall MSHR hits
system.cpu0.dcache.overall_mshr_hits::total 693147 # number of overall MSHR hits
system.cpu0.dcache.ReadReq_mshr_misses::cpu1.data 63739 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::cpu2.data 131132 # number of ReadReq MSHR misses
system.cpu0.dcache.ReadReq_mshr_misses::total 194871 # number of ReadReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu1.data 28623 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::cpu2.data 53102 # number of WriteReq MSHR misses
system.cpu0.dcache.WriteReq_mshr_misses::total 81725 # number of WriteReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu1.data 1750 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu2.data 3301 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.LoadLockedReq_mshr_misses::total 5051 # number of LoadLockedReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::cpu2.data 2 # number of StoreCondReq MSHR misses
system.cpu0.dcache.StoreCondReq_mshr_misses::total 2 # number of StoreCondReq MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu1.data 92362 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::cpu2.data 184234 # number of demand (read+write) MSHR misses
system.cpu0.dcache.demand_mshr_misses::total 276596 # number of demand (read+write) MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu1.data 92362 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::cpu2.data 184234 # number of overall MSHR misses
system.cpu0.dcache.overall_mshr_misses::total 276596 # number of overall MSHR misses
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu1.data 780368750 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu2.data 1698635349 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_miss_latency::total 2479004099 # number of ReadReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu1.data 960165763 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu2.data 1859721243 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.WriteReq_mshr_miss_latency::total 2819887006 # number of WriteReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 19520250 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu2.data 38036501 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 57556751 # number of LoadLockedReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu2.data 22000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 22000 # number of StoreCondReq MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu1.data 1740534513 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::cpu2.data 3558356592 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.demand_mshr_miss_latency::total 5298891105 # number of demand (read+write) MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu1.data 1740534513 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::cpu2.data 3558356592 # number of overall MSHR miss cycles
system.cpu0.dcache.overall_mshr_miss_latency::total 5298891105 # number of overall MSHR miss cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 27401033000 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu2.data 28573458500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 55974491500 # number of ReadReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 1439106494 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu2.data 13338859363 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 14777965857 # number of WriteReq MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu1.data 28840139494 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu2.data 41912317863 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_latency::total 70752457357 # number of overall MSHR uncacheable cycles
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.033890 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.026711 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.014085 # mshr miss rate for ReadReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.021347 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.019372 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.007999 # mshr miss rate for WriteReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.050400 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu2.data 0.042835 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.020198 # mshr miss rate for LoadLockedReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu2.data 0.000027 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.000008 # mshr miss rate for StoreCondReq accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu1.data 0.028670 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::cpu2.data 0.024082 # mshr miss rate for demand accesses
system.cpu0.dcache.demand_mshr_miss_rate::total 0.011500 # mshr miss rate for demand accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu1.data 0.028670 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::cpu2.data 0.024082 # mshr miss rate for overall accesses
system.cpu0.dcache.overall_mshr_miss_rate::total 0.011500 # mshr miss rate for overall accesses
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12243.190982 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 12953.629541 # average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 12721.257134 # average ReadReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 33545.252524 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 35021.679843 # average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 34504.582515 # average WriteReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 11154.428571 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu2.data 11522.720691 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11395.119976 # average LoadLockedReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu2.data 11000 # average StoreCondReq mshr miss latency
system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 11000 # average StoreCondReq mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu1.data 18844.703590 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu2.data 19314.331730 # average overall mshr miss latency
system.cpu0.dcache.demand_avg_mshr_miss_latency::total 19157.511696 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu1.data 18844.703590 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu2.data 19314.331730 # average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_miss_latency::total 19157.511696 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu2.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu2.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::total inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu1.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu2.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu1.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.dtb.inst_hits 0 # ITB inst hits
system.cpu1.dtb.inst_misses 0 # ITB inst misses
system.cpu1.dtb.read_hits 2093956 # DTB read hits
system.cpu1.dtb.read_misses 2077 # DTB read misses
system.cpu1.dtb.write_hits 1416211 # DTB write hits
system.cpu1.dtb.write_misses 373 # DTB write misses
system.cpu1.dtb.flush_tlb 554 # Number of times complete TLB was flushed
system.cpu1.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.dtb.flush_tlb_mva_asid 221 # Number of times TLB was flushed by MVA & ASID
system.cpu1.dtb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID
system.cpu1.dtb.flush_entries 1760 # Number of entries that have been flushed from TLB
system.cpu1.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.dtb.prefetch_faults 36 # Number of TLB faults due to prefetch
system.cpu1.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.dtb.perms_faults 79 # Number of TLB faults due to permissions restrictions
system.cpu1.dtb.read_accesses 2096033 # DTB read accesses
system.cpu1.dtb.write_accesses 1416584 # DTB write accesses
system.cpu1.dtb.inst_accesses 0 # ITB inst accesses
system.cpu1.dtb.hits 3510167 # DTB hits
system.cpu1.dtb.misses 2450 # DTB misses
system.cpu1.dtb.accesses 3512617 # DTB accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu1.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu1.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu1.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu1.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu1.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu1.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu1.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu1.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu1.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu1.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu1.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu1.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu1.itb.inst_hits 8180990 # ITB inst hits
system.cpu1.itb.inst_misses 1185 # ITB inst misses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.write_hits 0 # DTB write hits
system.cpu1.itb.write_misses 0 # DTB write misses
system.cpu1.itb.flush_tlb 554 # Number of times complete TLB was flushed
system.cpu1.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu1.itb.flush_tlb_mva_asid 221 # Number of times TLB was flushed by MVA & ASID
system.cpu1.itb.flush_tlb_asid 12 # Number of times TLB was flushed by ASID
system.cpu1.itb.flush_entries 944 # Number of entries that have been flushed from TLB
system.cpu1.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu1.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu1.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu1.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu1.itb.read_accesses 0 # DTB read accesses
system.cpu1.itb.write_accesses 0 # DTB write accesses
system.cpu1.itb.inst_accesses 8182175 # ITB inst accesses
system.cpu1.itb.hits 8180990 # DTB hits
system.cpu1.itb.misses 1185 # DTB misses
system.cpu1.itb.accesses 8182175 # DTB accesses
system.cpu1.numCycles 581419148 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu1.committedInsts 7970398 # Number of instructions committed
system.cpu1.committedOps 10116193 # Number of ops (including micro ops) committed
system.cpu1.num_int_alu_accesses 9089557 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 2019 # Number of float alu accesses
system.cpu1.num_func_calls 304010 # number of times a function call or return occured
system.cpu1.num_conditional_control_insts 1112792 # number of instructions that are conditional controls
system.cpu1.num_int_insts 9089557 # number of integer instructions
system.cpu1.num_fp_insts 2019 # number of float instructions
system.cpu1.num_int_register_reads 52989642 # number of times the integer registers were read
system.cpu1.num_int_register_writes 9881584 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 1441 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 580 # number of times the floating registers were written
system.cpu1.num_mem_refs 3676962 # number of memory refs
system.cpu1.num_load_insts 2186992 # Number of load instructions
system.cpu1.num_store_insts 1489970 # Number of store instructions
system.cpu1.num_idle_cycles 545339727.510646 # Number of idle cycles
system.cpu1.num_busy_cycles 36079420.489354 # Number of busy cycles
system.cpu1.not_idle_fraction 0.062054 # Percentage of non-idle cycles
system.cpu1.idle_fraction 0.937946 # Percentage of idle cycles
system.cpu1.Branches 1445114 # Number of branches fetched
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
system.cpu2.branchPred.lookups 4780240 # Number of BP lookups
system.cpu2.branchPred.condPredicted 3898194 # Number of conditional branches predicted
system.cpu2.branchPred.condIncorrect 223690 # Number of conditional branches incorrect
system.cpu2.branchPred.BTBLookups 3180058 # Number of BTB lookups
system.cpu2.branchPred.BTBHits 2524004 # Number of BTB hits
system.cpu2.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu2.branchPred.BTBHitPct 79.369747 # BTB Hit Percentage
system.cpu2.branchPred.usedRAS 414035 # Number of times the RAS was used to get a target.
system.cpu2.branchPred.RASInCorrect 21682 # Number of incorrect RAS predictions.
system.cpu2.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu2.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu2.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu2.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu2.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu2.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu2.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu2.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu2.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu2.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu2.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu2.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu2.dstage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.dstage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu2.dtb.inst_hits 0 # ITB inst hits
system.cpu2.dtb.inst_misses 0 # ITB inst misses
system.cpu2.dtb.read_hits 10926394 # DTB read hits
system.cpu2.dtb.read_misses 23081 # DTB read misses
system.cpu2.dtb.write_hits 3349602 # DTB write hits
system.cpu2.dtb.write_misses 6536 # DTB write misses
system.cpu2.dtb.flush_tlb 552 # Number of times complete TLB was flushed
system.cpu2.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu2.dtb.flush_tlb_mva_asid 540 # Number of times TLB was flushed by MVA & ASID
system.cpu2.dtb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID
system.cpu2.dtb.flush_entries 2337 # Number of entries that have been flushed from TLB
system.cpu2.dtb.align_faults 728 # Number of TLB faults due to alignment restrictions
system.cpu2.dtb.prefetch_faults 164 # Number of TLB faults due to prefetch
system.cpu2.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu2.dtb.perms_faults 452 # Number of TLB faults due to permissions restrictions
system.cpu2.dtb.read_accesses 10949475 # DTB read accesses
system.cpu2.dtb.write_accesses 3356138 # DTB write accesses
system.cpu2.dtb.inst_accesses 0 # ITB inst accesses
system.cpu2.dtb.hits 14275996 # DTB hits
system.cpu2.dtb.misses 29617 # DTB misses
system.cpu2.dtb.accesses 14305613 # DTB accesses
system.cpu2.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits
system.cpu2.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses
system.cpu2.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits
system.cpu2.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses
system.cpu2.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits
system.cpu2.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID
system.cpu2.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB
system.cpu2.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu2.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions
system.cpu2.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses
system.cpu2.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses
system.cpu2.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses
system.cpu2.istage2_mmu.stage2_tlb.hits 0 # DTB hits
system.cpu2.istage2_mmu.stage2_tlb.misses 0 # DTB misses
system.cpu2.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses
system.cpu2.itb.inst_hits 4052754 # ITB inst hits
system.cpu2.itb.inst_misses 4681 # ITB inst misses
system.cpu2.itb.read_hits 0 # DTB read hits
system.cpu2.itb.read_misses 0 # DTB read misses
system.cpu2.itb.write_hits 0 # DTB write hits
system.cpu2.itb.write_misses 0 # DTB write misses
system.cpu2.itb.flush_tlb 552 # Number of times complete TLB was flushed
system.cpu2.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA
system.cpu2.itb.flush_tlb_mva_asid 540 # Number of times TLB was flushed by MVA & ASID
system.cpu2.itb.flush_tlb_asid 21 # Number of times TLB was flushed by ASID
system.cpu2.itb.flush_entries 1722 # Number of entries that have been flushed from TLB
system.cpu2.itb.align_faults 0 # Number of TLB faults due to alignment restrictions
system.cpu2.itb.prefetch_faults 0 # Number of TLB faults due to prefetch
system.cpu2.itb.domain_faults 0 # Number of TLB faults due to domain restrictions
system.cpu2.itb.perms_faults 963 # Number of TLB faults due to permissions restrictions
system.cpu2.itb.read_accesses 0 # DTB read accesses
system.cpu2.itb.write_accesses 0 # DTB write accesses
system.cpu2.itb.inst_accesses 4057435 # ITB inst accesses
system.cpu2.itb.hits 4052754 # DTB hits
system.cpu2.itb.misses 4681 # DTB misses
system.cpu2.itb.accesses 4057435 # DTB accesses
system.cpu2.numCycles 88329548 # number of cpu cycles simulated
system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu2.fetch.icacheStallCycles 9368286 # Number of cycles fetch is stalled on an Icache miss
system.cpu2.fetch.Insts 32480016 # Number of instructions fetch has processed
system.cpu2.fetch.Branches 4780240 # Number of branches that fetch encountered
system.cpu2.fetch.predictedBranches 2938039 # Number of branches that fetch has predicted taken
system.cpu2.fetch.Cycles 6853051 # Number of cycles fetch has run and was not squashing or blocked
system.cpu2.fetch.SquashCycles 1759446 # Number of cycles fetch has spent squashing
system.cpu2.fetch.TlbCycles 50956 # Number of cycles fetch has spent waiting for tlb
system.cpu2.fetch.BlockedCycles 19165610 # Number of cycles fetch has spent blocked
system.cpu2.fetch.MiscStallCycles 248 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu2.fetch.PendingDrainCycles 867 # Number of cycles fetch has spent waiting on pipes to drain
system.cpu2.fetch.PendingTrapStallCycles 33412 # Number of stall cycles due to pending traps
system.cpu2.fetch.PendingQuiesceStallCycles 724302 # Number of stall cycles due to pending quiesce instructions
system.cpu2.fetch.IcacheWaitRetryStallCycles 479 # Number of stall cycles due to full MSHR
system.cpu2.fetch.CacheLines 4051341 # Number of cache lines fetched
system.cpu2.fetch.IcacheSquashes 290206 # Number of outstanding Icache misses that were squashed
system.cpu2.fetch.ItlbSquashes 2075 # Number of outstanding ITLB misses that were squashed
system.cpu2.fetch.rateDist::samples 37405927 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::mean 1.043731 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::stdev 2.431289 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::0 30558019 81.69% 81.69% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::1 385772 1.03% 82.72% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::2 515915 1.38% 84.10% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::3 819609 2.19% 86.29% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::4 625256 1.67% 87.97% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::5 342326 0.92% 88.88% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::6 1044683 2.79% 91.67% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::7 230213 0.62% 92.29% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::8 2884134 7.71% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.rateDist::total 37405927 # Number of instructions fetched each cycle (Total)
system.cpu2.fetch.branchRate 0.054118 # Number of branch fetches per cycle
system.cpu2.fetch.rate 0.367714 # Number of inst fetches per cycle
system.cpu2.decode.IdleCycles 9993670 # Number of cycles decode is idle
system.cpu2.decode.BlockedCycles 19739606 # Number of cycles decode is blocked
system.cpu2.decode.RunCycles 6190224 # Number of cycles decode is running
system.cpu2.decode.UnblockCycles 324742 # Number of cycles decode is unblocking
system.cpu2.decode.SquashCycles 1156786 # Number of cycles decode is squashing
system.cpu2.decode.BranchResolved 609493 # Number of times decode resolved a branch
system.cpu2.decode.BranchMispred 53173 # Number of times decode detected a branch misprediction
system.cpu2.decode.DecodedInsts 36942390 # Number of instructions handled by decode
system.cpu2.decode.SquashedInsts 178785 # Number of squashed instructions handled by decode
system.cpu2.rename.SquashCycles 1156786 # Number of cycles rename is squashing
system.cpu2.rename.IdleCycles 10542033 # Number of cycles rename is idle
system.cpu2.rename.BlockCycles 6802518 # Number of cycles rename is blocking
system.cpu2.rename.serializeStallCycles 11433975 # count of cycles rename stalled for serializing inst
system.cpu2.rename.RunCycles 5951508 # Number of cycles rename is running
system.cpu2.rename.UnblockCycles 1518203 # Number of cycles rename is unblocking
system.cpu2.rename.RenamedInsts 34853467 # Number of instructions processed by rename
system.cpu2.rename.ROBFullEvents 104 # Number of times rename has blocked due to ROB full
system.cpu2.rename.IQFullEvents 325261 # Number of times rename has blocked due to IQ full
system.cpu2.rename.LSQFullEvents 883658 # Number of times rename has blocked due to LSQ full
system.cpu2.rename.FullRegisterEvents 140 # Number of times there has been no free registers
system.cpu2.rename.RenamedOperands 37388012 # Number of destination operands rename has renamed
system.cpu2.rename.RenameLookups 160878048 # Number of register rename lookups that rename has made
system.cpu2.rename.int_rename_lookups 148313673 # Number of integer rename lookups
system.cpu2.rename.fp_rename_lookups 3357 # Number of floating rename lookups
system.cpu2.rename.CommittedMaps 26544776 # Number of HB maps that are committed
system.cpu2.rename.UndoneMaps 10843235 # Number of HB maps that are undone due to squashing
system.cpu2.rename.serializingInsts 285604 # count of serializing insts renamed
system.cpu2.rename.tempSerializingInsts 261905 # count of temporary serializing insts renamed
system.cpu2.rename.skidInsts 3322163 # count of insts added to the skid buffer
system.cpu2.memDep0.insertedLoads 6624625 # Number of loads inserted to the mem dependence unit.
system.cpu2.memDep0.insertedStores 3901879 # Number of stores inserted to the mem dependence unit.
system.cpu2.memDep0.conflictingLoads 530898 # Number of conflicting loads.
system.cpu2.memDep0.conflictingStores 772979 # Number of conflicting stores.
system.cpu2.iq.iqInstsAdded 32179363 # Number of instructions added to the IQ (excludes non-spec)
system.cpu2.iq.iqNonSpecInstsAdded 501455 # Number of non-speculative instructions added to the IQ
system.cpu2.iq.iqInstsIssued 34749523 # Number of instructions issued
system.cpu2.iq.iqSquashedInstsIssued 55329 # Number of squashed instructions issued
system.cpu2.iq.iqSquashedInstsExamined 7166724 # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu2.iq.iqSquashedOperandsExamined 19100923 # Number of squashed operands that are examined and possibly removed from graph
system.cpu2.iq.iqSquashedNonSpecRemoved 145150 # Number of squashed non-spec instructions that were removed
system.cpu2.iq.issued_per_cycle::samples 37405927 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::mean 0.928984 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::stdev 1.590317 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::0 24720555 66.09% 66.09% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::1 3979487 10.64% 76.73% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::2 2312001 6.18% 82.91% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::3 1968335 5.26% 88.17% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::4 2779247 7.43% 95.60% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::5 968566 2.59% 98.19% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::6 497905 1.33% 99.52% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::7 144867 0.39% 99.91% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::8 34964 0.09% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
system.cpu2.iq.issued_per_cycle::total 37405927 # Number of insts issued each cycle
system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntAlu 19427 1.28% 1.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntMult 1 0.00% 1.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::IntDiv 0 0.00% 1.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatAdd 0 0.00% 1.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCmp 0 0.00% 1.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatCvt 0 0.00% 1.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatMult 0 0.00% 1.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatDiv 0 0.00% 1.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 1.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAdd 0 0.00% 1.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 1.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdAlu 0 0.00% 1.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCmp 0 0.00% 1.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdCvt 0 0.00% 1.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMisc 0 0.00% 1.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMult 0 0.00% 1.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 1.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShift 0 0.00% 1.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 1.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 1.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 1.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 1.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 1.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 1.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 1.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 1.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 1.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 1.28% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemRead 1392100 91.45% 92.73% # attempts to use FU when none available
system.cpu2.iq.fu_full::MemWrite 110700 7.27% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu2.iq.FU_type_0::No_OpClass 8337 0.02% 0.02% # Type of FU issued
system.cpu2.iq.FU_type_0::IntAlu 19784762 56.94% 56.96% # Type of FU issued
system.cpu2.iq.FU_type_0::IntMult 28044 0.08% 57.04% # Type of FU issued
system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 57.04% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 57.04% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 57.04% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 57.04% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 57.04% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 57.04% # Type of FU issued
system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 57.04% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 57.04% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 57.04% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 57.04% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 57.04% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 57.04% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMisc 4 0.00% 57.04% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 57.04% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 57.04% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 57.04% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdShiftAcc 4 0.00% 57.04% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 57.04% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.04% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.04% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.04% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.04% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.04% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMisc 384 0.00% 57.04% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 57.04% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatMultAcc 4 0.00% 57.04% # Type of FU issued
system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.04% # Type of FU issued
system.cpu2.iq.FU_type_0::MemRead 11409832 32.83% 89.88% # Type of FU issued
system.cpu2.iq.FU_type_0::MemWrite 3518152 10.12% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
system.cpu2.iq.FU_type_0::total 34749523 # Type of FU issued
system.cpu2.iq.rate 0.393408 # Inst issue rate
system.cpu2.iq.fu_busy_cnt 1522228 # FU busy when requested
system.cpu2.iq.fu_busy_rate 0.043806 # FU busy rate (busy events/executed inst)
system.cpu2.iq.int_inst_queue_reads 108504523 # Number of integer instruction queue reads
system.cpu2.iq.int_inst_queue_writes 39852721 # Number of integer instruction queue writes
system.cpu2.iq.int_inst_queue_wakeup_accesses 28051848 # Number of integer instruction queue wakeup accesses
system.cpu2.iq.fp_inst_queue_reads 7496 # Number of floating instruction queue reads
system.cpu2.iq.fp_inst_queue_writes 3959 # Number of floating instruction queue writes
system.cpu2.iq.fp_inst_queue_wakeup_accesses 3344 # Number of floating instruction queue wakeup accesses
system.cpu2.iq.int_alu_accesses 36259410 # Number of integer alu accesses
system.cpu2.iq.fp_alu_accesses 4004 # Number of floating point alu accesses
system.cpu2.iew.lsq.thread0.forwLoads 206643 # Number of loads that had data forwarded from stores
system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
system.cpu2.iew.lsq.thread0.squashedLoads 1533647 # Number of loads squashed
system.cpu2.iew.lsq.thread0.ignoredResponses 2027 # Number of memory responses ignored because the instruction is squashed
system.cpu2.iew.lsq.thread0.memOrderViolation 9444 # Number of memory ordering violations
system.cpu2.iew.lsq.thread0.squashedStores 562515 # Number of stores squashed
system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
system.cpu2.iew.lsq.thread0.rescheduledLoads 5286265 # Number of loads that were rescheduled
system.cpu2.iew.lsq.thread0.cacheBlocked 344866 # Number of times an access to memory failed due to the cache being blocked
system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle
system.cpu2.iew.iewSquashCycles 1156786 # Number of cycles IEW is squashing
system.cpu2.iew.iewBlockCycles 5177746 # Number of cycles IEW is blocking
system.cpu2.iew.iewUnblockCycles 87629 # Number of cycles IEW is unblocking
system.cpu2.iew.iewDispatchedInsts 32763326 # Number of instructions dispatched to IQ
system.cpu2.iew.iewDispSquashedInsts 61736 # Number of squashed instructions skipped by dispatch
system.cpu2.iew.iewDispLoadInsts 6624625 # Number of dispatched load instructions
system.cpu2.iew.iewDispStoreInsts 3901879 # Number of dispatched store instructions
system.cpu2.iew.iewDispNonSpecInsts 359192 # Number of dispatched non-speculative instructions
system.cpu2.iew.iewIQFullEvents 29253 # Number of times the IQ has become full, causing a stall
system.cpu2.iew.iewLSQFullEvents 2415 # Number of times the LSQ has become full, causing a stall
system.cpu2.iew.memOrderViolationEvents 9444 # Number of memory order violations
system.cpu2.iew.predictedTakenIncorrect 107780 # Number of branches that were predicted taken incorrectly
system.cpu2.iew.predictedNotTakenIncorrect 89787 # Number of branches that were predicted not taken incorrectly
system.cpu2.iew.branchMispredicts 197567 # Number of branch mispredicts detected at execute
system.cpu2.iew.iewExecutedInsts 33835206 # Number of executed instructions
system.cpu2.iew.iewExecLoadInsts 11139307 # Number of load instructions executed
system.cpu2.iew.iewExecSquashedInsts 914317 # Number of squashed instructions skipped in execute
system.cpu2.iew.exec_swp 0 # number of swp insts executed
system.cpu2.iew.exec_nop 82508 # number of nop insts executed
system.cpu2.iew.exec_refs 14623996 # number of memory reference insts executed
system.cpu2.iew.exec_branches 3761047 # Number of branches executed
system.cpu2.iew.exec_stores 3484689 # Number of stores executed
system.cpu2.iew.exec_rate 0.383056 # Inst execution rate
system.cpu2.iew.wb_sent 33433924 # cumulative count of insts sent to commit
system.cpu2.iew.wb_count 28055192 # cumulative count of insts written-back
system.cpu2.iew.wb_producers 16098734 # num instructions producing a value
system.cpu2.iew.wb_consumers 29085804 # num instructions consuming a value
system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
system.cpu2.iew.wb_rate 0.317620 # insts written-back per cycle
system.cpu2.iew.wb_fanout 0.553491 # average fanout of values written-back
system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
system.cpu2.commit.commitSquashedInsts 7134883 # The number of squashed insts skipped by commit
system.cpu2.commit.commitNonSpecStalls 356305 # The number of times commit has been forced to stall to communicate backwards
system.cpu2.commit.branchMispredicts 171320 # The number of times a branch was mispredicted
system.cpu2.commit.committed_per_cycle::samples 36248935 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::mean 0.700393 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::stdev 1.738300 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::0 27340525 75.42% 75.42% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::1 4430140 12.22% 87.65% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::2 1255420 3.46% 91.11% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::3 637620 1.76% 92.87% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::4 510981 1.41% 94.28% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::5 317875 0.88% 95.15% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::6 419132 1.16% 96.31% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::7 311355 0.86% 97.17% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::8 1025887 2.83% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
system.cpu2.commit.committed_per_cycle::total 36248935 # Number of insts commited each cycle
system.cpu2.commit.committedInsts 20549284 # Number of instructions committed
system.cpu2.commit.committedOps 25388512 # Number of ops (including micro ops) committed
system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed
system.cpu2.commit.refs 8430342 # Number of memory references committed
system.cpu2.commit.loads 5090978 # Number of loads committed
system.cpu2.commit.membars 94231 # Number of memory barriers committed
system.cpu2.commit.branches 3241086 # Number of branches committed
system.cpu2.commit.fp_insts 3299 # Number of committed floating point instructions.
system.cpu2.commit.int_insts 22644563 # Number of committed integer instructions.
system.cpu2.commit.function_calls 295800 # Number of function calls committed.
system.cpu2.commit.bw_lim_events 1025887 # number cycles where commit BW limit reached
system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits
system.cpu2.rob.rob_reads 67225559 # The number of ROB reads
system.cpu2.rob.rob_writes 66247729 # The number of ROB writes
system.cpu2.timesIdled 359329 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu2.idleCycles 50923621 # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu2.quiesceCycles 3554004914 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
system.cpu2.committedInsts 20493925 # Number of Instructions Simulated
system.cpu2.committedOps 25333153 # Number of Ops (including micro ops) Simulated
system.cpu2.committedInsts_total 20493925 # Number of Instructions Simulated
system.cpu2.cpi 4.310036 # CPI: Cycles Per Instruction
system.cpu2.cpi_total 4.310036 # CPI: Total CPI of All Threads
system.cpu2.ipc 0.232017 # IPC: Instructions Per Cycle
system.cpu2.ipc_total 0.232017 # IPC: Total IPC of All Threads
system.cpu2.int_regfile_reads 157011420 # number of integer regfile reads
system.cpu2.int_regfile_writes 29864331 # number of integer regfile writes
system.cpu2.fp_regfile_reads 46835 # number of floating regfile reads
system.cpu2.fp_regfile_writes 45178 # number of floating regfile writes
system.cpu2.misc_regfile_reads 66864323 # number of misc regfile reads
system.cpu2.misc_regfile_writes 296992 # number of misc regfile writes
system.iocache.tags.replacements 0 # number of replacements
system.iocache.tags.tagsinuse 0 # Cycle average of tags in use
system.iocache.tags.total_refs 0 # Total number of references to valid blocks.
system.iocache.tags.sampled_refs 0 # Sample count of references to valid blocks.
system.iocache.tags.avg_refs nan # Average number of references to valid blocks.
system.iocache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.iocache.tags.tag_accesses 0 # Number of tag accesses
system.iocache.tags.data_accesses 0 # Number of data accesses
system.iocache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.iocache.blocked::no_mshrs 0 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
system.iocache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.ReadReq_mshr_uncacheable_latency::realview.clcd 1347826044250 # number of ReadReq MSHR uncacheable cycles
system.iocache.ReadReq_mshr_uncacheable_latency::total 1347826044250 # number of ReadReq MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::realview.clcd 1347826044250 # number of overall MSHR uncacheable cycles
system.iocache.overall_mshr_uncacheable_latency::total 1347826044250 # number of overall MSHR uncacheable cycles
system.iocache.ReadReq_avg_mshr_uncacheable_latency::realview.clcd inf # average ReadReq mshr uncacheable latency
system.iocache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::realview.clcd inf # average overall mshr uncacheable latency
system.iocache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu2.kern.inst.arm 0 # number of arm instructions executed
system.cpu2.kern.inst.quiesce 0 # number of quiesce instructions executed
---------- End Simulation Statistics ----------
Reference in a new issue View git blame Copy permalink