047caf24ba
This function was used by the now-defunct InOrderCPU model. Since this model is no longer in gem5, this function was not called from anywhere in the code.
349 lines
12 KiB
C++
349 lines
12 KiB
C++
/*
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* Copyright (c) 2011-2012, 2014 ARM Limited
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* Copyright (c) 2010 The University of Edinburgh
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2004-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Kevin Lim
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* Korey Sewell
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* Timothy M. Jones
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* Nilay Vaish
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*/
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#ifndef __CPU_PRED_BPRED_UNIT_HH__
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#define __CPU_PRED_BPRED_UNIT_HH__
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#include <deque>
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#include "base/statistics.hh"
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#include "base/types.hh"
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#include "cpu/pred/btb.hh"
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#include "cpu/pred/indirect.hh"
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#include "cpu/pred/ras.hh"
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#include "cpu/inst_seq.hh"
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#include "cpu/static_inst.hh"
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#include "params/BranchPredictor.hh"
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#include "sim/probe/pmu.hh"
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#include "sim/sim_object.hh"
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/**
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* Basically a wrapper class to hold both the branch predictor
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* and the BTB.
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*/
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class BPredUnit : public SimObject
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{
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public:
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typedef BranchPredictorParams Params;
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/**
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* @param params The params object, that has the size of the BP and BTB.
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*/
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BPredUnit(const Params *p);
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/**
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* Registers statistics.
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*/
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void regStats() override;
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void regProbePoints() override;
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/** Perform sanity checks after a drain. */
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void drainSanityCheck() const;
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/**
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* Predicts whether or not the instruction is a taken branch, and the
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* target of the branch if it is taken.
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* @param inst The branch instruction.
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* @param PC The predicted PC is passed back through this parameter.
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* @param tid The thread id.
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* @return Returns if the branch is taken or not.
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*/
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bool predict(const StaticInstPtr &inst, const InstSeqNum &seqNum,
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TheISA::PCState &pc, ThreadID tid);
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// @todo: Rename this function.
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virtual void uncondBranch(ThreadID tid, Addr pc, void * &bp_history) = 0;
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/**
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* Tells the branch predictor to commit any updates until the given
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* sequence number.
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* @param done_sn The sequence number to commit any older updates up until.
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* @param tid The thread id.
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*/
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void update(const InstSeqNum &done_sn, ThreadID tid);
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/**
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* Squashes all outstanding updates until a given sequence number.
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* @param squashed_sn The sequence number to squash any younger updates up
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* until.
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* @param tid The thread id.
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*/
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void squash(const InstSeqNum &squashed_sn, ThreadID tid);
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/**
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* Squashes all outstanding updates until a given sequence number, and
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* corrects that sn's update with the proper address and taken/not taken.
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* @param squashed_sn The sequence number to squash any younger updates up
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* until.
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* @param corr_target The correct branch target.
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* @param actually_taken The correct branch direction.
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* @param tid The thread id.
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*/
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void squash(const InstSeqNum &squashed_sn,
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const TheISA::PCState &corr_target,
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bool actually_taken, ThreadID tid);
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/**
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* @param bp_history Pointer to the history object. The predictor
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* will need to update any state and delete the object.
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*/
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virtual void squash(ThreadID tid, void *bp_history) = 0;
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/**
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* Looks up a given PC in the BP to see if it is taken or not taken.
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* @param inst_PC The PC to look up.
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* @param bp_history Pointer that will be set to an object that
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* has the branch predictor state associated with the lookup.
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* @return Whether the branch is taken or not taken.
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*/
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virtual bool lookup(ThreadID tid, Addr instPC, void * &bp_history) = 0;
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/**
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* If a branch is not taken, because the BTB address is invalid or missing,
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* this function sets the appropriate counter in the global and local
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* predictors to not taken.
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* @param inst_PC The PC to look up the local predictor.
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* @param bp_history Pointer that will be set to an object that
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* has the branch predictor state associated with the lookup.
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*/
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virtual void btbUpdate(ThreadID tid, Addr instPC, void * &bp_history) = 0;
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/**
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* Looks up a given PC in the BTB to see if a matching entry exists.
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* @param inst_PC The PC to look up.
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* @return Whether the BTB contains the given PC.
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*/
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bool BTBValid(Addr instPC)
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{ return BTB.valid(instPC, 0); }
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/**
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* Looks up a given PC in the BTB to get the predicted target.
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* @param inst_PC The PC to look up.
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* @return The address of the target of the branch.
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*/
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TheISA::PCState BTBLookup(Addr instPC)
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{ return BTB.lookup(instPC, 0); }
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/**
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* Updates the BP with taken/not taken information.
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* @param inst_PC The branch's PC that will be updated.
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* @param taken Whether the branch was taken or not taken.
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* @param bp_history Pointer to the branch predictor state that is
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* associated with the branch lookup that is being updated.
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* @param squashed Set to true when this function is called during a
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* squash operation.
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* @todo Make this update flexible enough to handle a global predictor.
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*/
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virtual void update(ThreadID tid, Addr instPC, bool taken,
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void *bp_history, bool squashed) = 0;
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/**
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* Deletes the associated history with a branch, performs no predictor
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* updates. Used for branches that mispredict and update tables but
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* are still speculative and later retire.
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* @param bp_history History to delete associated with this predictor
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*/
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virtual void retireSquashed(ThreadID tid, void *bp_history) = 0;
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/**
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* Updates the BTB with the target of a branch.
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* @param inst_PC The branch's PC that will be updated.
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* @param target_PC The branch's target that will be added to the BTB.
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*/
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void BTBUpdate(Addr instPC, const TheISA::PCState &target)
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{ BTB.update(instPC, target, 0); }
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virtual unsigned getGHR(ThreadID tid, void* bp_history) const { return 0; }
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void dump();
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private:
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struct PredictorHistory {
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/**
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* Makes a predictor history struct that contains any
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* information needed to update the predictor, BTB, and RAS.
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*/
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PredictorHistory(const InstSeqNum &seq_num, Addr instPC,
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bool pred_taken, void *bp_history,
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ThreadID _tid)
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: seqNum(seq_num), pc(instPC), bpHistory(bp_history), RASTarget(0),
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RASIndex(0), tid(_tid), predTaken(pred_taken), usedRAS(0), pushedRAS(0),
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wasCall(0), wasReturn(0), wasSquashed(0), wasIndirect(0)
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{}
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bool operator==(const PredictorHistory &entry) const {
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return this->seqNum == entry.seqNum;
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}
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/** The sequence number for the predictor history entry. */
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InstSeqNum seqNum;
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/** The PC associated with the sequence number. */
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Addr pc;
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/** Pointer to the history object passed back from the branch
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* predictor. It is used to update or restore state of the
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* branch predictor.
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*/
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void *bpHistory;
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/** The RAS target (only valid if a return). */
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TheISA::PCState RASTarget;
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/** The RAS index of the instruction (only valid if a call). */
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unsigned RASIndex;
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/** The thread id. */
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ThreadID tid;
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/** Whether or not it was predicted taken. */
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bool predTaken;
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/** Whether or not the RAS was used. */
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bool usedRAS;
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/* Whether or not the RAS was pushed */
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bool pushedRAS;
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/** Whether or not the instruction was a call. */
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bool wasCall;
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/** Whether or not the instruction was a return. */
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bool wasReturn;
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/** Whether this instruction has already mispredicted/updated bp */
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bool wasSquashed;
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/** Wether this instruction was an indirect branch */
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bool wasIndirect;
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};
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typedef std::deque<PredictorHistory> History;
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/** Number of the threads for which the branch history is maintained. */
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const unsigned numThreads;
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/**
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* The per-thread predictor history. This is used to update the predictor
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* as instructions are committed, or restore it to the proper state after
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* a squash.
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*/
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std::vector<History> predHist;
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/** The BTB. */
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DefaultBTB BTB;
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/** The per-thread return address stack. */
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std::vector<ReturnAddrStack> RAS;
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/** Option to disable indirect predictor. */
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const bool useIndirect;
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/** The indirect target predictor. */
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IndirectPredictor iPred;
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/** Stat for number of BP lookups. */
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Stats::Scalar lookups;
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/** Stat for number of conditional branches predicted. */
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Stats::Scalar condPredicted;
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/** Stat for number of conditional branches predicted incorrectly. */
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Stats::Scalar condIncorrect;
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/** Stat for number of BTB lookups. */
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Stats::Scalar BTBLookups;
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/** Stat for number of BTB hits. */
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Stats::Scalar BTBHits;
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/** Stat for number of times the BTB is correct. */
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Stats::Scalar BTBCorrect;
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/** Stat for percent times an entry in BTB found. */
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Stats::Formula BTBHitPct;
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/** Stat for number of times the RAS is used to get a target. */
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Stats::Scalar usedRAS;
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/** Stat for number of times the RAS is incorrect. */
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Stats::Scalar RASIncorrect;
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/** Stat for the number of indirect target lookups.*/
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Stats::Scalar indirectLookups;
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/** Stat for the number of indirect target hits.*/
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Stats::Scalar indirectHits;
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/** Stat for the number of indirect target misses.*/
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Stats::Scalar indirectMisses;
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/** Stat for the number of indirect target mispredictions.*/
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Stats::Scalar indirectMispredicted;
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protected:
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/** Number of bits to shift instructions by for predictor addresses. */
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const unsigned instShiftAmt;
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/**
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* @{
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* @name PMU Probe points.
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*/
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/**
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* Helper method to instantiate probe points belonging to this
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* object.
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*
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* @param name Name of the probe point.
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* @return A unique_ptr to the new probe point.
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*/
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ProbePoints::PMUUPtr pmuProbePoint(const char *name);
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/**
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* Branches seen by the branch predictor
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*
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* @note This counter includes speculative branches.
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*/
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ProbePoints::PMUUPtr ppBranches;
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/** Miss-predicted branches */
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ProbePoints::PMUUPtr ppMisses;
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/** @} */
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};
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#endif // __CPU_PRED_BPRED_UNIT_HH__
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