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gem5/src/mem
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Nilay Vaish 39e9445468 ruby: consumer: avoid using receiver side clock 
A set of patches was recently committed to allow multiple clock domains
in ruby. In those patches, I had inadvertently made an incorrect use of
the clocks. Suppose object A needs to schedule an event on object B. It
was possible that A accesses B's clock to schedule the event. This is not
possible in actual system. Hence, changes are being to the Consumer class
so as to avoid such happenings. Note that in a multi eventq simulation,
this can possibly lead to an incorrect simulation.

There are two functions in the Consumer class that are used for scheduling
events. The first function takes in the relative delay over the current time
as the argument and adds the current time to it for scheduling the event.
The second function takes in the absolute time (in ticks) for scheduling the
event. The first function is now being moved to protected section of the
class so that only objects of the derived classes can use it. All other
objects will have to specify absolute time while scheduling an event
for some consumer.
2013-03-22 15:53:26 -05:00
..
cache mem: Fix sender state bug and delay popping 2013-02-19 12:57:47 -05:00
config mem: Remove the IIC replacement policy 2013-01-07 13:05:39 -05:00
protocol ruby: remove unsued profile functions 2013-03-22 15:53:25 -05:00
ruby ruby: consumer: avoid using receiver side clock 2013-03-22 15:53:26 -05:00
slicc slicc: remove check if the L1Cache has a sequencer 2013-03-22 15:53:24 -05:00
abstract_mem.cc base: Encapsulate the underlying fields in AddrRange 2013-01-07 13:05:38 -05:00
abstract_mem.hh base: Encapsulate the underlying fields in AddrRange 2013-01-07 13:05:38 -05:00
AbstractMemory.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
addr_mapper.cc mem: Add predecessor to SenderState base class 2013-02-19 05:56:05 -05:00
addr_mapper.hh mem: Add predecessor to SenderState base class 2013-02-19 05:56:05 -05:00
AddrMapper.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
bridge.cc mem: Enforce strict use of busFirst- and busLastWordTime 2013-02-19 05:56:06 -05:00
bridge.hh mem: Add predecessor to SenderState base class 2013-02-19 05:56:05 -05:00
Bridge.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
bus.cc mem: Merge ranges in bus before passing them on 2013-03-01 13:20:19 -05:00
bus.hh mem: Merge ranges in bus before passing them on 2013-03-01 13:20:19 -05:00
Bus.py sim: Add a system-global option to bypass caches 2013-02-15 17:40:09 -05:00
coherent_bus.cc mem: Enforce strict use of busFirst- and busLastWordTime 2013-02-19 05:56:06 -05:00
coherent_bus.hh sim: Make clock private and access using clockPeriod() 2013-02-19 05:56:06 -05:00
comm_monitor.cc mem: Add predecessor to SenderState base class 2013-02-19 05:56:05 -05:00
comm_monitor.hh mem: Add predecessor to SenderState base class 2013-02-19 05:56:05 -05:00
CommMonitor.py mem: Add tracing support in the communication monitor 2013-01-07 13:05:37 -05:00
fs_translating_port_proxy.cc mem: fix bug with CopyStringOut and null string termination. 2012-05-10 18:04:27 -05:00
fs_translating_port_proxy.hh MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
mem_object.cc Port: Add protocol-agnostic ports in the port hierarchy 2012-10-15 08:12:35 -04:00
mem_object.hh Port: Add protocol-agnostic ports in the port hierarchy 2012-10-15 08:12:35 -04:00
MemObject.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
mport.cc MEM: Separate snoops and normal memory requests/responses 2012-04-14 05:45:07 -04:00
mport.hh MEM: Separate requests and responses for timing accesses 2012-05-01 13:40:42 -04:00
noncoherent_bus.cc mem: Enforce strict use of busFirst- and busLastWordTime 2013-02-19 05:56:06 -05:00
noncoherent_bus.hh sim: Make clock private and access using clockPeriod() 2013-02-19 05:56:06 -05:00
packet.cc mem: Add predecessor to SenderState base class 2013-02-19 05:56:05 -05:00
packet.hh mem: Make packet bus-related time accounting relative 2013-02-19 05:56:06 -05:00
packet_access.hh arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh 2009-09-23 08:34:21 -07:00
packet_queue.cc mem: Add sanity check to packet queue size 2013-01-07 13:05:35 -05:00
packet_queue.hh sim: have a curTick per eventq 2012-11-16 10:27:47 -06:00
page_table.cc Fix: Address a few benign memory leaks 2012-07-09 12:35:30 -04:00
page_table.hh SE/FS: Get rid of includes of config/full_system.hh. 2011-11-18 02:20:22 -08:00
physical.cc mem: Merge interleaved ranges when creating backing store 2013-03-01 13:20:21 -05:00
physical.hh mem: Merge ranges that are part of the conf table 2013-01-07 13:05:38 -05:00
port.cc Port: Add protocol-agnostic ports in the port hierarchy 2012-10-15 08:12:35 -04:00
port.hh mem: Fix typo in port comments 2012-10-31 09:28:23 -04:00
port_proxy.cc MEM: Remove the Broadcast destination from the packet 2012-04-14 05:45:55 -04:00
port_proxy.hh MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
qport.hh sim: Move the draining interface into a separate base class 2012-11-02 11:32:01 -05:00
request.hh ARM: dump stats and process info on context switches 2012-11-02 11:32:01 -05:00
SConscript mem: Add tracing support in the communication monitor 2013-01-07 13:05:37 -05:00
se_translating_port_proxy.cc SETranslatingPortProxy: fix bug in tryReadString() 2012-08-06 16:57:11 -07:00
se_translating_port_proxy.hh MEM: Introduce the master/slave port sub-classes in C++ 2012-03-30 09:40:11 -04:00
simple_dram.cc mem: Fix missing delete of packet in DRAM access 2013-03-18 05:22:45 -04:00
simple_dram.hh mem: SimpleDRAM variable naming and whitespace fixes 2013-03-01 13:20:24 -05:00
simple_mem.cc mem: Enforce strict use of busFirst- and busLastWordTime 2013-02-19 05:56:06 -05:00
simple_mem.hh mem: fix use after free issue in memories until 4-phase work complete. 2012-11-02 11:50:16 -05:00
SimpleDRAM.py mem: Add a method to build multi-channel DRAM configurations 2013-03-01 13:20:32 -05:00
SimpleMemory.py sim: Include object header files in SWIG interfaces 2012-11-02 11:32:01 -05:00
tport.cc Port: Extend the QueuedPort interface and use where appropriate 2012-08-22 11:39:56 -04:00
tport.hh Port: Hide the queue implementation in SimpleTimingPort 2012-07-09 12:35:42 -04:00