gem5/kern/kernel_stats.hh
Kevin Lim 61d95de4c8 Large update of several parts of my code. The most notable change is the inclusion of a full-fledged load/store queue. At the moment it still has some issues running, but most of the code is hopefully close to the final version.
SConscript:
arch/isa_parser.py:
cpu/base_dyn_inst.cc:
    Remove OOO CPU stuff.
arch/alpha/faults.hh:
    Add fake memory fault.  This will be removed eventually.
arch/alpha/isa_desc:
    Change EA comp and Mem accessor to be const StaticInstPtrs.
cpu/base_dyn_inst.hh:
    Update read/write calls to use load queue and store queue indices.
cpu/beta_cpu/alpha_dyn_inst.hh:
    Change to const StaticInst in the register accessors.
cpu/beta_cpu/alpha_dyn_inst_impl.hh:
    Update syscall code with thread numbers.
cpu/beta_cpu/alpha_full_cpu.hh:
    Alter some of the full system code so it will compile without errors.
cpu/beta_cpu/alpha_full_cpu_builder.cc:
    Created a DerivAlphaFullCPU class so I can instantiate different CPUs that have different template parameters.
cpu/beta_cpu/alpha_full_cpu_impl.hh:
    Update some of the full system code so it compiles.
cpu/beta_cpu/alpha_params.hh:
cpu/beta_cpu/fetch_impl.hh:
    Remove asid.
cpu/beta_cpu/comm.hh:
    Remove global history field.
cpu/beta_cpu/commit.hh:
    Comment out rename map.
cpu/beta_cpu/commit_impl.hh:
    Update some of the full system code so it compiles.  Also change it so that it handles memory instructions properly.
cpu/beta_cpu/cpu_policy.hh:
    Removed IQ from the IEW template parameter to make it more uniform.
cpu/beta_cpu/decode.hh:
    Add debug function.
cpu/beta_cpu/decode_impl.hh:
    Slight updates for decode in the case where it causes a squash.
cpu/beta_cpu/fetch.hh:
cpu/beta_cpu/rob.hh:
    Comment out unneccessary code.
cpu/beta_cpu/full_cpu.cc:
    Changed some of the full system code so it compiles.  Updated exec contexts and so forth to hopefully make multithreading easier.
cpu/beta_cpu/full_cpu.hh:
    Updated some of the full system code to make it compile.
cpu/beta_cpu/iew.cc:
    Removed IQ from template parameter to IEW.
cpu/beta_cpu/iew.hh:
    Removed IQ from template parameter to IEW. Updated IEW to recognize the Load/Store queue.
cpu/beta_cpu/iew_impl.hh:
    New handling of memory instructions through the Load/Store queue.
cpu/beta_cpu/inst_queue.hh:
    Updated comment.
cpu/beta_cpu/inst_queue_impl.hh:
    Slightly different handling of memory instructions due to Load/Store queue.
cpu/beta_cpu/regfile.hh:
    Updated full system code so it compiles.
cpu/beta_cpu/rob_impl.hh:
    Moved some code around; no major functional changes.
cpu/ooo_cpu/ooo_cpu.hh:
    Slight updates to OOO CPU; still does not work.
cpu/static_inst.hh:
    Remove OOO CPU stuff.  Change ea comp and mem acc to return const StaticInst.
kern/kernel_stats.hh:
    Extra forward declares added due to compile error.

--HG--
extra : convert_revision : 594a7cdbe57f6c2bda7d08856fcd864604a6238e
2005-05-03 10:56:47 -04:00

197 lines
5.1 KiB
C++

/*
* Copyright (c) 2003 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __KERNEL_STATS_HH__
#define __KERNEL_STATS_HH__
#include <map>
#include <stack>
#include <string>
#include <vector>
#include "base/statistics.hh"
#include "sim/serialize.hh"
#include "targetarch/isa_traits.hh"
class BaseCPU;
class ExecContext;
class FnEvent;
// What does kernel stats expect is included?
class StaticInstBase;
class System;
enum Fault;
namespace Kernel {
enum cpu_mode { kernel, user, idle, interrupt, cpu_mode_num };
extern const char *modestr[];
class Binning
{
private:
std::string myname;
System *system;
private:
// lisa's binning stuff
struct fnCall
{
Stats::MainBin *myBin;
std::string name;
};
struct SWContext
{
Counter calls;
std::stack<fnCall *> callStack;
};
std::map<const std::string, Stats::MainBin *> fnBins;
std::map<const Addr, SWContext *> swCtxMap;
std::multimap<const std::string, std::string> callerMap;
void populateMap(std::string caller, std::string callee);
std::vector<FnEvent *> fnEvents;
Stats::Scalar<> fnCalls;
Stats::MainBin *getBin(const std::string &name);
bool findCaller(std::string, std::string) const;
SWContext *findContext(Addr pcb);
bool addContext(Addr pcb, SWContext *ctx)
{
return (swCtxMap.insert(std::make_pair(pcb, ctx))).second;
}
void remContext(Addr pcb)
{
swCtxMap.erase(pcb);
}
void dumpState() const;
SWContext *swctx;
std::vector<std::string> binned_fns;
private:
Stats::MainBin *modeBin[cpu_mode_num];
public:
const bool bin;
const bool fnbin;
cpu_mode themode;
void palSwapContext(ExecContext *xc);
void execute(ExecContext *xc, const StaticInstBase *inst);
void call(ExecContext *xc, Stats::MainBin *myBin);
void changeMode(cpu_mode mode);
public:
Binning(System *sys);
virtual ~Binning();
const std::string name() const { return myname; }
void regStats(const std::string &name);
public:
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string &section);
};
class Statistics : public Serializable
{
friend class Binning;
private:
std::string myname;
ExecContext *xc;
Addr idleProcess;
cpu_mode themode;
Tick lastModeTick;
bool bin_int;
void changeMode(cpu_mode newmode);
private:
Stats::Scalar<> _arm;
Stats::Scalar<> _quiesce;
Stats::Scalar<> _ivlb;
Stats::Scalar<> _ivle;
Stats::Scalar<> _hwrei;
Stats::Vector<> _iplCount;
Stats::Vector<> _iplGood;
Stats::Vector<> _iplTicks;
Stats::Formula _iplUsed;
Stats::Vector<> _callpal;
Stats::Vector<> _syscall;
Stats::Vector<> _faults;
Stats::Vector<> _mode;
Stats::Vector<> _modeGood;
Stats::Formula _modeFraction;
Stats::Vector<> _modeTicks;
Stats::Scalar<> _swap_context;
private:
int iplLast;
Tick iplLastTick;
public:
Statistics(ExecContext *context);
const std::string name() const { return myname; }
void regStats(const std::string &name);
public:
void arm() { _arm++; }
void quiesce() { _quiesce++; }
void ivlb() { _ivlb++; }
void ivle() { _ivle++; }
void hwrei() { _hwrei++; }
void fault(Fault fault) { _faults[fault]++; }
void swpipl(int ipl);
void mode(cpu_mode newmode);
void context(Addr oldpcbb, Addr newpcbb);
void callpal(int code);
void setIdleProcess(Addr idle);
public:
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string &section);
};
/* end namespace Kernel */ }
#endif // __KERNEL_STATS_HH__