13c005a8af
--HG-- rename : cpu/base_cpu.cc => cpu/base.cc rename : cpu/base_cpu.hh => cpu/base.hh rename : cpu/beta_cpu/2bit_local_pred.cc => cpu/o3/2bit_local_pred.cc rename : cpu/beta_cpu/2bit_local_pred.hh => cpu/o3/2bit_local_pred.hh rename : cpu/beta_cpu/alpha_full_cpu.cc => cpu/o3/alpha_cpu.cc rename : cpu/beta_cpu/alpha_full_cpu.hh => cpu/o3/alpha_cpu.hh rename : cpu/beta_cpu/alpha_full_cpu_builder.cc => cpu/o3/alpha_cpu_builder.cc rename : cpu/beta_cpu/alpha_full_cpu_impl.hh => cpu/o3/alpha_cpu_impl.hh rename : cpu/beta_cpu/alpha_dyn_inst.cc => cpu/o3/alpha_dyn_inst.cc rename : cpu/beta_cpu/alpha_dyn_inst.hh => cpu/o3/alpha_dyn_inst.hh rename : cpu/beta_cpu/alpha_dyn_inst_impl.hh => cpu/o3/alpha_dyn_inst_impl.hh rename : cpu/beta_cpu/alpha_impl.hh => cpu/o3/alpha_impl.hh rename : cpu/beta_cpu/alpha_params.hh => cpu/o3/alpha_params.hh rename : cpu/beta_cpu/bpred_unit.cc => cpu/o3/bpred_unit.cc rename : cpu/beta_cpu/bpred_unit.hh => cpu/o3/bpred_unit.hh rename : cpu/beta_cpu/bpred_unit_impl.hh => cpu/o3/bpred_unit_impl.hh rename : cpu/beta_cpu/btb.cc => cpu/o3/btb.cc rename : cpu/beta_cpu/btb.hh => cpu/o3/btb.hh rename : cpu/beta_cpu/comm.hh => cpu/o3/comm.hh rename : cpu/beta_cpu/commit.cc => cpu/o3/commit.cc rename : cpu/beta_cpu/commit.hh => cpu/o3/commit.hh rename : cpu/beta_cpu/commit_impl.hh => cpu/o3/commit_impl.hh rename : cpu/beta_cpu/full_cpu.cc => cpu/o3/cpu.cc rename : cpu/beta_cpu/full_cpu.hh => cpu/o3/cpu.hh rename : cpu/beta_cpu/cpu_policy.hh => cpu/o3/cpu_policy.hh rename : cpu/beta_cpu/decode.cc => cpu/o3/decode.cc rename : cpu/beta_cpu/decode.hh => cpu/o3/decode.hh rename : cpu/beta_cpu/decode_impl.hh => cpu/o3/decode_impl.hh rename : cpu/beta_cpu/fetch.cc => cpu/o3/fetch.cc rename : cpu/beta_cpu/fetch.hh => cpu/o3/fetch.hh rename : cpu/beta_cpu/fetch_impl.hh => cpu/o3/fetch_impl.hh rename : cpu/beta_cpu/free_list.cc => cpu/o3/free_list.cc rename : cpu/beta_cpu/free_list.hh => cpu/o3/free_list.hh rename : cpu/beta_cpu/iew.cc => cpu/o3/iew.cc rename : cpu/beta_cpu/iew.hh => cpu/o3/iew.hh rename : cpu/beta_cpu/iew_impl.hh => cpu/o3/iew_impl.hh rename : cpu/beta_cpu/inst_queue.cc => cpu/o3/inst_queue.cc rename : cpu/beta_cpu/inst_queue.hh => cpu/o3/inst_queue.hh rename : cpu/beta_cpu/inst_queue_impl.hh => cpu/o3/inst_queue_impl.hh rename : cpu/beta_cpu/mem_dep_unit.cc => cpu/o3/mem_dep_unit.cc rename : cpu/beta_cpu/mem_dep_unit.hh => cpu/o3/mem_dep_unit.hh rename : cpu/beta_cpu/mem_dep_unit_impl.hh => cpu/o3/mem_dep_unit_impl.hh rename : cpu/beta_cpu/ras.cc => cpu/o3/ras.cc rename : cpu/beta_cpu/ras.hh => cpu/o3/ras.hh rename : cpu/beta_cpu/regfile.hh => cpu/o3/regfile.hh rename : cpu/beta_cpu/rename.cc => cpu/o3/rename.cc rename : cpu/beta_cpu/rename.hh => cpu/o3/rename.hh rename : cpu/beta_cpu/rename_impl.hh => cpu/o3/rename_impl.hh rename : cpu/beta_cpu/rename_map.cc => cpu/o3/rename_map.cc rename : cpu/beta_cpu/rename_map.hh => cpu/o3/rename_map.hh rename : cpu/beta_cpu/rob.cc => cpu/o3/rob.cc rename : cpu/beta_cpu/rob.hh => cpu/o3/rob.hh rename : cpu/beta_cpu/rob_impl.hh => cpu/o3/rob_impl.hh rename : cpu/beta_cpu/sat_counter.cc => cpu/o3/sat_counter.cc rename : cpu/beta_cpu/sat_counter.hh => cpu/o3/sat_counter.hh rename : cpu/beta_cpu/store_set.cc => cpu/o3/store_set.cc rename : cpu/beta_cpu/store_set.hh => cpu/o3/store_set.hh rename : cpu/beta_cpu/tournament_pred.cc => cpu/o3/tournament_pred.cc rename : cpu/beta_cpu/tournament_pred.hh => cpu/o3/tournament_pred.hh rename : cpu/ooo_cpu/ooo_cpu.cc => cpu/ozone/cpu.cc rename : cpu/ooo_cpu/ooo_cpu.hh => cpu/ozone/cpu.hh rename : cpu/ooo_cpu/ooo_impl.hh => cpu/ozone/cpu_impl.hh rename : cpu/ooo_cpu/ea_list.cc => cpu/ozone/ea_list.cc rename : cpu/ooo_cpu/ea_list.hh => cpu/ozone/ea_list.hh rename : cpu/simple_cpu/simple_cpu.cc => cpu/simple/cpu.cc rename : cpu/simple_cpu/simple_cpu.hh => cpu/simple/cpu.hh rename : cpu/full_cpu/smt.hh => cpu/smt.hh rename : cpu/full_cpu/op_class.hh => encumbered/cpu/full/op_class.hh extra : convert_revision : c4a891d8d6d3e0e9e5ea56be47d851da44d8c032
156 lines
4.4 KiB
C++
156 lines
4.4 KiB
C++
/*
|
|
* Copyright (c) 2002-2004 The Regents of The University of Michigan
|
|
* All rights reserved.
|
|
*
|
|
* Redistribution and use in source and binary forms, with or without
|
|
* modification, are permitted provided that the following conditions are
|
|
* met: redistributions of source code must retain the above copyright
|
|
* notice, this list of conditions and the following disclaimer;
|
|
* redistributions in binary form must reproduce the above copyright
|
|
* notice, this list of conditions and the following disclaimer in the
|
|
* documentation and/or other materials provided with the distribution;
|
|
* neither the name of the copyright holders nor the names of its
|
|
* contributors may be used to endorse or promote products derived from
|
|
* this software without specific prior written permission.
|
|
*
|
|
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
|
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
|
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
|
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
|
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
|
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
|
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
|
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
|
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
|
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
|
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
|
*/
|
|
|
|
#ifndef __CPU_MEMTEST_MEMTEST_HH__
|
|
#define __CPU_MEMTEST_MEMTEST_HH__
|
|
|
|
#include <set>
|
|
|
|
#include "base/statistics.hh"
|
|
#include "mem/functional/functional.hh"
|
|
#include "mem/mem_interface.hh"
|
|
#include "sim/eventq.hh"
|
|
#include "sim/sim_exit.hh"
|
|
#include "sim/sim_object.hh"
|
|
#include "sim/stats.hh"
|
|
|
|
class ExecContext;
|
|
class MemTest : public SimObject
|
|
{
|
|
public:
|
|
|
|
MemTest(const std::string &name,
|
|
MemInterface *_cache_interface,
|
|
FunctionalMemory *main_mem,
|
|
FunctionalMemory *check_mem,
|
|
unsigned _memorySize,
|
|
unsigned _percentReads,
|
|
unsigned _percentCopies,
|
|
unsigned _percentUncacheable,
|
|
unsigned _progressInterval,
|
|
unsigned _percentSourceUnaligned,
|
|
unsigned _percentDestUnaligned,
|
|
Addr _traceAddr,
|
|
Counter _max_loads);
|
|
|
|
// register statistics
|
|
virtual void regStats();
|
|
|
|
inline Tick cycles(int numCycles) const { return numCycles; }
|
|
|
|
// main simulation loop (one cycle)
|
|
void tick();
|
|
|
|
protected:
|
|
class TickEvent : public Event
|
|
{
|
|
private:
|
|
MemTest *cpu;
|
|
public:
|
|
TickEvent(MemTest *c)
|
|
: Event(&mainEventQueue, CPU_Tick_Pri), cpu(c) {}
|
|
void process() {cpu->tick();}
|
|
virtual const char *description() { return "tick event"; }
|
|
};
|
|
|
|
TickEvent tickEvent;
|
|
|
|
MemInterface *cacheInterface;
|
|
FunctionalMemory *mainMem;
|
|
FunctionalMemory *checkMem;
|
|
ExecContext *xc;
|
|
|
|
unsigned size; // size of testing memory region
|
|
|
|
unsigned percentReads; // target percentage of read accesses
|
|
unsigned percentCopies; // target percentage of copy accesses
|
|
unsigned percentUncacheable;
|
|
|
|
int id;
|
|
|
|
std::set<unsigned> outstandingAddrs;
|
|
|
|
unsigned blockSize;
|
|
|
|
Addr blockAddrMask;
|
|
|
|
Addr blockAddr(Addr addr)
|
|
{
|
|
return (addr & ~blockAddrMask);
|
|
}
|
|
|
|
Addr traceBlockAddr;
|
|
|
|
Addr baseAddr1; // fix this to option
|
|
Addr baseAddr2; // fix this to option
|
|
Addr uncacheAddr;
|
|
|
|
unsigned progressInterval; // frequency of progress reports
|
|
Tick nextProgressMessage; // access # for next progress report
|
|
|
|
unsigned percentSourceUnaligned;
|
|
unsigned percentDestUnaligned;
|
|
|
|
Tick noResponseCycles;
|
|
|
|
uint64_t numReads;
|
|
uint64_t maxLoads;
|
|
Stats::Scalar<> numReadsStat;
|
|
Stats::Scalar<> numWritesStat;
|
|
Stats::Scalar<> numCopiesStat;
|
|
|
|
// called by MemCompleteEvent::process()
|
|
void completeRequest(MemReqPtr &req, uint8_t *data);
|
|
|
|
friend class MemCompleteEvent;
|
|
};
|
|
|
|
|
|
class MemCompleteEvent : public Event
|
|
{
|
|
MemReqPtr req;
|
|
uint8_t *data;
|
|
MemTest *tester;
|
|
|
|
public:
|
|
|
|
MemCompleteEvent(MemReqPtr &_req, uint8_t *_data, MemTest *_tester)
|
|
: Event(&mainEventQueue),
|
|
req(_req), data(_data), tester(_tester)
|
|
{
|
|
}
|
|
|
|
void process();
|
|
|
|
virtual const char *description();
|
|
};
|
|
|
|
#endif // __CPU_MEMTEST_MEMTEST_HH__
|
|
|
|
|
|
|