2f316082e4
arch/alpha/alpha_linux_process.cc: arch/alpha/alpha_linux_process.hh: arch/alpha/alpha_memory.cc: arch/alpha/alpha_memory.hh: arch/alpha/alpha_tru64_process.cc: arch/alpha/alpha_tru64_process.hh: arch/alpha/aout_machdep.h: arch/alpha/arguments.cc: arch/alpha/arguments.hh: arch/alpha/faults.cc: arch/alpha/faults.hh: arch/alpha/isa_traits.hh: arch/alpha/osfpal.cc: arch/alpha/osfpal.hh: arch/alpha/pseudo_inst.cc: arch/alpha/pseudo_inst.hh: arch/alpha/vptr.hh: arch/alpha/vtophys.cc: arch/alpha/vtophys.hh: base/bitfield.hh: base/callback.hh: base/circlebuf.cc: base/circlebuf.hh: base/compression/lzss_compression.cc: base/compression/lzss_compression.hh: base/compression/null_compression.hh: base/cprintf.cc: base/cprintf.hh: base/cprintf_formats.hh: base/date.cc: base/dbl_list.hh: base/endian.hh: base/fast_alloc.cc: base/fast_alloc.hh: base/fifo_buffer.cc: base/fifo_buffer.hh: base/hashmap.hh: base/hostinfo.cc: base/hostinfo.hh: base/hybrid_pred.cc: base/hybrid_pred.hh: base/inet.cc: base/inet.hh: base/inifile.cc: base/inifile.hh: base/intmath.cc: base/intmath.hh: base/loader/aout_object.cc: base/loader/aout_object.hh: base/loader/ecoff_object.cc: base/loader/ecoff_object.hh: base/loader/elf_object.cc: base/loader/elf_object.hh: base/loader/object_file.cc: base/loader/object_file.hh: base/loader/symtab.cc: base/loader/symtab.hh: base/misc.cc: base/misc.hh: base/mod_num.hh: base/mysql.cc: base/mysql.hh: base/pollevent.cc: base/pollevent.hh: base/predictor.hh: base/random.cc: base/random.hh: base/range.cc: base/range.hh: base/refcnt.hh: base/remote_gdb.cc: base/remote_gdb.hh: base/res_list.hh: base/sat_counter.cc: base/sat_counter.hh: base/sched_list.hh: base/socket.cc: base/socket.hh: base/statistics.cc: base/statistics.hh: base/stats/events.cc: base/stats/events.hh: base/stats/flags.hh: base/stats/mysql.cc: base/stats/mysql.hh: base/stats/mysql_run.hh: base/stats/output.hh: base/stats/statdb.cc: base/stats/statdb.hh: base/stats/text.cc: base/stats/text.hh: base/stats/types.hh: base/stats/visit.cc: base/stats/visit.hh: base/str.cc: base/str.hh: base/time.cc: base/time.hh: base/trace.cc: base/trace.hh: base/userinfo.cc: base/userinfo.hh: cpu/base_cpu.cc: cpu/base_cpu.hh: cpu/exec_context.cc: cpu/exec_context.hh: cpu/exetrace.cc: cpu/exetrace.hh: cpu/full_cpu/op_class.hh: cpu/full_cpu/smt.hh: cpu/inst_seq.hh: cpu/intr_control.cc: cpu/intr_control.hh: cpu/memtest/memtest.cc: cpu/memtest/memtest.hh: cpu/pc_event.cc: cpu/pc_event.hh: cpu/simple_cpu/simple_cpu.cc: cpu/simple_cpu/simple_cpu.hh: cpu/static_inst.cc: cpu/static_inst.hh: dev/alpha_console.cc: dev/alpha_console.hh: dev/baddev.cc: dev/baddev.hh: dev/disk_image.cc: dev/disk_image.hh: dev/etherbus.cc: dev/etherbus.hh: dev/etherdump.cc: dev/etherdump.hh: dev/etherint.cc: dev/etherint.hh: dev/etherlink.cc: dev/etherlink.hh: dev/etherpkt.cc: dev/etherpkt.hh: dev/ethertap.cc: dev/ethertap.hh: dev/ide_ctrl.cc: dev/ide_ctrl.hh: dev/ide_disk.cc: dev/ide_disk.hh: dev/io_device.cc: dev/io_device.hh: dev/ns_gige.cc: dev/ns_gige.hh: dev/ns_gige_reg.h: dev/pciconfigall.cc: dev/pciconfigall.hh: dev/pcidev.cc: dev/pcidev.hh: dev/pcireg.h: dev/platform.cc: dev/platform.hh: dev/simple_disk.cc: dev/simple_disk.hh: dev/tsunami.cc: dev/tsunami.hh: dev/tsunami_cchip.cc: dev/tsunami_cchip.hh: dev/tsunami_io.cc: dev/tsunami_io.hh: dev/tsunami_pchip.cc: dev/tsunami_pchip.hh: dev/tsunami_uart.hh: dev/tsunamireg.h: docs/stl.hh: kern/linux/linux.hh: kern/linux/linux_syscalls.cc: kern/linux/linux_syscalls.hh: kern/linux/linux_system.cc: kern/linux/linux_system.hh: kern/system_events.cc: kern/system_events.hh: kern/tru64/dump_mbuf.cc: kern/tru64/dump_mbuf.hh: kern/tru64/mbuf.hh: kern/tru64/printf.cc: kern/tru64/printf.hh: kern/tru64/tru64.hh: kern/tru64/tru64_events.cc: kern/tru64/tru64_events.hh: kern/tru64/tru64_syscalls.cc: kern/tru64/tru64_syscalls.hh: kern/tru64/tru64_system.cc: kern/tru64/tru64_system.hh: sim/async.hh: sim/builder.cc: sim/builder.hh: sim/debug.cc: sim/debug.hh: sim/eventq.cc: sim/eventq.hh: sim/host.hh: sim/main.cc: sim/param.cc: sim/param.hh: sim/process.cc: sim/process.hh: sim/serialize.cc: sim/serialize.hh: sim/sim_events.cc: sim/sim_events.hh: sim/sim_exit.hh: sim/sim_object.cc: sim/sim_object.hh: sim/stat_control.cc: sim/stat_control.hh: sim/stats.hh: sim/syscall_emul.cc: sim/syscall_emul.hh: sim/system.cc: sim/system.hh: sim/universe.cc: test/bitvectest.cc: test/circletest.cc: test/cprintftest.cc: test/initest.cc: test/lru_test.cc: test/nmtest.cc: test/offtest.cc: test/paramtest.cc: test/rangetest.cc: test/sized_test.cc: test/stattest.cc: test/strnumtest.cc: test/symtest.cc: test/tokentest.cc: test/tracetest.cc: util/m5/m5.c: util/m5/m5op.h: util/tap/tap.cc: Updated Copyright dev/console.cc: dev/console.hh: This code isn't ours, and shouldn't have our copyright --HG-- extra : convert_revision : 598f2e5eab5d5d3de2c1e862b389086e3212f7c4
268 lines
7.7 KiB
C++
268 lines
7.7 KiB
C++
/*
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* Copyright (c) 2002-2004 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <cassert>
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#include <iomanip>
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#include <iostream>
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#include <sstream>
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#include "base/cprintf.hh"
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using namespace std;
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namespace cp {
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ArgList::~ArgList()
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{
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while (!objects.empty()) {
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delete objects.front();
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objects.pop_front();
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}
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}
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void
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ArgList::dump(const string &format)
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{
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list_t::iterator iter = objects.begin();
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list_t::iterator end = objects.end();
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const char *p = format.c_str();
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stream->fill(' ');
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stream->flags((ios::fmtflags)0);
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while (*p) {
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switch (*p) {
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case '%': {
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if (p[1] == '%') {
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*stream << '%';
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p += 2;
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continue;
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}
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Format fmt;
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bool done = false;
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bool end_number = false;
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bool have_precision = false;
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int number = 0;
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while (!done) {
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++p;
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if (*p >= '0' && *p <= '9') {
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if (end_number)
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continue;
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} else if (number > 0)
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end_number = true;
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switch (*p) {
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case 's':
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fmt.format = Format::string;
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done = true;
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break;
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case 'c':
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fmt.format = Format::character;
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done = true;
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break;
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case 'l':
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continue;
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case 'p':
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fmt.format = Format::integer;
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fmt.base = Format::hex;
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fmt.alternate_form = true;
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done = true;
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break;
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case 'X':
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fmt.uppercase = true;
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case 'x':
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fmt.base = Format::hex;
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fmt.format = Format::integer;
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done = true;
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break;
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case 'o':
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fmt.base = Format::oct;
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fmt.format = Format::integer;
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done = true;
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break;
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case 'd':
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case 'i':
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case 'u':
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fmt.format = Format::integer;
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done = true;
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break;
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case 'G':
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fmt.uppercase = true;
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case 'g':
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fmt.format = Format::floating;
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fmt.float_format = Format::best;
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done = true;
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break;
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case 'E':
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fmt.uppercase = true;
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case 'e':
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fmt.format = Format::floating;
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fmt.float_format = Format::scientific;
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done = true;
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break;
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case 'f':
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fmt.format = Format::floating;
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fmt.float_format = Format::fixed;
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done = true;
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break;
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case 'n':
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*stream << "we don't do %n!!!\n";
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done = true;
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break;
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case '#':
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fmt.alternate_form = true;
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break;
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case '-':
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fmt.flush_left = true;
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break;
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case '+':
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fmt.print_sign = true;
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break;
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case ' ':
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fmt.blank_space = true;
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break;
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case '.':
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fmt.width = number;
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fmt.precision = 0;
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have_precision = true;
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number = 0;
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end_number = false;
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break;
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case '0':
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if (number == 0) {
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fmt.fill_zero = true;
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break;
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}
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case '1':
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case '2':
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case '3':
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case '4':
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case '5':
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case '6':
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case '7':
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case '8':
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case '9':
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number = number * 10 + (*p - '0');
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break;
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case '%':
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assert("we shouldn't get here");
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break;
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default:
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done = true;
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break;
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}
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if (end_number) {
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if (have_precision)
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fmt.precision = number;
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else
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fmt.width = number;
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end_number = false;
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number = 0;
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}
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}
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if (iter != end)
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{
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ios::fmtflags saved_flags = stream->flags();
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char old_fill = stream->fill();
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int old_precision = stream->precision();
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(*iter)->process(*stream, fmt);
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stream->flags(saved_flags);
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stream->fill(old_fill);
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stream->precision(old_precision);
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++iter;
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} else {
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*stream << "<missing arg for format>";
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}
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++p;
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}
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break;
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case '\n':
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*stream << endl;
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++p;
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break;
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case '\r':
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++p;
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if (*p != '\n')
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*stream << endl;
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break;
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default: {
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size_t len = strcspn(p, "%\n\r\0");
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stream->write(p, len);
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p += len;
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}
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break;
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}
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}
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while (iter != end) {
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*stream << "<extra arg>";
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++iter;
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}
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}
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string
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ArgList::dumpToString(const string &format)
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{
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stringstream ss;
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dump(ss, format);
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return ss.str();
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}
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}
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