312 lines
7.6 KiB
C++
312 lines
7.6 KiB
C++
/*
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* Copyright (c) 2008 The Hewlett-Packard Development Company
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* All rights reserved.
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#ifndef __ARCH_X86_BIOS_INTELMP_HH__
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#define __ARCH_X86_BIOS_INTELMP_HH__
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#include <string>
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#include <vector>
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#include "base/bitfield.hh"
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#include "enums/X86IntelMPAddressType.hh"
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#include "enums/X86IntelMPInterruptType.hh"
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#include "enums/X86IntelMPPolarity.hh"
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#include "enums/X86IntelMPRangeList.hh"
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#include "enums/X86IntelMPTriggerMode.hh"
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#include "sim/sim_object.hh"
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class FunctionalPort;
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// Config entry types
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class X86IntelMPBaseConfigEntryParams;
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class X86IntelMPExtConfigEntryParams;
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// General table structures
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class X86IntelMPConfigTableParams;
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class X86IntelMPFloatingPointerParams;
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// Base entry types
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class X86IntelMPBusParams;
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class X86IntelMPIOAPICParams;
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class X86IntelMPIOIntAssignmentParams;
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class X86IntelMPLocalIntAssignmentParams;
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class X86IntelMPProcessorParams;
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// Extended entry types
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class X86IntelMPAddrSpaceMappingParams;
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class X86IntelMPBusHierarchyParams;
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class X86IntelMPCompatAddrSpaceModParams;
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namespace X86ISA
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{
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namespace IntelMP
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{
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class FloatingPointer : public SimObject
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{
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protected:
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typedef X86IntelMPFloatingPointerParams Params;
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uint32_t tableAddr;
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uint8_t specRev;
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uint8_t defaultConfig;
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bool imcrPresent;
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static const char signature[];
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public:
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Addr writeOut(FunctionalPort * port, Addr addr);
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Addr getTableAddr()
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{
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return tableAddr;
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}
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void setTableAddr(Addr addr)
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{
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tableAddr = addr;
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}
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FloatingPointer(Params * p);
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};
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class BaseConfigEntry : public SimObject
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{
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protected:
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typedef X86IntelMPBaseConfigEntryParams Params;
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uint8_t type;
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public:
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virtual Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum);
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BaseConfigEntry(Params * p, uint8_t _type);
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};
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class ExtConfigEntry : public SimObject
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{
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protected:
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typedef X86IntelMPExtConfigEntryParams Params;
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uint8_t type;
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uint8_t length;
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public:
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virtual Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum);
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ExtConfigEntry(Params * p, uint8_t _type, uint8_t _length);
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};
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class ConfigTable : public SimObject
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{
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protected:
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typedef X86IntelMPConfigTableParams Params;
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static const char signature[];
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uint8_t specRev;
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std::string oemID;
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std::string productID;
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uint32_t oemTableAddr;
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uint16_t oemTableSize;
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uint32_t localApic;
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std::vector<BaseConfigEntry *> baseEntries;
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std::vector<ExtConfigEntry *> extEntries;
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public:
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Addr writeOut(FunctionalPort * port, Addr addr);
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ConfigTable(Params * p);
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};
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class Processor : public BaseConfigEntry
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{
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protected:
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typedef X86IntelMPProcessorParams Params;
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uint8_t localApicID;
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uint8_t localApicVersion;
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uint8_t cpuFlags;
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uint32_t cpuSignature;
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uint32_t featureFlags;
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public:
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Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum);
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Processor(Params * p);
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};
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class Bus : public BaseConfigEntry
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{
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protected:
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typedef X86IntelMPBusParams Params;
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uint8_t busID;
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std::string busType;
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public:
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Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum);
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Bus(Params * p);
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};
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class IOAPIC : public BaseConfigEntry
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{
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protected:
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typedef X86IntelMPIOAPICParams Params;
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uint8_t id;
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uint8_t version;
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uint8_t flags;
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uint32_t address;
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public:
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Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum);
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IOAPIC(Params * p);
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};
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class IntAssignment : public BaseConfigEntry
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{
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protected:
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uint8_t interruptType;
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uint16_t flags;
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uint8_t sourceBusID;
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uint8_t sourceBusIRQ;
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uint8_t destApicID;
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uint8_t destApicIntIn;
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public:
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Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum);
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IntAssignment(X86IntelMPBaseConfigEntryParams * p,
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Enums::X86IntelMPInterruptType _interruptType,
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Enums::X86IntelMPPolarity polarity,
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Enums::X86IntelMPTriggerMode trigger,
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uint8_t _type,
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uint8_t _sourceBusID, uint8_t _sourceBusIRQ,
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uint8_t _destApicID, uint8_t _destApicIntIn) :
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BaseConfigEntry(p, _type),
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interruptType(_interruptType), flags(0),
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sourceBusID(_sourceBusID), sourceBusIRQ(_sourceBusIRQ),
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destApicID(_destApicID), destApicIntIn(_destApicIntIn)
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{
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replaceBits(flags, 0, 1, polarity);
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replaceBits(flags, 2, 3, trigger);
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}
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};
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class IOIntAssignment : public IntAssignment
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{
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protected:
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typedef X86IntelMPIOIntAssignmentParams Params;
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public:
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IOIntAssignment(Params * p);
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};
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class LocalIntAssignment : public IntAssignment
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{
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protected:
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typedef X86IntelMPLocalIntAssignmentParams Params;
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public:
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LocalIntAssignment(Params * p);
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};
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class AddrSpaceMapping : public ExtConfigEntry
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{
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protected:
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typedef X86IntelMPAddrSpaceMappingParams Params;
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uint8_t busID;
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uint8_t addrType;
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uint64_t addr;
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uint64_t addrLength;
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public:
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Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum);
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AddrSpaceMapping(Params * p);
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};
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class BusHierarchy : public ExtConfigEntry
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{
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protected:
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typedef X86IntelMPBusHierarchyParams Params;
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uint8_t busID;
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uint8_t info;
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uint8_t parentBus;
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public:
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Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum);
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BusHierarchy(Params * p);
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};
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class CompatAddrSpaceMod : public ExtConfigEntry
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{
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protected:
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typedef X86IntelMPCompatAddrSpaceModParams Params;
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uint8_t busID;
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uint8_t mod;
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uint32_t rangeList;
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public:
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Addr writeOut(FunctionalPort * port, Addr addr, uint8_t &checkSum);
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CompatAddrSpaceMod(Params * p);
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};
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} //IntelMP
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} //X86ISA
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#endif
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