102 lines
3.3 KiB
C++
102 lines
3.3 KiB
C++
/*
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* Copyright (c) 2003-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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* Ali Saidi
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*/
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#ifndef __ARCH_SPARC_ISA_TRAITS_HH__
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#define __ARCH_SPARC_ISA_TRAITS_HH__
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#include "arch/sparc/sparc_traits.hh"
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#include "arch/sparc/types.hh"
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#include "base/types.hh"
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#include "config/full_system.hh"
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class StaticInstPtr;
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namespace BigEndianGuest {}
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namespace SparcISA
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{
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const int MachineBytes = 8;
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// This makes sure the big endian versions of certain functions are used.
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using namespace BigEndianGuest;
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// SPARC has a delay slot
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#define ISA_HAS_DELAY_SLOT 1
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// SPARC NOP (sethi %(hi(0), g0)
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const MachInst NoopMachInst = 0x01000000;
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// 8K. This value is implmentation specific; and should probably
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// be somewhere else.
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const int LogVMPageSize = 13;
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const int VMPageSize = (1 << LogVMPageSize);
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// real address virtual mapping
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// sort of like alpha super page, but less frequently used
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const Addr SegKPMEnd = ULL(0xfffffffc00000000);
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const Addr SegKPMBase = ULL(0xfffffac000000000);
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// Why does both the previous set of constants and this one exist?
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const int PageShift = 13;
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const int PageBytes = 1ULL << PageShift;
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const int BranchPredAddrShiftAmt = 2;
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StaticInstPtr decodeInst(ExtMachInst);
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/////////// TLB Stuff ////////////
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const Addr StartVAddrHole = ULL(0x0000800000000000);
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const Addr EndVAddrHole = ULL(0xFFFF7FFFFFFFFFFF);
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const Addr VAddrAMask = ULL(0xFFFFFFFF);
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const Addr PAddrImplMask = ULL(0x000000FFFFFFFFFF);
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const Addr BytesInPageMask = ULL(0x1FFF);
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#if FULL_SYSTEM
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enum InterruptTypes
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{
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IT_TRAP_LEVEL_ZERO,
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IT_HINTP,
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IT_INT_VEC,
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IT_CPU_MONDO,
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IT_DEV_MONDO,
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IT_RES_ERROR,
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IT_SOFT_INT,
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NumInterruptTypes
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};
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#endif
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// Memory accesses cannot be unaligned
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const bool HasUnalignedMemAcc = false;
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}
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#endif // __ARCH_SPARC_ISA_TRAITS_HH__
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