245 lines
7.8 KiB
C++
245 lines
7.8 KiB
C++
/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Copyright (c) 2001-2005 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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*/
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#ifndef __ARCH_ARM_TLB_HH__
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#define __ARCH_ARM_TLB_HH__
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#include <map>
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#include "arch/arm/isa_traits.hh"
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#include "arch/arm/pagetable.hh"
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#include "arch/arm/utility.hh"
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#include "arch/arm/vtophys.hh"
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#include "base/statistics.hh"
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#include "mem/request.hh"
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#include "params/ArmTLB.hh"
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#include "sim/fault_fwd.hh"
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#include "sim/tlb.hh"
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class ThreadContext;
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namespace ArmISA {
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class TableWalker;
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class TLB : public BaseTLB
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{
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public:
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enum ArmFlags {
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AlignmentMask = 0x1f,
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AlignByte = 0x0,
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AlignHalfWord = 0x1,
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AlignWord = 0x3,
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AlignDoubleWord = 0x7,
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AlignQuadWord = 0xf,
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AlignOctWord = 0x1f,
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AllowUnaligned = 0x20,
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// Priv code operating as if it wasn't
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UserMode = 0x40,
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// Because zero otherwise looks like a valid setting and may be used
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// accidentally, this bit must be non-zero to show it was used on
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// purpose.
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MustBeOne = 0x80
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};
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protected:
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TlbEntry *table; // the Page Table
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int size; // TLB Size
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uint32_t _attr; // Memory attributes for last accessed TLB entry
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#if FULL_SYSTEM
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TableWalker *tableWalker;
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#endif
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/** Lookup an entry in the TLB
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* @param vpn virtual address
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* @param asn context id/address space id to use
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* @param functional if the lookup should modify state
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* @return pointer to TLB entrry if it exists
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*/
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TlbEntry *lookup(Addr vpn, uint8_t asn, bool functional = false);
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// Access Stats
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mutable Stats::Scalar instHits;
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mutable Stats::Scalar instMisses;
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mutable Stats::Scalar readHits;
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mutable Stats::Scalar readMisses;
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mutable Stats::Scalar writeHits;
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mutable Stats::Scalar writeMisses;
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mutable Stats::Scalar inserts;
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mutable Stats::Scalar flushTlb;
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mutable Stats::Scalar flushTlbMva;
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mutable Stats::Scalar flushTlbMvaAsid;
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mutable Stats::Scalar flushTlbAsid;
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mutable Stats::Scalar flushedEntries;
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mutable Stats::Scalar alignFaults;
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mutable Stats::Scalar prefetchFaults;
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mutable Stats::Scalar domainFaults;
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mutable Stats::Scalar permsFaults;
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Stats::Formula readAccesses;
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Stats::Formula writeAccesses;
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Stats::Formula instAccesses;
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Stats::Formula hits;
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Stats::Formula misses;
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Stats::Formula accesses;
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int rangeMRU; //On lookup, only move entries ahead when outside rangeMRU
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public:
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typedef ArmTLBParams Params;
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TLB(const Params *p);
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virtual ~TLB();
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int getsize() const { return size; }
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void insert(Addr vaddr, TlbEntry &pte);
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/** Reset the entire TLB */
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void flushAll();
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/** Remove any entries that match both a va and asn
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* @param mva virtual address to flush
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* @param asn contextid/asn to flush on match
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*/
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void flushMvaAsid(Addr mva, uint64_t asn);
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/** Remove any entries that match the asn
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* @param asn contextid/asn to flush on match
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*/
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void flushAsid(uint64_t asn);
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/** Remove all entries that match the va regardless of asn
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* @param mva address to flush from cache
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*/
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void flushMva(Addr mva);
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Fault trickBoxCheck(RequestPtr req, Mode mode, uint8_t domain, bool sNp);
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Fault walkTrickBoxCheck(Addr pa, Addr va, Addr sz, bool is_exec,
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bool is_write, uint8_t domain, bool sNp);
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void printTlb();
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void demapPage(Addr vaddr, uint64_t asn)
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{
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flushMvaAsid(vaddr, asn);
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}
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static bool validVirtualAddress(Addr vaddr);
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/**
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* Do a functional lookup on the TLB (for debugging)
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* and don't modify any internal state
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* @param tc thread context to get the context id from
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* @param vaddr virtual address to translate
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* @param pa returned physical address
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* @return if the translation was successful
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*/
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bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr);
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/** Accessor functions for memory attributes for last accessed TLB entry
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*/
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void
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setAttr(uint32_t attr)
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{
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_attr = attr;
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}
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uint32_t
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getAttr() const
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{
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return _attr;
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}
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#if FULL_SYSTEM
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Fault translateFs(RequestPtr req, ThreadContext *tc, Mode mode,
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Translation *translation, bool &delay, bool timing);
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#else
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Fault translateSe(RequestPtr req, ThreadContext *tc, Mode mode,
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Translation *translation, bool &delay, bool timing);
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#endif
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Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
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Fault translateTiming(RequestPtr req, ThreadContext *tc,
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Translation *translation, Mode mode);
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// Checkpointing
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void serialize(std::ostream &os);
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void unserialize(Checkpoint *cp, const std::string §ion);
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void regStats();
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// Get the port from the table walker and return it
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virtual Port *getPort();
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// Caching misc register values here.
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// Writing to misc registers needs to invalidate them.
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// translateFunctional/translateSe/translateFs checks if they are
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// invalid and call updateMiscReg if necessary.
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protected:
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SCTLR sctlr;
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bool isPriv;
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uint32_t contextId;
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PRRR prrr;
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NMRR nmrr;
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uint32_t dacr;
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bool miscRegValid;
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void updateMiscReg(ThreadContext *tc)
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{
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sctlr = tc->readMiscReg(MISCREG_SCTLR);
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CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
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isPriv = cpsr.mode != MODE_USER;
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contextId = tc->readMiscReg(MISCREG_CONTEXTIDR);
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prrr = tc->readMiscReg(MISCREG_PRRR);
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nmrr = tc->readMiscReg(MISCREG_NMRR);
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dacr = tc->readMiscReg(MISCREG_DACR);
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miscRegValid = true;
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}
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public:
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inline void invalidateMiscReg() { miscRegValid = false; }
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};
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} // namespace ArmISA
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#endif // __ARCH_ARM_TLB_HH__
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