734 lines
23 KiB
C++
734 lines
23 KiB
C++
/*
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* Copyright (c) 2010 ARM Limited
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* All rights reserved
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*
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* The license below extends only to copyright in the software and shall
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* not be construed as granting a license to any other intellectual
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* property including but not limited to intellectual property relating
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* to a hardware implementation of the functionality of the software
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* licensed hereunder. You may use the software subject to the license
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* terms below provided that you ensure that this notice is replicated
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* unmodified and in its entirety in all distributions of the software,
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* modified or unmodified, in source code or in binary form.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Ali Saidi
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*/
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#include "arch/arm/faults.hh"
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#include "arch/arm/table_walker.hh"
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#include "arch/arm/tlb.hh"
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#include "cpu/base.hh"
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#include "cpu/thread_context.hh"
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#include "dev/io_device.hh"
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#include "sim/system.hh"
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using namespace ArmISA;
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TableWalker::TableWalker(const Params *p)
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: MemObject(p), port(NULL), tlb(NULL), currState(NULL), pending(false),
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doL1DescEvent(this), doL2DescEvent(this), doProcessEvent(this)
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{
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sctlr = 0;
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}
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TableWalker::~TableWalker()
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{
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;
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}
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unsigned int
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TableWalker::drain(Event *de)
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{
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if (stateQueueL1.size() || stateQueueL2.size() || pendingQueue.size())
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{
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changeState(Draining);
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DPRINTF(Checkpoint, "TableWalker busy, wait to drain\n");
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return 1;
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}
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else
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{
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changeState(Drained);
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DPRINTF(Checkpoint, "TableWalker free, no need to drain\n");
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return 0;
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}
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}
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void
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TableWalker::resume()
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{
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MemObject::resume();
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if ((params()->sys->getMemoryMode() == Enums::timing) && currState) {
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delete currState;
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currState = NULL;
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}
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}
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Port*
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TableWalker::getPort(const std::string &if_name, int idx)
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{
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if (if_name == "port") {
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if (port != NULL)
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return port;
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System *sys = params()->sys;
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Tick minb = params()->min_backoff;
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Tick maxb = params()->max_backoff;
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port = new DmaPort(this, sys, minb, maxb);
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return port;
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}
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return NULL;
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}
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Fault
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TableWalker::walk(RequestPtr _req, ThreadContext *_tc, uint8_t _cid, TLB::Mode _mode,
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TLB::Translation *_trans, bool _timing)
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{
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if (!currState) {
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// For atomic mode, a new WalkerState instance should be only created
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// once per TLB. For timing mode, a new instance is generated for every
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// TLB miss.
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DPRINTF(TLBVerbose, "creating new instance of WalkerState\n");
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currState = new WalkerState();
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currState->tableWalker = this;
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} else if (_timing) {
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// This is a translation that was completed and then faulted again
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// because some underlying parameters that affect the translation
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// changed out from under us (e.g. asid). It will either be a
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// misprediction, in which case nothing will happen or we'll use
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// this fault to re-execute the faulting instruction which should clean
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// up everything.
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if (currState->vaddr == _req->getVaddr()) {
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return new ReExec;
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}
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panic("currState should always be empty in timing mode!\n");
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}
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currState->tc = _tc;
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currState->transState = _trans;
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currState->req = _req;
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currState->fault = NoFault;
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currState->contextId = _cid;
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currState->timing = _timing;
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currState->mode = _mode;
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/** @todo These should be cached or grabbed from cached copies in
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the TLB, all these miscreg reads are expensive */
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currState->vaddr = currState->req->getVaddr();
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currState->sctlr = currState->tc->readMiscReg(MISCREG_SCTLR);
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sctlr = currState->sctlr;
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currState->N = currState->tc->readMiscReg(MISCREG_TTBCR);
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currState->isFetch = (currState->mode == TLB::Execute);
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currState->isWrite = (currState->mode == TLB::Write);
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if (!currState->timing)
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return processWalk();
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if (pending || pendingQueue.size()) {
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pendingQueue.push_back(currState);
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currState = NULL;
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} else {
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pending = true;
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return processWalk();
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}
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return NoFault;
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}
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void
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TableWalker::processWalkWrapper()
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{
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assert(!currState);
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assert(pendingQueue.size());
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currState = pendingQueue.front();
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pendingQueue.pop_front();
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pending = true;
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processWalk();
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}
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Fault
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TableWalker::processWalk()
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{
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Addr ttbr = 0;
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// If translation isn't enabled, we shouldn't be here
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assert(currState->sctlr.m);
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DPRINTF(TLB, "Begining table walk for address %#x, TTBCR: %#x, bits:%#x\n",
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currState->vaddr, currState->N, mbits(currState->vaddr, 31,
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32-currState->N));
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if (currState->N == 0 || !mbits(currState->vaddr, 31, 32-currState->N)) {
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DPRINTF(TLB, " - Selecting TTBR0\n");
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ttbr = currState->tc->readMiscReg(MISCREG_TTBR0);
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} else {
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DPRINTF(TLB, " - Selecting TTBR1\n");
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ttbr = currState->tc->readMiscReg(MISCREG_TTBR1);
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currState->N = 0;
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}
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Addr l1desc_addr = mbits(ttbr, 31, 14-currState->N) |
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(bits(currState->vaddr,31-currState->N,20) << 2);
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DPRINTF(TLB, " - Descriptor at address %#x\n", l1desc_addr);
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// Trickbox address check
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Fault f;
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f = tlb->walkTrickBoxCheck(l1desc_addr, currState->vaddr, sizeof(uint32_t),
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currState->isFetch, currState->isWrite, 0, true);
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if (f) {
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DPRINTF(TLB, "Trickbox check caused fault on %#x\n", currState->vaddr);
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if (currState->timing) {
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pending = false;
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nextWalk(currState->tc);
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currState = NULL;
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} else {
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currState->tc = NULL;
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currState->req = NULL;
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}
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return f;
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}
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Request::Flags flag = 0;
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if (currState->sctlr.c == 0) {
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flag = Request::UNCACHEABLE;
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}
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if (currState->timing) {
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port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t),
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&doL1DescEvent, (uint8_t*)&currState->l1Desc.data,
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currState->tc->getCpuPtr()->ticks(1), flag);
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DPRINTF(TLBVerbose, "Adding to walker fifo: queue size before adding: %d\n",
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stateQueueL1.size());
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stateQueueL1.push_back(currState);
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currState = NULL;
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} else {
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port->dmaAction(MemCmd::ReadReq, l1desc_addr, sizeof(uint32_t),
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NULL, (uint8_t*)&currState->l1Desc.data,
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currState->tc->getCpuPtr()->ticks(1), flag);
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doL1Descriptor();
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f = currState->fault;
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}
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return f;
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}
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void
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TableWalker::memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr,
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uint8_t texcb, bool s)
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{
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// Note: tc and sctlr local variables are hiding tc and sctrl class
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// variables
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DPRINTF(TLBVerbose, "memAttrs texcb:%d s:%d\n", texcb, s);
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te.shareable = false; // default value
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te.nonCacheable = false;
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bool outer_shareable = false;
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if (sctlr.tre == 0 || ((sctlr.tre == 1) && (sctlr.m == 0))) {
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switch(texcb) {
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case 0: // Stongly-ordered
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te.nonCacheable = true;
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te.mtype = TlbEntry::StronglyOrdered;
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te.shareable = true;
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te.innerAttrs = 1;
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te.outerAttrs = 0;
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break;
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case 1: // Shareable Device
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te.nonCacheable = true;
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te.mtype = TlbEntry::Device;
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te.shareable = true;
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te.innerAttrs = 3;
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te.outerAttrs = 0;
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break;
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case 2: // Outer and Inner Write-Through, no Write-Allocate
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te.mtype = TlbEntry::Normal;
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te.shareable = s;
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te.innerAttrs = 6;
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te.outerAttrs = bits(texcb, 1, 0);
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break;
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case 3: // Outer and Inner Write-Back, no Write-Allocate
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te.mtype = TlbEntry::Normal;
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te.shareable = s;
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te.innerAttrs = 7;
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te.outerAttrs = bits(texcb, 1, 0);
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break;
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case 4: // Outer and Inner Non-cacheable
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te.nonCacheable = true;
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te.mtype = TlbEntry::Normal;
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te.shareable = s;
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te.innerAttrs = 0;
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te.outerAttrs = bits(texcb, 1, 0);
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break;
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case 5: // Reserved
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panic("Reserved texcb value!\n");
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break;
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case 6: // Implementation Defined
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panic("Implementation-defined texcb value!\n");
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break;
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case 7: // Outer and Inner Write-Back, Write-Allocate
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te.mtype = TlbEntry::Normal;
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te.shareable = s;
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te.innerAttrs = 5;
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te.outerAttrs = 1;
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break;
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case 8: // Non-shareable Device
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te.nonCacheable = true;
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te.mtype = TlbEntry::Device;
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te.shareable = false;
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te.innerAttrs = 3;
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te.outerAttrs = 0;
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break;
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case 9 ... 15: // Reserved
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panic("Reserved texcb value!\n");
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break;
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case 16 ... 31: // Cacheable Memory
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te.mtype = TlbEntry::Normal;
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te.shareable = s;
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if (bits(texcb, 1,0) == 0 || bits(texcb, 3,2) == 0)
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te.nonCacheable = true;
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te.innerAttrs = bits(texcb, 1, 0);
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te.outerAttrs = bits(texcb, 3, 2);
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break;
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default:
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panic("More than 32 states for 5 bits?\n");
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}
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} else {
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assert(tc);
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PRRR prrr = tc->readMiscReg(MISCREG_PRRR);
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NMRR nmrr = tc->readMiscReg(MISCREG_NMRR);
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DPRINTF(TLBVerbose, "memAttrs PRRR:%08x NMRR:%08x\n", prrr, nmrr);
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uint8_t curr_tr = 0, curr_ir = 0, curr_or = 0;
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switch(bits(texcb, 2,0)) {
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case 0:
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curr_tr = prrr.tr0;
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curr_ir = nmrr.ir0;
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curr_or = nmrr.or0;
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outer_shareable = (prrr.nos0 == 0);
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break;
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case 1:
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curr_tr = prrr.tr1;
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curr_ir = nmrr.ir1;
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curr_or = nmrr.or1;
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outer_shareable = (prrr.nos1 == 0);
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break;
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case 2:
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curr_tr = prrr.tr2;
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curr_ir = nmrr.ir2;
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curr_or = nmrr.or2;
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outer_shareable = (prrr.nos2 == 0);
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break;
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case 3:
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curr_tr = prrr.tr3;
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curr_ir = nmrr.ir3;
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curr_or = nmrr.or3;
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outer_shareable = (prrr.nos3 == 0);
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break;
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case 4:
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curr_tr = prrr.tr4;
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curr_ir = nmrr.ir4;
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curr_or = nmrr.or4;
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outer_shareable = (prrr.nos4 == 0);
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break;
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case 5:
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curr_tr = prrr.tr5;
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curr_ir = nmrr.ir5;
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curr_or = nmrr.or5;
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outer_shareable = (prrr.nos5 == 0);
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break;
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case 6:
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panic("Imp defined type\n");
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case 7:
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curr_tr = prrr.tr7;
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curr_ir = nmrr.ir7;
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curr_or = nmrr.or7;
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outer_shareable = (prrr.nos7 == 0);
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break;
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}
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switch(curr_tr) {
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case 0:
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DPRINTF(TLBVerbose, "StronglyOrdered\n");
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te.mtype = TlbEntry::StronglyOrdered;
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te.nonCacheable = true;
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te.innerAttrs = 1;
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te.outerAttrs = 0;
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te.shareable = true;
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break;
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case 1:
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DPRINTF(TLBVerbose, "Device ds1:%d ds0:%d s:%d\n",
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prrr.ds1, prrr.ds0, s);
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te.mtype = TlbEntry::Device;
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te.nonCacheable = true;
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te.innerAttrs = 3;
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te.outerAttrs = 0;
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if (prrr.ds1 && s)
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te.shareable = true;
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if (prrr.ds0 && !s)
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te.shareable = true;
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break;
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case 2:
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DPRINTF(TLBVerbose, "Normal ns1:%d ns0:%d s:%d\n",
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prrr.ns1, prrr.ns0, s);
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te.mtype = TlbEntry::Normal;
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if (prrr.ns1 && s)
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te.shareable = true;
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if (prrr.ns0 && !s)
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te.shareable = true;
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break;
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case 3:
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panic("Reserved type");
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}
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if (te.mtype == TlbEntry::Normal){
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switch(curr_ir) {
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case 0:
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te.nonCacheable = true;
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te.innerAttrs = 0;
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break;
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case 1:
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te.innerAttrs = 5;
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break;
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case 2:
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te.innerAttrs = 6;
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break;
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case 3:
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te.innerAttrs = 7;
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break;
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}
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switch(curr_or) {
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case 0:
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te.nonCacheable = true;
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te.outerAttrs = 0;
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break;
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case 1:
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te.outerAttrs = 1;
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break;
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case 2:
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te.outerAttrs = 2;
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break;
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case 3:
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te.outerAttrs = 3;
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break;
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}
|
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}
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}
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DPRINTF(TLBVerbose, "memAttrs: shareable: %d, innerAttrs: %d, \
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outerAttrs: %d\n",
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te.shareable, te.innerAttrs, te.outerAttrs);
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|
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/** Formatting for Physical Address Register (PAR)
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* Only including lower bits (TLB info here)
|
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* PAR:
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* PA [31:12]
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* Reserved [11]
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* TLB info [10:1]
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* NOS [10] (Not Outer Sharable)
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* NS [9] (Non-Secure)
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* -- [8] (Implementation Defined)
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* SH [7] (Sharable)
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* Inner[6:4](Inner memory attributes)
|
|
* Outer[3:2](Outer memory attributes)
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* SS [1] (SuperSection)
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* F [0] (Fault, Fault Status in [6:1] if faulted)
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|
*/
|
|
te.attributes = (
|
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((outer_shareable ? 0:1) << 10) |
|
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// TODO: NS Bit
|
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((te.shareable ? 1:0) << 7) |
|
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(te.innerAttrs << 4) |
|
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(te.outerAttrs << 2)
|
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// TODO: Supersection bit
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// TODO: Fault bit
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);
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|
|
|
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}
|
|
|
|
void
|
|
TableWalker::doL1Descriptor()
|
|
{
|
|
DPRINTF(TLB, "L1 descriptor for %#x is %#x\n",
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currState->vaddr, currState->l1Desc.data);
|
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TlbEntry te;
|
|
|
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switch (currState->l1Desc.type()) {
|
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case L1Descriptor::Ignore:
|
|
case L1Descriptor::Reserved:
|
|
if (!currState->timing) {
|
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currState->tc = NULL;
|
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currState->req = NULL;
|
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}
|
|
DPRINTF(TLB, "L1 Descriptor Reserved/Ignore, causing fault\n");
|
|
if (currState->isFetch)
|
|
currState->fault =
|
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new PrefetchAbort(currState->vaddr, ArmFault::Translation0);
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else
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currState->fault =
|
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new DataAbort(currState->vaddr, 0, currState->isWrite,
|
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ArmFault::Translation0);
|
|
return;
|
|
case L1Descriptor::Section:
|
|
if (currState->sctlr.afe && bits(currState->l1Desc.ap(), 0) == 0) {
|
|
/** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is
|
|
* enabled if set, do l1.Desc.setAp0() instead of generating
|
|
* AccessFlag0
|
|
*/
|
|
|
|
currState->fault = new DataAbort(currState->vaddr,
|
|
currState->l1Desc.domain(), currState->isWrite,
|
|
ArmFault::AccessFlag0);
|
|
}
|
|
if (currState->l1Desc.supersection()) {
|
|
panic("Haven't implemented supersections\n");
|
|
}
|
|
te.N = 20;
|
|
te.pfn = currState->l1Desc.pfn();
|
|
te.size = (1<<te.N) - 1;
|
|
te.global = !currState->l1Desc.global();
|
|
te.valid = true;
|
|
te.vpn = currState->vaddr >> te.N;
|
|
te.sNp = true;
|
|
te.xn = currState->l1Desc.xn();
|
|
te.ap = currState->l1Desc.ap();
|
|
te.domain = currState->l1Desc.domain();
|
|
te.asid = currState->contextId;
|
|
memAttrs(currState->tc, te, currState->sctlr,
|
|
currState->l1Desc.texcb(), currState->l1Desc.shareable());
|
|
|
|
DPRINTF(TLB, "Inserting Section Descriptor into TLB\n");
|
|
DPRINTF(TLB, " - N:%d pfn:%#x size: %#x global:%d valid: %d\n",
|
|
te.N, te.pfn, te.size, te.global, te.valid);
|
|
DPRINTF(TLB, " - vpn:%#x sNp: %d xn:%d ap:%d domain: %d asid:%d nc:%d\n",
|
|
te.vpn, te.sNp, te.xn, te.ap, te.domain, te.asid,
|
|
te.nonCacheable);
|
|
DPRINTF(TLB, " - domain from l1 desc: %d data: %#x bits:%d\n",
|
|
currState->l1Desc.domain(), currState->l1Desc.data,
|
|
(currState->l1Desc.data >> 5) & 0xF );
|
|
|
|
if (!currState->timing) {
|
|
currState->tc = NULL;
|
|
currState->req = NULL;
|
|
}
|
|
tlb->insert(currState->vaddr, te);
|
|
|
|
return;
|
|
case L1Descriptor::PageTable:
|
|
Addr l2desc_addr;
|
|
l2desc_addr = currState->l1Desc.l2Addr() |
|
|
(bits(currState->vaddr, 19,12) << 2);
|
|
DPRINTF(TLB, "L1 descriptor points to page table at: %#x\n",
|
|
l2desc_addr);
|
|
|
|
// Trickbox address check
|
|
currState->fault = tlb->walkTrickBoxCheck(l2desc_addr, currState->vaddr,
|
|
sizeof(uint32_t), currState->isFetch, currState->isWrite,
|
|
currState->l1Desc.domain(), false);
|
|
|
|
if (currState->fault) {
|
|
if (!currState->timing) {
|
|
currState->tc = NULL;
|
|
currState->req = NULL;
|
|
}
|
|
return;
|
|
}
|
|
|
|
|
|
if (currState->timing) {
|
|
currState->delayed = true;
|
|
port->dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t),
|
|
&doL2DescEvent, (uint8_t*)&currState->l2Desc.data,
|
|
currState->tc->getCpuPtr()->ticks(1));
|
|
} else {
|
|
port->dmaAction(MemCmd::ReadReq, l2desc_addr, sizeof(uint32_t),
|
|
NULL, (uint8_t*)&currState->l2Desc.data,
|
|
currState->tc->getCpuPtr()->ticks(1));
|
|
doL2Descriptor();
|
|
}
|
|
return;
|
|
default:
|
|
panic("A new type in a 2 bit field?\n");
|
|
}
|
|
}
|
|
|
|
void
|
|
TableWalker::doL2Descriptor()
|
|
{
|
|
DPRINTF(TLB, "L2 descriptor for %#x is %#x\n",
|
|
currState->vaddr, currState->l2Desc.data);
|
|
TlbEntry te;
|
|
|
|
if (currState->l2Desc.invalid()) {
|
|
DPRINTF(TLB, "L2 descriptor invalid, causing fault\n");
|
|
if (!currState->timing) {
|
|
currState->tc = NULL;
|
|
currState->req = NULL;
|
|
}
|
|
if (currState->isFetch)
|
|
currState->fault =
|
|
new PrefetchAbort(currState->vaddr, ArmFault::Translation1);
|
|
else
|
|
currState->fault =
|
|
new DataAbort(currState->vaddr, currState->l1Desc.domain(),
|
|
currState->isWrite, ArmFault::Translation1);
|
|
return;
|
|
}
|
|
|
|
if (currState->sctlr.afe && bits(currState->l2Desc.ap(), 0) == 0) {
|
|
/** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is enabled
|
|
* if set, do l2.Desc.setAp0() instead of generating AccessFlag0
|
|
*/
|
|
|
|
currState->fault =
|
|
new DataAbort(currState->vaddr, 0, currState->isWrite,
|
|
ArmFault::AccessFlag1);
|
|
|
|
}
|
|
|
|
if (currState->l2Desc.large()) {
|
|
te.N = 16;
|
|
te.pfn = currState->l2Desc.pfn();
|
|
} else {
|
|
te.N = 12;
|
|
te.pfn = currState->l2Desc.pfn();
|
|
}
|
|
|
|
te.valid = true;
|
|
te.size = (1 << te.N) - 1;
|
|
te.asid = currState->contextId;
|
|
te.sNp = false;
|
|
te.vpn = currState->vaddr >> te.N;
|
|
te.global = currState->l2Desc.global();
|
|
te.xn = currState->l2Desc.xn();
|
|
te.ap = currState->l2Desc.ap();
|
|
te.domain = currState->l1Desc.domain();
|
|
memAttrs(currState->tc, te, currState->sctlr, currState->l2Desc.texcb(),
|
|
currState->l2Desc.shareable());
|
|
|
|
if (!currState->timing) {
|
|
currState->tc = NULL;
|
|
currState->req = NULL;
|
|
}
|
|
tlb->insert(currState->vaddr, te);
|
|
}
|
|
|
|
void
|
|
TableWalker::doL1DescriptorWrapper()
|
|
{
|
|
currState = stateQueueL1.front();
|
|
currState->delayed = false;
|
|
|
|
DPRINTF(TLBVerbose, "L1 Desc object host addr: %p\n",&currState->l1Desc.data);
|
|
DPRINTF(TLBVerbose, "L1 Desc object data: %08x\n",currState->l1Desc.data);
|
|
|
|
DPRINTF(TLBVerbose, "calling doL1Descriptor for vaddr:%#x\n", currState->vaddr);
|
|
doL1Descriptor();
|
|
|
|
stateQueueL1.pop_front();
|
|
// Check if fault was generated
|
|
if (currState->fault != NoFault) {
|
|
currState->transState->finish(currState->fault, currState->req,
|
|
currState->tc, currState->mode);
|
|
|
|
pending = false;
|
|
nextWalk(currState->tc);
|
|
|
|
currState->req = NULL;
|
|
currState->tc = NULL;
|
|
currState->delayed = false;
|
|
|
|
}
|
|
else if (!currState->delayed) {
|
|
// delay is not set so there is no L2 to do
|
|
DPRINTF(TLBVerbose, "calling translateTiming again\n");
|
|
currState->fault = tlb->translateTiming(currState->req, currState->tc,
|
|
currState->transState, currState->mode);
|
|
|
|
pending = false;
|
|
nextWalk(currState->tc);
|
|
|
|
currState->req = NULL;
|
|
currState->tc = NULL;
|
|
currState->delayed = false;
|
|
delete currState;
|
|
} else {
|
|
// need to do L2 descriptor
|
|
stateQueueL2.push_back(currState);
|
|
}
|
|
currState = NULL;
|
|
}
|
|
|
|
void
|
|
TableWalker::doL2DescriptorWrapper()
|
|
{
|
|
currState = stateQueueL2.front();
|
|
assert(currState->delayed);
|
|
|
|
DPRINTF(TLBVerbose, "calling doL2Descriptor for vaddr:%#x\n",
|
|
currState->vaddr);
|
|
doL2Descriptor();
|
|
|
|
// Check if fault was generated
|
|
if (currState->fault != NoFault) {
|
|
currState->transState->finish(currState->fault, currState->req,
|
|
currState->tc, currState->mode);
|
|
}
|
|
else {
|
|
DPRINTF(TLBVerbose, "calling translateTiming again\n");
|
|
currState->fault = tlb->translateTiming(currState->req, currState->tc,
|
|
currState->transState, currState->mode);
|
|
}
|
|
|
|
|
|
stateQueueL2.pop_front();
|
|
pending = false;
|
|
nextWalk(currState->tc);
|
|
|
|
currState->req = NULL;
|
|
currState->tc = NULL;
|
|
currState->delayed = false;
|
|
|
|
delete currState;
|
|
currState = NULL;
|
|
}
|
|
|
|
void
|
|
TableWalker::nextWalk(ThreadContext *tc)
|
|
{
|
|
if (pendingQueue.size())
|
|
schedule(doProcessEvent, tc->getCpuPtr()->nextCycle(curTick()+1));
|
|
}
|
|
|
|
|
|
|
|
ArmISA::TableWalker *
|
|
ArmTableWalkerParams::create()
|
|
{
|
|
return new ArmISA::TableWalker(this);
|
|
}
|
|
|